CN111583851A - Grid driving circuit and driving method thereof - Google Patents
Grid driving circuit and driving method thereof Download PDFInfo
- Publication number
- CN111583851A CN111583851A CN202010467365.0A CN202010467365A CN111583851A CN 111583851 A CN111583851 A CN 111583851A CN 202010467365 A CN202010467365 A CN 202010467365A CN 111583851 A CN111583851 A CN 111583851A
- Authority
- CN
- China
- Prior art keywords
- data
- frame
- buffer unit
- value
- grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention provides a grid driving circuit and a driving method thereof, which relate to the technical field of panel display, wherein the grid driving circuit is connected with a time schedule controller and comprises a shift register unit and a data buffer unit, wherein the data buffer unit is used for storing register values of each frame of data needing to update the horizontal lines of pixels; when each frame of data is ended, the time schedule controller compares the next frame of data to be updated with the currently input frame of data to obtain the value of a register of the next frame of data needing to update the horizontal line of the pixel, and the time schedule controller inputs a data signal and a clock signal to the data buffer unit for storing the value; the value in the shift register unit and the value in the data buffer unit are input to the level converter unit after passing through the AND gate, and the level converter unit outputs a corresponding high-frequency pulse signal through the output buffer unit to control the opening time of the corresponding gate; in each frame of grid scanning, pixels needing to be updated are charged, and pixels not needing to be updated are not charged.
Description
Technical Field
The invention belongs to the technical field of panel display, and particularly relates to a gate driving circuit and a driving method thereof.
Technical Field
In the conventional gate driving circuit, the gate is sequentially turned on from top to bottom or from bottom to top row by row every frame, the scanning frequency is fixed, and the charging time of each horizontal line to the pixel is fixed.
The conventional gate driving circuit adopts a sequential scanning manner, and the shift register unit inside the gate driving circuit module inputs various control signals (CPV, L/R, etc.), and fig. 1 is a driving timing diagram of the conventional gate driving circuit, in which an STV1 signal provides a signal that the gate first row is opened, and the CPV signal output by the timing controller TCON changes the register value in the shift register at its rising edge. At the rising edge of each CPV signal, the value 1 in the shift register is sequentially transferred downward, and the position where the original value is 1 needs to be filled with the value 0 in the transfer process. When the value is changed to 1, the corresponding OUTPUT (Out 1-Out 7 are illustrated in fig. 1) changes from a low frequency pulse signal to a high frequency pulse signal; when the value is changed to 0, the corresponding OUTPUT is changed from the high frequency pulse signal to the low frequency pulse signal. Since the OUTPUT frequency duty ratio of the CPV is the same, and the pulse width of OUTPUT is the same, that is, the on time of each gate is the same, the charging time of the pixel on each gate is fixed to be the same.
Such a gate scan driving circuit may cause the following disadvantages: firstly, the charging time of each row of pixels is fixed by sequential scanning, and when the method is applied to a product with high refresh rate and high resolution, the charging time is insufficient, so that the pixel charging rate is insufficient, and the product cannot be developed and produced in quantity; secondly, each pixel can be repeatedly charged in each frame of picture, and the waste of power consumption exists.
Disclosure of Invention
The invention provides a grid driving circuit and a driving method thereof.A data buffer unit is additionally arranged in the grid driving circuit, and a timing controller is matched to charge pixels in a differential manner in the grid scanning process of each frame of data, so that the charging of local pixels is realized and the driving power consumption of a display is reduced when each frame of picture is scanned.
The technical scheme of the invention is as follows:
the invention discloses a grid drive circuit, which is connected with a time schedule controller and comprises:
the pixel updating circuit comprises an input buffer unit, a shift register unit, a data buffer unit, a level converter unit and an output buffer unit which are connected in sequence, wherein the data buffer unit is used for storing register values of each frame of data, which need to update the horizontal lines of pixels;
when each frame of data is ended, the time schedule controller compares the next frame of data to be updated with the currently input frame of data to obtain the corresponding temporary register value of the next frame of data needing to update the horizontal line of the pixel, and the time schedule controller inputs a data signal and a clock signal to the data buffer unit for storing the value;
the value in the shift register unit and the value in the data buffer unit are input to the level converter unit after passing through the AND gate, and the level converter unit outputs a corresponding high-frequency pulse signal through the output buffer unit to control the opening time of the corresponding gate; in each frame of grid scanning, pixels needing to be updated are charged, and pixels not needing to be updated are not charged.
Preferably, the clock signal output by the timing controller adopts a variable frequency timing.
Preferably, the clock signal frequency-converts the output frequency of each frame of the output gate, i.e.: in each frame grid, the scanning time of the grid of the horizontal line where the pixel charging is required to be started is longer than that of the grid of the horizontal line where the pixel charging is not required to be started.
Preferably, the timing controller has a data transmission interface which inputs a value to the data buffer unit through a data signal and a clock signal.
Preferably, the data transmission interface is selected from the group consisting of TTL, LVDS, and Point to Point.
The invention also discloses a driving method, which comprises the following steps:
s1: the time schedule controller compares the next frame data to be updated with the currently input frame data line by line, if the data of the same horizontal line are completely consistent, the grid of the horizontal line of the next frame is not opened, and the value of a temporary storage corresponding to the horizontal line in the data buffer unit is set as 0; otherwise, executing the next step;
s2: opening the grid of the horizontal line of the next frame, and setting the value of a temporary storage corresponding to the horizontal line in the data buffer unit as 1;
s3: in each frame, the shift register is sequentially scanned downward, and when the value in the shift register unit and the value in the data buffer unit are both 1, the output buffer unit outputs a high voltage.
Preferably, the clock signal output by the timing controller adopts a variable frequency timing.
Preferably, the clock signal frequency-converts the output frequency of each frame of the output gate, i.e.: in each frame grid, the scanning time of the grid of the horizontal line where the pixel charging is required to be started is longer than that of the grid of the horizontal line where the pixel charging is not required to be started.
The invention can bring at least one of the following beneficial effects:
according to the invention, the data buffer unit is additionally arranged in the grid drive circuit and is used for storing the horizontal line of the pixel to be updated obtained after the comparison of two adjacent frames of data, and then the pixel is charged in a different manner in the grid scanning process of each frame of data, namely the pixel to be updated is charged, and the pixel which does not need to be updated is not charged; meanwhile, the variable-frequency CPV time sequence is matched, so that the charging time of the pixels needing to be updated is effectively increased, and the problem of insufficient charging of the pixel capacitor at the end of scanning is solved. The invention provides a non-sequential grid driving circuit, which is matched with a timing sequence controller, so that the local pixels are charged when each frame of picture is scanned, and the driving power consumption of a display is greatly reduced.
Drawings
The present invention will be further described in the following detailed description of preferred embodiments, which is to be read in connection with the accompanying drawings.
Fig. 1 is a driving timing diagram of a conventional gate driving circuit;
FIG. 2 is a schematic diagram of an internal module of the gate driving circuit according to the present invention;
FIG. 3 is a schematic diagram of the connection between the shift register unit and the data buffer unit according to the present invention;
FIG. 4 is a timing diagram of the output of the data signal and the clock signal in the data buffer unit according to the present invention;
FIG. 5 is a schematic diagram of an embodiment of an internal module driver of the gate driving circuit according to the present invention;
FIG. 6 is a driving timing diagram of the driving of the internal module of the gate driving circuit according to the embodiment of the present invention;
fig. 7 is a timing diagram of the variable frequency driving employed by the gate driving circuit of the present invention.
Detailed Description
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will be made with reference to the accompanying drawings. It is obvious that the drawings in the following description are only some examples of the invention, and that for a person skilled in the art, other drawings and embodiments can be derived from them without inventive effort.
For the sake of simplicity, the drawings only schematically show the parts relevant to the present invention, and they do not represent the actual structure as a product. In addition, in order to make the drawings concise and understandable, components having the same structure or function in some of the drawings are only schematically illustrated or only labeled. In this document, "one" means not only "only one" but also a case of "more than one".
The technical solution of the present invention is described in detail with specific examples below.
The invention provides a non-sequential gate driving circuit, which is connected with a time schedule controller, as shown in fig. 2, the gate driving circuit comprises: an input buffer unit, a shift register unit, a data buffer unit, a level shifter unit and an output buffer unit connected in sequence; the data buffer unit is used for storing register values of each frame of data needing to update the horizontal lines of the pixels, the input buffer unit is connected with the time schedule controller, and the time schedule controller outputs signals CPV, L/R, STV1, STV2, OE and XAO to the input buffer unit.
When each frame of Data is ended, the time schedule controller compares the next frame of Data to be updated with the currently input frame of Data to obtain the register value of the horizontal line of the pixel to be updated of the corresponding next frame of Data, and then the time schedule controller inputs the register value Data of the horizontal line of the pixel to be updated into the Data buffer unit by using the Data transmission interface through the Data signal Data and the Clock signal Clock so as to facilitate the Data buffer unit to store the Data.
As shown in fig. 3, the values in the shift register unit and the data buffer unit are input to the level shifter unit after passing through the and gate, and the level shifter unit outputs a corresponding pulse signal through the output buffer unit to control the gate on time; in each frame of grid scanning, pixels needing to be updated are charged, and pixels not needing to be updated are not charged. Each frame of picture can not repeatedly charge each pixel, and the phenomenon of power consumption waste does not exist.
In order to perform non-sequential pixel charging update on pictures with difference between two adjacent frames, a data buffer unit is additionally arranged in a grid drive circuit and is used for storing and comparing the values of a temporary storage of a horizontal line of pixels to be updated, which are obtained after the data of the two adjacent frames, and then the pixels of each line are charged with difference in the grid scanning process of each frame of data, namely the pixels to be updated are charged, and the pixels which do not need to be updated are not charged. The data buffer unit writes data at the end of each frame without affecting the normal operation of the gate driving circuit.
After each frame of data is ended, the time schedule controller needs to compare the next frame of data to be updated with the currently input frame of data line by line, if the data of the same horizontal line are completely consistent, the grid electrode of the horizontal line of the next frame of data is not opened, and the value of a temporary storage corresponding to the horizontal line in the data buffer unit is set to be 0; if the data in the same horizontal line is not completely consistent, the gate of the horizontal line in the next frame is turned on, and the value of the register in the data buffer unit corresponding to the horizontal line is set to 1, that is: in the data buffer unit, when which row of pixels in the next frame data needs to be updated compared to the current frame data, the value of the register corresponding to the horizontal row in the data buffer unit is set to 1, and the value of the register corresponding to the horizontal row without pixels needing to be updated is set to 0. The invention firstly uses the time sequence controller to compare two frames of Data to obtain the value of the corresponding Data buffer unit, and then uses the Data transmission interface of the time sequence controller to input the Data signal Data and the Clock signal Clock into the Data buffer unit, namely, the value of the horizontal line temporary storage of the next frame of pixel to be updated is stored into the Data buffer unit. As shown in fig. 4, the Data buffer unit fills the register of the horizontal line of the pixel to be updated in the next frame with 1 and fills the register of the horizontal line of the pixel not to be updated with 0 at the end of each frame by the input Data signal Data and the Clock signal Clock.
The Data transmission interface of the timing controller can select a proper transmission interface according to the specific operation frequency of the Data signal Data and the Clock signal Clock, and the selectable range of the transmission interface is TTL (logic gate circuit), LVDS (low amplitude differential signaling), Point to Point (Point to Point), and the like. The resolution is 1920(H) × 1080(V), the refresh rate is 144Hz, and the number of vertical display frames is 40. The Clock frequency required by the data buffer unit can be roughly calculated as: 144 + 40/1080 + 4.35456MHz, the transmission interface can be selected as LVDS (LVDS transmission support rate is typically above 77 MHz).
At the same time, the value in the shift register unit is also input into the data buffer unit, the value in the shift register unit and the value in the data buffer unit are input into the level converter unit after passing through the AND gate, and then the output buffer unit outputs corresponding high-frequency pulse to control the opening time of the corresponding gate. The shift registers sequentially scan downwards, the numerical value 1 in the shift registers sequentially transfers downwards, and the position where the original numerical value is 1 is filled with the numerical value 0 in the transferring process. Only when the value in the shift register unit and the value in the data buffer unit are both 1, the output buffer unit will output high frequency pulses to turn on the gate lines to charge the pixels. FIG. 5 shows an embodiment, as shown in FIG. 5, the horizontal column of the pixel to be updated corresponding to the fifth column of the data buffer unit has a value of 1, when the shift register scans to the fifth column, the value of the shift register unit and the value of the data buffer unit are both 1, so only OUTPUT5 has a high frequency pulse signal, while the data buffer units in the remaining columns have values of 0, FIG. 6 shows a corresponding driving timing diagram, as shown in FIG. 6, the OUTPUT buffer unit only opens the gate in the fifth column OUTPUT, and the remaining columns do not operate.
Preferably, the Clock signal Clock output by the timing controller may adopt a variable frequency CPV timing, as shown in fig. 7, the Clock signal Clock varies the output frequency of each frame of the output gate, that is: in each frame gate, the scan time T2 of the gate of the horizontal line where pixel charging is required to be turned on is greater than the scan time T1 of the gate of the horizontal line where pixel charging is not required to be turned on. The charging time of the scanning time T2 for the pixel is obviously longer than the fixed charging time of the pixel by the prior sequential scanning driving circuit, and for the product with high refresh rate and high resolution, the charging time of the pixel can be effectively increased by adjusting the Clock signal Clock output time sequence, thereby solving the problem of insufficient charging of the pixel capacitor at the end of scanning.
The invention also discloses a driving method of the grid driving circuit, which comprises the following steps:
s1: the time schedule controller compares the next frame data to be updated with the currently input frame data line by line, if the data of the same horizontal line are completely consistent, the grid of the horizontal line of the next frame is not opened, and the value of a temporary storage corresponding to the horizontal line in the data buffer unit is set as 0; otherwise, executing the next step;
s2: opening the grid of the horizontal line of the next frame, and setting the value of a temporary storage corresponding to the horizontal line in the data buffer unit as 1;
s3: in each frame, the shift register is sequentially scanned downward, and when the value in the shift register unit and the value in the data buffer unit are both 1, the output buffer unit outputs a high voltage.
Preferably, the clock signal of the present invention adopts a variable frequency CPV timing, and the clock signal varies the output frequency of each frame of the output gate, that is: in each frame gate, the scan time T2 of the gate of the horizontal line where pixel charging is required to be turned on is greater than the scan time T1 of the gate of the horizontal line where pixel charging is not required to be turned on. .
According to the invention, the data buffer unit is additionally arranged in the grid drive circuit and is used for storing the horizontal line of the pixel to be updated obtained after the comparison of two adjacent frames of data, and then the pixel is charged in a different manner in the grid scanning process of each frame of data, namely the pixel to be updated is charged, and the pixel which does not need to be updated is not charged; meanwhile, the variable-frequency CPV time sequence is matched, so that the charging time of the pixels needing to be updated is effectively increased, and the problem of insufficient charging of the pixel capacitor at the end of scanning is solved. The invention provides a non-sequential grid driving circuit, which is matched with a timing sequence controller, so that the local pixels are charged when each frame of picture is scanned, and the driving power consumption of a display is greatly reduced.
It should be noted that the above mentioned embodiments are only preferred embodiments of the present invention, but the present invention is not limited to the details of the above embodiments, and it should be noted that, for those skilled in the art, it is possible to make various modifications and amendments within the technical concept of the present invention without departing from the principle of the present invention, and various modifications, amendments and equivalents of the technical solution of the present invention should be regarded as the protection scope of the present invention.
Claims (8)
1. A gate driving circuit connected to a timing controller, comprising:
the pixel updating circuit comprises an input buffer unit, a shift register unit, a data buffer unit, a level converter unit and an output buffer unit which are connected in sequence, wherein the data buffer unit is used for storing register values of each frame of data, which need to update the horizontal lines of pixels;
when each frame of data is ended, the time schedule controller compares the next frame of data to be updated with the currently input frame of data to obtain the corresponding temporary register value of the next frame of data needing to update the horizontal line of the pixel, and the time schedule controller inputs a data signal and a clock signal to the data buffer unit for storing the value;
the value in the shift register unit and the value in the data buffer unit are input to the level converter unit after passing through the AND gate, and the level converter unit outputs a corresponding high-frequency pulse signal through the output buffer unit to control the opening time of the corresponding gate; in each frame of grid scanning, pixels needing to be updated are charged, and pixels not needing to be updated are not charged.
2. The gate driving circuit of claim 1, wherein the clock signal outputted from the timing controller is frequency-converted.
3. A gate drive circuit as claimed in claim 2, wherein the clock signal frequency converts the output frequency of each frame of the output gate by: in each frame grid, the scanning time of the grid of the horizontal line where the pixel charging is required to be started is longer than that of the grid of the horizontal line where the pixel charging is not required to be started.
4. The gate driving circuit of claim 1, wherein the timing controller has a data transfer interface for inputting a value to the data buffer unit by a data signal and a clock signal.
5. The gate driving circuit of claim 4, wherein the data transmission interface is selected from a range including TTL, LVDS and Point to Point.
6. The driving method of the gate driving circuit according to claim 1, comprising the steps of:
s1: the time schedule controller compares the next frame data to be updated with the currently input frame data line by line, if the data of the same horizontal line are completely consistent, the grid of the horizontal line of the next frame is not opened, and the value of a temporary storage corresponding to the horizontal line in the data buffer unit is set as 0; otherwise, executing the next step;
s2: opening the grid of the horizontal line of the next frame, and setting the value of a temporary storage corresponding to the horizontal line in the data buffer unit as 1;
s3: in each frame, the shift register is sequentially scanned downward, and when the value in the shift register unit and the value in the data buffer unit are both 1, the output buffer unit outputs a high voltage.
7. The driving method as claimed in claim 6, wherein the clock signal outputted from the timing controller adopts a variable frequency timing.
8. The driving method according to claim 6, wherein the clock signal frequency-converts the output frequency of each frame of the output gate by: in each frame grid, the scanning time of the grid of the horizontal line where the pixel charging is required to be started is longer than that of the grid of the horizontal line where the pixel charging is not required to be started.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010467365.0A CN111583851A (en) | 2020-05-28 | 2020-05-28 | Grid driving circuit and driving method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010467365.0A CN111583851A (en) | 2020-05-28 | 2020-05-28 | Grid driving circuit and driving method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111583851A true CN111583851A (en) | 2020-08-25 |
Family
ID=72125512
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010467365.0A Pending CN111583851A (en) | 2020-05-28 | 2020-05-28 | Grid driving circuit and driving method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111583851A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112687222A (en) * | 2020-12-28 | 2021-04-20 | 北京大学 | Display method, device, electronic equipment and medium based on pulse signal |
| CN114550636A (en) * | 2022-03-08 | 2022-05-27 | 北京奕斯伟计算技术有限公司 | Control method of data driver and time sequence controller and electronic equipment |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103137081A (en) * | 2011-11-22 | 2013-06-05 | 上海天马微电子有限公司 | Display panel gate drive circuit and display screen |
| CN104766577A (en) * | 2015-04-08 | 2015-07-08 | 合肥京东方光电科技有限公司 | Time sequence controller, driving control method, gate driving circuit and method |
| CN106251804A (en) * | 2016-09-30 | 2016-12-21 | 京东方科技集团股份有限公司 | Shift register cell, driving method, gate driver circuit and display device |
| CN106898325A (en) * | 2017-04-27 | 2017-06-27 | 南京中电熊猫平板显示科技有限公司 | Liquid crystal display faceplate device and its driving method |
| CN109064967A (en) * | 2018-10-31 | 2018-12-21 | 京东方科技集团股份有限公司 | A kind of control circuit and its driving method, grid drive chip, detection device |
-
2020
- 2020-05-28 CN CN202010467365.0A patent/CN111583851A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103137081A (en) * | 2011-11-22 | 2013-06-05 | 上海天马微电子有限公司 | Display panel gate drive circuit and display screen |
| CN104766577A (en) * | 2015-04-08 | 2015-07-08 | 合肥京东方光电科技有限公司 | Time sequence controller, driving control method, gate driving circuit and method |
| CN106251804A (en) * | 2016-09-30 | 2016-12-21 | 京东方科技集团股份有限公司 | Shift register cell, driving method, gate driver circuit and display device |
| CN106898325A (en) * | 2017-04-27 | 2017-06-27 | 南京中电熊猫平板显示科技有限公司 | Liquid crystal display faceplate device and its driving method |
| CN109064967A (en) * | 2018-10-31 | 2018-12-21 | 京东方科技集团股份有限公司 | A kind of control circuit and its driving method, grid drive chip, detection device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112687222A (en) * | 2020-12-28 | 2021-04-20 | 北京大学 | Display method, device, electronic equipment and medium based on pulse signal |
| US11862053B2 (en) | 2020-12-28 | 2024-01-02 | Spike Vision (Beijing) Technology Co., Ltd. | Display method based on pulse signals, apparatus, electronic device and medium |
| CN114550636A (en) * | 2022-03-08 | 2022-05-27 | 北京奕斯伟计算技术有限公司 | Control method of data driver and time sequence controller and electronic equipment |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP3226235B1 (en) | Display apparatus | |
| EP3832637A1 (en) | Shift register unit and driving method thereof, gate driving circuit and display device | |
| CN101369460B (en) | Shift buffer | |
| US10332466B2 (en) | Method of driving display panel and display apparatus for performing the same | |
| US20010033278A1 (en) | Display device driving circuit, driving method of display device, and image display device | |
| CN103280205B (en) | Display device, time schedule controller and method for displaying image | |
| CN109559706B (en) | Display driving circuit and display device | |
| CN107507597A (en) | Image display panel and grid drive circuit thereof | |
| CN102778798B (en) | Liquid crystal display panel and display driving method | |
| CN101178879B (en) | Display panel of LCD device and drive method thereof | |
| CN100555399C (en) | The driver that is used for LCD | |
| US20070176881A1 (en) | Driving circuit for driving liquid crystal display device and method thereof | |
| CN103155027B (en) | Display device | |
| US20210150969A1 (en) | Shift Register Unit, Gate Driving Circuit, Display Device, and Driving Method | |
| CN106898325A (en) | Liquid crystal display faceplate device and its driving method | |
| CN111583851A (en) | Grid driving circuit and driving method thereof | |
| US20210241673A1 (en) | Gate driving unit, gate driving method, gate driving circuit, display panel and display device | |
| CN114974163B (en) | Scanning driving circuit, array substrate and display panel | |
| CN109599070A (en) | Liquid crystal display device and its control method | |
| CN101447232B (en) | Shift buffer of pre-pull-down forward stage surge | |
| CN103680377A (en) | Gate shift register and flat panel display using the same | |
| JP3090922B2 (en) | Flat display device, array substrate, and method of driving flat display device | |
| US5892495A (en) | Scanning circuit and image display apparatus | |
| KR100806907B1 (en) | Liquid crystal display and driving method thereof | |
| CN105931607A (en) | Driving method of display panel and liquid crystal display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20200827 Address after: No.7 Tianyou Road, Qixia District, Nanjing City, Jiangsu Province Applicant after: NANJING CEC PANDA LCD TECHNOLOGY Co.,Ltd. Address before: Nanjing Crystal Valley Road in Qixia District of Nanjing City Tianyou 210033 Jiangsu province No. 7 Applicant before: NANJING CEC PANDA LCD TECHNOLOGY Co.,Ltd. Applicant before: NANJING CEC PANDA FPD TECHNOLOGY Co.,Ltd. Applicant before: NANJING HUADONG ELECTRONICS INFORMATION & TECHNOLOGY Co.,Ltd. |
|
| TA01 | Transfer of patent application right | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20200825 |
|
| WD01 | Invention patent application deemed withdrawn after publication |