CN111581900A - TFPG (pulse train generator) -based general processing module fault modeling method for avionics system - Google Patents
TFPG (pulse train generator) -based general processing module fault modeling method for avionics system Download PDFInfo
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Abstract
The embodiment of the invention discloses a fault modeling method for a general processing module of an avionics system based on TFPG, which comprises the following steps: analyzing the fault mode of the general processing module, and determining the fault mode and the propagation effect of the general processing module; fault modeling a general processing module based on a time fault propagation map (TFPG), the fault modeling comprising: fault modeling of a universal module level and fault modeling of a functional circuit level, wherein the fault modeling of the universal module level is used for describing fault or failure behaviors at the module level, and the fault modeling of the functional circuit level is used for describing fault behaviors at the functional circuit level; and generating a fault model file, and importing the fault model formed by modeling into avionic system health management software as a basic fault library for avionic fault diagnosis. The technical scheme provided by the embodiment of the invention provides fault diagnosis support for realizing the health management of the avionics system, thereby improving the running reliability and fault tolerance of the avionics system.
Description
Technical Field
The application relates to the technical field of health management of a comprehensive modular avionics system, in particular to a fault modeling method for a general processing module of an avionics system based on a TFPG (pulse width modulation) generator.
Background
In the joint standardization Avionics architecture council (advanced architecture council, ASAAC) specification, a comprehensive modular Avionics system is defined as a plurality of comprehensive functional areas, an Avionics function is completed through internal logical functional partitions, and each functional partition comprises a plurality of resource modules for bearing specific Avionics tasks. The resource module level is a set of bottom layer physical hardware, and each avionic task runs on the resource module level in a software application mode through a standardized general processing module, so that the integration of maximum avionic functions and the sharing of avionic resources are realized.
Disclosure of Invention
In order to solve the technical problem, an embodiment of the present invention provides a time failure propagation map (TFPG) -based method for modeling a failure of a general processing module of an avionics system, which provides a failure diagnosis support for implementing health management of the avionics system, thereby improving the reliability and fault tolerance of the operation of the avionics system.
The embodiment of the invention provides a fault modeling method for a general processing module of an avionics system based on TFPG, which comprises the following steps:
analyzing the fault mode of the general processing module, and determining the fault mode and the propagation effect of the general processing module;
fault modeling is carried out on the general processing module based on a time fault propagation diagram TFPG, and the fault modeling based on the TFPG comprises the following steps: fault modeling at a generic module level for describing the behavior of a fault or failure at a module level and fault modeling at a functional circuit level for describing the behavior of a fault at a functional circuit level;
and generating a fault model file, and importing the fault model formed by modeling into avionic system health management software as a basic fault library for avionic fault diagnosis.
Optionally, in the method for modeling a fault of a TFPG-based general processing module of an avionics system, the analyzing the fault mode of the general processing module includes:
and fault modeling is carried out on the general processing module, and the fault mode of each functional circuit and the influence of the fault mode on the general processing module are determined by analyzing each functional circuit in the general processing module.
Optionally, in the method for modeling faults of a TFPG-based avionics system general processing module, the fault modeling based on the TFPG further includes:
defining parameters in a TFPG, wherein the TFPG is a directed graph with labels, nodes represent failure modes, and edges between the nodes capture the propagation of failure influence in a dynamic system along with the time; edges in the TFPG may be activated or deactivated according to a set of possible operating modes in the avionics system.
Optionally, in the method for modeling faults of a TFPG-based avionics system general processing module as described above, the TFPG is represented as a tuple G ═ (F, D, E, M, ET, EM, DC); wherein the content of the first and second substances,
f is a non-empty set of failure mode nodes;
d is a non-empty set of difference nodes;
m is a set of system modes;
e → Int is a map that associates each edge in E with a time interval;
EM E → P (M) is a map linking each edge in E to the set of patterns in M;
d → { AND, OR } is a map defining the type of each difference as AND OR.
Optionally, in the method for modeling a fault of a TFPG-based avionics system general processing module, the general processing module includes a multi-stage functional circuit; fault modeling of the generic module hierarchy, comprising:
and fault modeling is carried out on each stage of functional circuit in the general processing module, and the formed TFPG fault model of the general processing module comprises the fault mode of each stage of functional circuit, the generated alarm content and the fault propagation time.
Optionally, in the method for modeling faults of a TFPG-based avionics system generic processing module, the modeling process of fault modeling at a generic module level includes:
mapping the typical fault mode of the general processing module into a fault mode node;
the relational path of fault propagation is modeled as directed edges and [ a, b ] on each edge represents a time constraint between two nodes, where a, b represent the minimum and maximum propagation times of the fault on the fault propagation path represented by the edge, respectively.
Optionally, in the method for modeling faults of a TFPG-based avionics system general processing module as described above, the functional circuit includes a chip and other hardware modules; fault modeling at the functional circuit level, comprising:
modeling a specified function circuit to form a TFGP fault model of the specified function circuit, wherein the TFGP fault model of the specified function circuit comprises: specifying hardware faults, generated alarm content and fault propagation time in the functional circuit; wherein the alarm content is mapped to a failure mode in a TFPG failure model of the generic module.
Optionally, in the method for modeling a fault of a TFPG-based avionics system general processing module, the specified functional circuit is an ethernet circuit, and the ethernet circuit includes a network chip, a PHY, and a transformer;
by modeling the fault of the ethernet circuit, the TFPG fault model of the ethernet circuit is formed to include: chip, resistance and capacitance faults, generated alarm content and fault propagation time in the Ethernet circuit module.
Optionally, in the method for modeling a fault of a TFPG-based avionics system general processing module, the generating a fault model file includes:
the graphical fault model constructed through fault modeling based on the TFPG can be exported as an XML file or compiled into C/C + + codes and added into avionics system real-time fault diagnosis software.
The fault modeling method of the general processing module of the avionics system based on the TFPG provided by the embodiment of the invention mainly comprises a fault mode analysis process of the general processing module of the avionics system and a fault modeling process based on a time fault propagation diagram, wherein the fault mapping in the fault modeling process comprises the steps of mapping elements of fault analysis to TFPG model elements and mapping low-level influences to high-level fault modes, and typical fault modes and propagation effects obtained by fault mode analysis in the avionics system are associated and organized with avionic fault detection events in a TFPG model mode. The embodiment of the invention combines the characteristics of the comprehensive modularized avionics system, constructs a fault model based on a time fault propagation diagram, realizes the fault diagnosis of the avionics system on the basis of the fault model, can realize the automatic fault detection, isolation and recovery of the avionics system, determines the total time of the fault by means of the detection capability of the sensor to the fault, and records and analyzes the time response of the fault. The embodiment of the invention can help a design engineer to find the problem of crossing the boundary of the subsystem and the design problem in an early stage, can support technicians and operators to determine faults, and improves the reliability of avionics products.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.
Fig. 1 is a flowchart of a fault modeling method for a TFPG-based general processing module of an avionics system according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a general module processing module according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a time fault propagation diagram according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a TFPG fault model of a general purpose processing module in accordance with an embodiment of the present invention;
fig. 5 is a schematic diagram of a TFPG fault model of an ethernet circuit according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
The steps illustrated in the flow charts of the figures may be performed in a computer system such as a set of computer-executable instructions. Also, while a logical order is shown in the flow diagrams, in some cases, the steps shown or described may be performed in an order different than here.
In order to meet the requirement of health management of an integrated modular avionics system, the invention provides an avionics system general module fault modeling method based on a Time Fault Propagation Graph (TFPG).
The following specific embodiments of the present invention may be combined, and the same or similar concepts or processes may not be described in detail in some embodiments.
Fig. 1 is a flowchart of a fault modeling method for a TFPG-based general processing module of an avionics system according to an embodiment of the present invention. The fault modeling method for the general processing module of the avionics system based on the TFPG provided by the embodiment of the invention comprises the following steps:
step 2, fault modeling is carried out on the general processing module based on the TFPG, and the fault modeling based on the TFPG comprises the following steps: fault modeling of a universal module level and fault modeling of a functional circuit level; the fault modeling of the universal module level is used for describing fault or failure behaviors at the module level, and the fault modeling of the functional circuit level is used for describing fault behaviors at the functional circuit level;
and 3, generating a fault model file, and importing the fault model formed by modeling into avionic system health management software as a basic fault library for avionic fault diagnosis.
Aiming at the fault diagnosis requirement of the general processing module of the comprehensive modularized avionics system, the embodiment of the invention organizes and associates the fault mode, the propagation effect and the detection event of the general processing module of the avionics system by adopting a time-based fault propagation diagram to form a fault model for real-time fault diagnosis.
In this embodiment of the present invention, the general processing module generally includes a multi-stage functional circuit, and the implementation manner of performing the failure mode analysis on the general processing module in step 1 may include:
and fault modeling is carried out on the general processing module, and the fault mode of each functional circuit and the influence of the fault mode on the general processing module are determined by analyzing each functional circuit in the general processing module.
Accordingly, the fault modeling of the generic module hierarchy in step 2 includes:
and fault modeling is carried out on each stage of functional circuit in the general processing module, and the formed TFPG fault model of the general processing module comprises the fault mode of each stage of functional circuit, the generated alarm content and the fault propagation time.
In practical application, the modeling process of fault modeling of the universal module hierarchy in step 2 includes:
step 21, mapping the typical fault mode of the general processing module into a fault mode node;
step 22, the relationship path of fault propagation is modeled as directed edges, and [ a, b ] on each edge represents the time constraint between two nodes, where a, b represent the minimum and maximum propagation time of the fault on the edge, i.e. the fault propagation path, respectively.
In embodiments of the present invention, the functional circuitry in the general processing module typically includes chips and other hardware modules; the implementation manner of the fault modeling of the functional circuit hierarchy in step 2 may include:
modeling a specified function circuit to form a TFPG fault model of the specified function circuit, wherein the TFGP model of the specified function circuit comprises the following steps: specifying hardware faults, generated alarm content and fault propagation time in the functional circuit; wherein the alarm content is mapped to a failure mode in a TFPG failure model of the generic module.
It should be noted that, in the embodiment of the present invention, before the fault modeling at the generic module level and the fault modeling at the functional circuit level, the method may further include:
defining parameters in a TFPG that is a labeled directed graph, wherein nodes represent failure modes, and edges between nodes capture the propagation of failure effects over time in a dynamic system; the edges in the TFPG may be activated or deactivated according to a set of possible operating modes in the avionics system.
The embodiment of the invention provides a fault modeling method of a general processing module of an avionics system based on a time fault propagation diagram, which mainly comprises a fault mode analysis process of the general processing module of the avionics system and a fault modeling process based on the time fault propagation diagram, wherein the fault mapping in the fault modeling process comprises the steps of mapping elements of fault analysis to TFPG model elements and mapping low-level influences to high-level fault modes, and typical fault modes and propagation effects obtained by the fault mode analysis in the avionics system are associated and organized with avionic fault detection events in a TFPG model mode, so that the fault modeling of the general processing module in the avionics system is realized, and real-time fault diagnosis is carried out on the basis of the typical fault modes and the propagation effects.
The fault modeling method for the general processing module of the avionics system based on the TFPG, provided by the embodiment of the invention, combines the characteristics of a comprehensive modularized avionics system, constructs a fault model based on a time fault propagation diagram, realizes the fault diagnosis of the avionics system on the basis of the fault model, can realize the automatic fault detection, isolation and recovery of the avionics system, determines the total time of fault occurrence by means of the detection capability of a sensor on the fault, and records and analyzes the time response of the fault. The embodiment of the invention can help a design engineer to find the problem of crossing the boundary of the subsystem and the design problem in an early stage, can support technicians and operators to determine faults, and improves the reliability of avionics products.
The fault modeling process and the fault model design of the avionics system general processing module are described in detail through specific embodiments.
(1) Analyzing the failure mode of the general processing module
And fault modeling is carried out on the general processing module, and the fault mode of each functional circuit and the influence of the fault mode on the general processing module are determined by analyzing each functional circuit in the general processing module. Fig. 2 is a schematic structural diagram of a general module processing module according to an embodiment of the present invention. It can be seen that a typical general-purpose modular processing module of an avionics system generally comprises the following functional circuits:
a) power supply circuit (DC-DC): converting the voltage input by an external direct current power supply into a direct current power supply required by a general processing module;
b) clock network circuit (CPU clock): the processor circuit needs clocks with different frequencies when working, and the clock circuit converts the crystal oscillator signal into clock signals with different frequencies;
c) processor circuit (CPU 0-2): namely the core circuit of the general processing module;
d) and a memory circuit: the storage circuit comprises two storage media, namely DDR and FLASH;
e) and a JTAG circuit: a Central Processing Unit (CPU) chip integrates a Joint Test Action Group (JATG) debugging technology, and the debugging of a processor core can be completed through a JATG interface;
f) and an Ethernet circuit: the method is mainly applied to an operating system and software debugging on the CPU;
g) PCI bus circuit
h) AFDX interface circuit
i) And an interface circuit: the device comprises a discrete magnitude interface circuit and an RS232/422 interface circuit;
j) test interface circuit
Each functional circuit also comprises a chip, a resistor, a capacitor and other devices. Table 1 below describes the effect on the overall general processing block after a typical functional circuit failure, i.e. the propagation path includes the failure mode and the effect.
TABLE 1
(2) Fault modeling of a general purpose processing module based on TFPG
A time fault propagation map (TFPG), as a causal model describing the behavior of system faults, can capture the spatio-temporal characteristics of fault propagation in dynamic systems, and can infer system faults based on events detected in real-time systems (e.g., BIT reports, alarms, mode switching). The fault modeling in the embodiment of the invention mainly comprises two parts of TFPG definition and a fault modeling process based on TFPG:
2-1, detailed definition of TFPG
The TFPG is a labeled directed graph, as shown in fig. 3, which is a schematic structural diagram of a time fault propagation graph according to an embodiment of the present invention, where nodes represent fault patterns, and the fault patterns are caused by faults or are differences and do not meet the influence of the fault patterns of the nominal condition. Edges between nodes in the graph capture the propagation of fault effects over time in a dynamic system. To represent fault propagation in a multi-mode (switching) system, edges in the graph model may be activated or deactivated according to a set of possible operating modes of the avionics system. Formally, TFPG is represented as the tuple G ═ (F, D, E, M, ET, EM, DC), where:
a) f is a non-empty set of failure mode nodes;
b) d is a non-empty set of difference nodes;
c)、
src (e) and dst (e) represent the source and destination nodes, respectively, of edge e, and set V contains n + m vertices, representing n failure modes and m differences.
d) And M is a set of system modes. At each moment t, the avionics system can only be in one mode;
e) e → Int is a map linking each edge in E to a time interval; the mapping ET links each edge E with the maximum and minimum propagation times of the fault propagation on this edge. For each edge E, we use the symbols e.tmin and e.tmax to represent the minimum and maximum times that the fault travels along edge E. That is, assuming that the propagating edge is active (activated), it takes at least (at most) e.tmin (e.tmax) time to propagate the fault from the source node to the target node.
f) EM E → P (M) is a map that relates each edge in E to the set of patterns in M, assuming that for any edge E ∈ E, there is a
The map EM associates each edge E ∈ E with a subset of the system mode in which a fault may propagate along the edge, therefore, propagation link E is enabled (active) in mode M ∈ M if and only if M ∈ EM (E).
g) D → { AND, OR } is a map defining the type of each difference as AND OR. The mapping DC defines the type of a given difference as AND OR. When the failure propagates to the parent node, a differencing node of the OR type will be activated. On the other hand, an AND diff node can only be activated when a fault propagates to the node from all its parents.
2-2 TFPG-based fault modeling process
Through failure mode analysis, the failure mode and its propagation effects of a typical general purpose processing module have been specified. The embodiment of the invention takes the main circuit of the general processing module as an example, explains the fault modeling process based on the TFPG, defines the fault mode of each functional circuit as fi, and generates the alarm as mdi. In order to meet the hierarchical fault description, the modeling process comprises fault modeling at a universal module level and fault modeling at a functional circuit level by combining the characteristics of the universal processing module of the avionics system. The fault modeling at the generic module level and the fault modeling at the functional circuit level are described in detail below, respectively:
1) fault modeling at generic module level
Fault modeling at the generic module level is used to describe the behavior of a fault or failure at the module level. In the modeling process, mapping the typical Fault mode of the general processing module into a Fault mode node, and expressing the Fault mode node by a Fault icon; the relational path of fault propagation is modeled as directed edges and [ a, b ] on each edge represents a time constraint between two nodes, where a, b represent the minimum and maximum propagation times of the fault on that edge, i.e., the fault propagation path, respectively. The fault modeling of the general processing module needs to model more than ten main functional circuits, and needs to analyze the influence of chips and main devices in the circuit on the general processing module, so that the general processing module has multiple levels and needs to model each level of functional circuits.
Fig. 4 is a schematic diagram of a TFPG fault model of a general processing module according to an embodiment of the present invention. In the figure, f1 represents the failure fault of the power supply circuit, and f 2-f 11 represent the failure faults of the clock network circuit, the processor circuit, the DDR, the FLASH, the JTAG circuit, the Ethernet circuit, the PCI bus circuit, the AFDX interface circuit, the interface circuit and the test interface circuit respectively. Since the fault effect of the general processing module is propagated very fast after the hardware of the general processing module fails, in the embodiment of the invention, the fault propagation time of the hardware is defined to be less than 0.01 second (S). The failure modes of the above failure propagation model are failures describing functional circuits, which in fact contain many chips and other hardware modules, and therefore, need to be modeled. The modeling manner of each functional circuit is described below by taking an ethernet circuit as an example.
2) Functional circuit level fault modeling
Fault modeling at the functional circuit level is used to describe fault behavior at the functional circuit level. The fault modeling ethernet circuit of the functional circuit in the embodiment of the present invention is described as an example. The ethernet circuit includes hardware modules such as a network chip, a PHY, and a transformer, and the fault modeling of the ethernet circuit needs to be mapped to the chip and the resistance-capacitance, the fault mode of the chip and the resistance-capacitance is defined as fi, and the generated alarms are PHY, XFMR, and CLK, as shown in fig. 5, which is a schematic diagram of a TFPG fault model of the ethernet circuit in the embodiment of the present invention.
In the figure, f1 to fn indicate failures such as chips, resistors, and capacitors in the ethernet circuit. The fault propagation time of the definition hardware is less than 0.01S. And for the functional circuit's three alarms are or relationship, any alarm generation would mean a network fault alarm. For example, for any fault from f1 to f3, an XFMR alarm is triggered, i.e., any fault on the left side in FIG. 5 will generate a corresponding alarm on the right side.
It should be noted that PHY, XFMR, and CLK in fig. 5 are relay effects, and nodes "ENE ERROR" and "No Effect" in fig. 5 are mapped to fi at the leftmost side in fig. 4, that is, the failure effects (including "ENE ERROR" and "No Effect") of the next hierarchy (i.e., functional circuit hierarchy) correspond to the failure modes in the previous hierarchy (general module hierarchy).
3) Generating a fault model file
After the construction of the multi-level TFPG model of the general processing module of the avionic system is completed, the fault model formed by modeling is imported into health management software of the avionic system as a basic fault library of avionic fault diagnosis. An engineer can export an XML file or compile the XML file into C/C + + codes through a graphical fault model constructed through fault modeling based on the TFPG, and the graphical fault model is added into avionic system real-time fault diagnosis software to provide a model data basis for subsequent TFPG reasoning and code generation.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (9)
1. A fault modeling method for a general processing module of an avionics system based on TFPG is characterized by comprising the following steps:
analyzing the fault mode of the general processing module, and determining the fault mode and the propagation effect of the general processing module;
fault modeling is carried out on the general processing module based on a time fault propagation diagram TFPG, and the fault modeling based on the TFPG comprises the following steps: fault modeling at a generic module level for describing the behavior of a fault or failure at a module level and fault modeling at a functional circuit level for describing the behavior of a fault at a functional circuit level;
and generating a fault model file, and importing the fault model formed by modeling into avionic system health management software as a basic fault library for avionic fault diagnosis.
2. The TFPG-based avionics system general processing module fault modeling method of claim 1, wherein the performing fault pattern analysis on the general processing module comprises:
and fault modeling is carried out on the general processing module, and the fault mode of each functional circuit and the influence of the fault mode on the general processing module are determined by analyzing each functional circuit in the general processing module.
3. The TFPG-based avionics system generic processing module fault modeling method of claim 1, further comprising:
defining parameters in a TFPG, wherein the TFPG is a directed graph with labels, nodes represent failure modes, and edges between the nodes capture the propagation of failure influence in a dynamic system along with the time; edges in the TFPG may be activated or deactivated according to a set of possible operating modes in the avionics system.
4. The TFPG-based avionics system generic processing module fault modeling method of claim 3, wherein the TFPG is represented as a tuple G ═ (F, D, E, M, ET, EM, DC); wherein the content of the first and second substances,
f is a non-empty set of failure mode nodes;
d is a non-empty set of difference nodes;
m is a set of system modes;
e → Int is a map that associates each edge in E with a time interval;
EM E → P (M) is a map linking each edge in E to the set of patterns in M;
d → { AND, OR } is a map defining the type of each difference as AND OR.
5. The TFPG-based avionics system general processing module fault modeling method of claim 4, wherein the general processing module comprises a multi-stage functional circuit; fault modeling of the generic module hierarchy, comprising:
and fault modeling is carried out on each stage of functional circuit in the general processing module, and the formed TFPG fault model of the general processing module comprises the fault mode of each stage of functional circuit, the generated alarm content and the fault propagation time.
6. The TFPG-based avionics system general processing module fault modeling method of claim 5, wherein the modeling process of fault modeling at the general module level comprises:
mapping the typical fault mode of the general processing module into a fault mode node;
the relational path of fault propagation is modeled as directed edges and [ a, b ] on each edge represents a time constraint between two nodes, where a, b represent the minimum and maximum propagation times of the fault on the fault propagation path represented by the edge, respectively.
7. The TFPG-based avionics system general processing module fault modeling method of claim 5, wherein the functional circuitry comprises chips and other hardware modules; fault modeling at the functional circuit level, comprising:
modeling a specified function circuit to form a TFGP fault model of the specified function circuit, wherein the TFGP fault model of the specified function circuit comprises: specifying hardware faults, generated alarm content and fault propagation time in the functional circuit; wherein the alarm content is mapped to a failure mode in a TFPG failure model of the generic module.
8. The TFPG-based avionics system general processing module fault modeling method of claim 7, wherein the designated function circuit is an ethernet circuit, the ethernet circuit including a network chip, a PHY, a transformer;
by modeling the fault of the ethernet circuit, the TFPG fault model of the ethernet circuit is formed to include: chip, resistance and capacitance faults, generated alarm content and fault propagation time in the Ethernet circuit module.
9. The TFPG-based avionics system general processing module fault modeling method according to any one of claims 1 to 8, wherein the generating of the fault model file comprises:
the graphical fault model constructed through fault modeling based on the TFPG can be exported as an XML file or compiled into C/C + + codes and added into avionics system real-time fault diagnosis software.
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| CN114218775A (en) * | 2021-12-06 | 2022-03-22 | 中国航空综合技术研究所 | Complex system task reliability test case design method under fault propagation model |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5546408A (en) * | 1994-06-09 | 1996-08-13 | International Business Machines Corporation | Hierarchical pattern faults for describing logic circuit failure mechanisms |
| EP0848156A2 (en) * | 1996-12-16 | 1998-06-17 | Toyota Jidosha Kabushiki Kaisha | Fuel vapor feed controlling apparatus for a lean burn type internal combustion engine |
| CN102945311A (en) * | 2012-10-08 | 2013-02-27 | 南京航空航天大学 | Method for diagnosing fault by functional fault directed graph |
| US20150142402A1 (en) * | 2013-11-18 | 2015-05-21 | The Boeing Company | Safety analysis of a complex system using component-oriented fault trees |
| CN110597726A (en) * | 2019-09-19 | 2019-12-20 | 中国商用飞机有限责任公司北京民用飞机技术研究中心 | Safety management method, device, equipment and storage medium for avionic system |
-
2020
- 2020-04-30 CN CN202010370730.6A patent/CN111581900B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5546408A (en) * | 1994-06-09 | 1996-08-13 | International Business Machines Corporation | Hierarchical pattern faults for describing logic circuit failure mechanisms |
| EP0848156A2 (en) * | 1996-12-16 | 1998-06-17 | Toyota Jidosha Kabushiki Kaisha | Fuel vapor feed controlling apparatus for a lean burn type internal combustion engine |
| CN102945311A (en) * | 2012-10-08 | 2013-02-27 | 南京航空航天大学 | Method for diagnosing fault by functional fault directed graph |
| US20150142402A1 (en) * | 2013-11-18 | 2015-05-21 | The Boeing Company | Safety analysis of a complex system using component-oriented fault trees |
| CN110597726A (en) * | 2019-09-19 | 2019-12-20 | 中国商用飞机有限责任公司北京民用飞机技术研究中心 | Safety management method, device, equipment and storage medium for avionic system |
Non-Patent Citations (2)
| Title |
|---|
| 徐文华等: "一种基于航电***架构模型的故障树自动建模方法", 《计算机工程与科学》 * |
| 贺若飞等: "无人机自主控制应用需求及研究发展分析", 《火力与指挥控制》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112677833A (en) * | 2021-01-18 | 2021-04-20 | 中车青岛四方机车车辆股份有限公司 | Rail vehicle shielding grounding system, wiring method thereof and rail vehicle |
| CN114218775A (en) * | 2021-12-06 | 2022-03-22 | 中国航空综合技术研究所 | Complex system task reliability test case design method under fault propagation model |
| CN114218775B (en) * | 2021-12-06 | 2023-11-28 | 中国航空综合技术研究所 | Complex system task reliability test case design method under fault propagation model |
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