CN111564457A - Array substrate, preparation method thereof and display panel - Google Patents

Array substrate, preparation method thereof and display panel Download PDF

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Publication number
CN111564457A
CN111564457A CN202010470538.4A CN202010470538A CN111564457A CN 111564457 A CN111564457 A CN 111564457A CN 202010470538 A CN202010470538 A CN 202010470538A CN 111564457 A CN111564457 A CN 111564457A
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layer
hole
conductive layer
metal wire
opposite
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CN111564457B (en
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付恒野
蔡惠洁
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Human Computer Interaction (AREA)
  • Position Input By Displaying (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

The invention relates to an array substrate, a preparation method thereof and a display panel. And transmitting a signal of a part of the first conductive layer opposite to the metal wire layer to another part of the first conductive layer opposite to the side wall of the through hole by using the second conductive layer. When the first conducting layer generates cracks at the included angle between the surface of the metal wire layer and the side wall of the through hole, signals of the metal wire layer can still be transmitted through the first conducting layer, the increase of lap joint impedance is avoided, and the abnormal touch phenomenon is avoided.

Description

Array substrate, preparation method thereof and display panel
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a preparation method thereof and a display panel.
Background
The display device can convert the data of the computer into various characters, numbers, symbols or visual images for display, and can input commands or data into the computer by using input tools such as a keyboard, and the display contents can be added, deleted and changed at any time by means of hardware and software of the system. Display devices are classified into plasma, liquid crystal, light emitting diode, cathode ray tube, and the like, according to the display device used.
Tft (thin Film transistor) is an abbreviation of thin Film transistor. The TFT type display screen is a mainstream display device in various notebook computers and desktop computers, and each liquid crystal pixel point on the display screen is driven by a thin film transistor integrated behind the pixel point, so the TFT type display screen is also a type of active matrix liquid crystal display device. The TFT type display screen is one of the best LCD color displays, and the TFT type display has the advantages of high responsivity, high brightness, high contrast ratio, etc., and the display effect thereof is close to that of the CRT type display.
The TFT substrate of the high resolution product has dense wiring in a pull line region (fanout) near the IC, including signal lines for implementing TP touch. In order to transmit the signal of the metal wire layer to the common electrode through the first conductive layer, a through hole needs to be arranged on the flat layer.
As shown in fig. 1, in the conventional design of the through hole 7, the first conductive layer 4 is overlapped on the metal wire layer 2 through the through hole 7, since the material of the first conductive layer 4 is ITO, and ITO is a hard film, the included angle between the surface of the metal wire layer 2 and the side wall of the through hole 7 is approximately a right angle, the first conductive layer 4 is easy to generate a crack 9 at the included angle, so that the overlap impedance is increased, and the signal of the metal wire layer 2 cannot be transmitted to the common electrode through the first conductive layer 4, thereby generating the abnormal touch phenomenon. In the prior art, the phenomenon that the first conducting layer 4 generates a crack 9 at the corner between the surface of the metal wire layer 2 and the side wall of the through hole is difficult to detect, and the crack can be found even in the complete machine state, so that the loss is serious. Therefore, a new array substrate is required to solve the above problems.
Disclosure of Invention
The invention aims to provide an array substrate, a preparation method thereof and a display panel, which can solve the problems that a first conducting layer in the existing array substrate is easy to generate cracks at an included angle between the surface of a metal wire layer and the side wall of a through hole, so that the lap joint impedance is increased, signals of the metal wire layer cannot be transmitted to a common electrode through the first conducting layer, and the abnormal touch phenomenon is generated.
In order to solve the above problems, the present invention provides an array substrate, including: a substrate; the metal wire layer is arranged on the substrate; the flat layer is arranged on the metal wire layer and the substrate; the through hole penetrates through the flat layer and is arranged opposite to the metal wire layer; the first conducting layer is arranged on the flat layer, extends into the through hole, is attached to the side wall of the through hole and is connected to the metal wire layer; the passivation layer is arranged on the first conductive layer and extends into the through hole; the through hole penetrates through the passivation layer and is arranged opposite to the side wall of the through hole and/or the metal wire layer; and a second conductive layer disposed in the via hole, connected to a portion of the first conductive layer opposite to the metal wire layer, and connected to another portion of the first conductive layer opposite to a sidewall of the via hole.
Further, the number of the through holes is more than two; a via hole is arranged opposite to the metal wire layer; the other via hole is arranged opposite to the side wall of the through hole.
Further, the second conductive layer is connected to the first conductive layer through one via hole and connected to the first conductive layer through another via hole.
Further, the via hole is arranged opposite to the side wall of the through hole and the metal wire layer.
Further, the second conductive layer is disposed in the via hole, attached to the first conductive layer, and extends from the hole wall on one side of the via hole to the hole wall on the other side.
In order to solve the above problems, the present invention further provides a method for manufacturing an array substrate, which includes the following steps: providing a substrate; preparing a metal wire layer on the substrate; preparing a flat layer on the metal wire layer and the substrate; penetrating through the flat layer to form a through hole, wherein the through hole is arranged opposite to the metal wire layer; preparing a first conductive layer on the flat layer, wherein the first conductive layer extends into the through hole, is attached to the side wall of the through hole and is connected to the metal wire layer; preparing a passivation layer on the first conductive layer, wherein the first conductive layer extends into the through hole; a through hole is formed through the passivation layer and is arranged opposite to the side wall of the through hole and/or the metal wire layer; and preparing a second conductive layer within the via hole, the second conductive layer being connected to a portion of the first conductive layer opposite to the metal line layer and to another portion of the first conductive layer opposite to the sidewall of the via hole.
Further, the step of forming a via hole through the passivation layer, wherein the via hole is disposed opposite to the sidewall of the through hole and/or the metal line layer, comprises: penetrating the passivation layer to form more than two through holes; a via hole is arranged opposite to the metal wire layer; the other via hole is arranged opposite to the side wall of the through hole.
Further, in the step of forming a via hole through the passivation layer, the via hole being disposed opposite to the sidewall of the through hole and/or the metal line layer, the via hole is disposed opposite to the sidewall of the through hole and the metal line layer.
Further, the through holes and the through holes are formed by etching.
In order to solve the above problems, the present invention further provides a display panel including the array substrate according to the present invention.
The invention has the advantages that: the invention relates to an array substrate, a preparation method thereof and a display panel. And transmitting a signal of a part of the first conductive layer opposite to the metal wire layer to another part of the first conductive layer opposite to the side wall of the through hole by using the second conductive layer. When the first conducting layer generates cracks at the included angle between the surface of the metal wire layer and the side wall of the through hole, signals of the metal wire layer can still be transmitted through the first conducting layer, the increase of lap joint impedance is avoided, and the abnormal touch phenomenon is avoided.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an array substrate in the prior art.
Fig. 2 is a schematic structural diagram of the array substrate of embodiment 1.
Fig. 3 is a schematic view of a through hole in an array substrate according to embodiment 1.
Fig. 4 is a schematic structural diagram of a via hole in the array substrate of embodiment 1.
Fig. 5 is a view showing a process of manufacturing an array substrate of example 1.
Fig. 6 is a schematic structural diagram of an array substrate in embodiment 2.
Fig. 7 is a schematic structural diagram of a via hole in the array substrate of embodiment 2.
Fig. 8 is a view showing a process of manufacturing an array substrate of example 2.
The components in the figure are identified as follows:
100. array substrate
1. Substrate 2, metal wire layer
3. Flat layer 4, first conductive layer
5. Passivation layer 6, second conductive layer
7. Through hole 8, via hole
9. Crack (crack)
81. First via 82 and second via
83. Third via hole
Detailed Description
The following detailed description of the preferred embodiments of the present invention is provided to enable those skilled in the art to make and use the present invention in a complete manner, and is provided for illustration of the technical disclosure of the present invention so that the technical disclosure of the present invention will be more clearly understood and appreciated by those skilled in the art how to implement the present invention. The present invention may, however, be embodied in many different forms of embodiment, and the scope of the present invention should not be construed as limited to the embodiment set forth herein, but rather construed as being limited only by the following description of the embodiment.
The directional terms used in the present invention, such as "up", "down", "front", "back", "left", "right", "inner", "outer", "side", etc., are only directions in the drawings, and are used for explaining and explaining the present invention, but not for limiting the scope of the present invention.
In the drawings, structurally identical elements are represented by like reference numerals, and structurally or functionally similar elements are represented by like reference numerals throughout the several views. In addition, the size and thickness of each component shown in the drawings are arbitrarily illustrated for convenience of understanding and description, and the present invention is not limited to the size and thickness of each component.
When certain components are described as being "on" another component, the component can be directly on the other component; there may also be an intermediate component disposed on the intermediate component and the intermediate component disposed on another component. When an element is referred to as being "mounted to" or "connected to" another element, they are directly "mounted to" or "connected to" the other element or "mounted to" or "connected to" the other element through an intermediate element.
Example 1
The embodiment provides a display panel including an array substrate 100.
As shown in fig. 2, the array substrate 100 includes: substrate 1, metal wire layer 2, planarization layer 3, first conductive layer 4, passivation layer 5, and second conductive layer 6.
The substrate 1 comprises a substrate, the substrate can be a flexible substrate and has a water and oxygen blocking effect, and the substrate has good impact resistance and can effectively protect the array substrate 100. The material of the substrate comprises one or more of glass, silicon dioxide, polyethylene, polypropylene, polystyrene, polylactic acid, polyethylene terephthalate, polyimide or polyurethane.
As shown in fig. 2, a metal wire layer 2 is disposed on the substrate 1; the material of the metal wire layer 2 is metal, such as copper Cu or molybdenum Mo.
As shown in fig. 2, a planarization layer 3 is disposed on the metal wire layer 2 and the substrate 1. The planarization layer 3 may provide a planar surface for the preparation of the first conductive layer 4 thereon.
As shown in fig. 2 and 3, a through hole 7 is formed in the planar layer 3, and the through hole 7 penetrates through the planar layer 3 and is disposed opposite to the metal wire layer 2. The through hole 7 is mainly used for connecting the first conductive layer 4 with the metal wiring layer 2, and the effect that signals in the metal wiring layer 2 are transmitted to the first conductive layer 4 is achieved.
As shown in fig. 2, the first conductive layer 4 is disposed on the planarization layer 3, extends into the through hole 7, attaches to the sidewall of the through hole 7, and is connected to the metal wire layer 2. First conductive layer 4 is thus brought into contact with metal wire layer 2, and the effect of transmitting signals in metal wire layer 2 to first conductive layer 4 is achieved. Since ITO (indium tin oxide) has excellent conductivity and transparency and can cut off electron radiation, ultraviolet rays, and far infrared rays harmful to the human body, ITO is preferable as the material of the first conductive layer 4 in this embodiment.
As shown in fig. 2, a passivation layer 5 is disposed on the first conductive layer 4 and extends into the via 7.
As shown in fig. 2 and 4, a via hole 8 is formed in the passivation layer 5, and the via hole 8 penetrates through the passivation layer 5 and is disposed opposite to the sidewall of the through hole 7 and/or the metal wire layer 2.
As shown in fig. 2 and 4, in the present embodiment, the via holes 8 include more than two. The via hole 8 in the present embodiment includes a first via hole 81, a second via hole 82, and a third via hole 83. The first via 81 is arranged opposite to the metal wire layer 2; the second via hole 82 is arranged opposite to one side wall of the through hole 7; the third via hole 83 is disposed opposite to the other side wall of the through hole 7. By forming via 8 on passivation layer 5, second conductive layer 6 facilitates the transfer of signals from a portion of first conductive layer 4 opposite metal wire layer 2 to another portion of first conductive layer 4 opposite the sidewall of via 7.
As shown in fig. 2, second conductive layer 6 is disposed within via 8, connected to a portion of first conductive layer 4 opposite to metal line layer 2, and connected to another portion of first conductive layer 4 opposite to a sidewall of via 7.
As shown in fig. 2, in the present embodiment, the second conductive layer 6 is connected to the first conductive layer 4 through a first via 81, connected to the first conductive layer 4 through a second via 82, and connected to the first conductive layer 4 through a third via 83. Since ITO (indium tin oxide) has excellent conductivity and transparency and can cut off electron radiation, ultraviolet rays, and far infrared rays harmful to the human body, ITO is preferable as the material of the second conductive layer 6 in this embodiment.
Thereby, the second conductive layer 6 transmits a signal of a portion of the first conductive layer 4 opposite to the metal wire layer 2 to another portion of the first conductive layer 4 opposite to the side wall of the via hole 7. When the first conductive layer 4 cracks at the corner between the surface of the metal wire layer 2 and the side wall of the through hole 7, the signal of the metal wire layer 2 can still be transmitted through the first conductive layer 4, so that the increase of the lap joint impedance is avoided, and the abnormal touch phenomenon is avoided.
As shown in fig. 5, the present embodiment further provides a method for manufacturing the array substrate 100 according to the present embodiment, which includes the following steps: s1, providing a substrate 1; s2, preparing a metal wire layer 2 on the substrate 1; s3, preparing a flat layer 3 on the metal wire layer 2 and the substrate 1; s4, forming a through hole 7 through the planarization layer 3, wherein the through hole 7 is disposed opposite to the metal wire layer 2; s5, preparing a first conductive layer 4 on the planarization layer 3, wherein the first conductive layer 4 extends into the via 7, attaches to the sidewall of the via 7, and connects to the metal wire layer 2; s6, preparing a passivation layer 5 on the first conductive layer 4, wherein the first conductive layer 4 extends into the through hole 7; s7, forming more than two through holes 8 through the passivation layer 5; a via 8 is arranged opposite to the metal wire layer 2; the other through hole 8 is arranged opposite to the side wall of the through hole 7; and S8, preparing a second conductive layer 6 within the via hole 8, the second conductive layer 6 being connected to a portion of the first conductive layer 4 opposite to the metal wire layer 2 and to another portion of the first conductive layer 4 opposite to the sidewall of the via hole 7.
In S8 the second conductive layer 6 is connected to the first conductive layer 4 through one via 8 and to the first conductive layer 4 through another via 8.
Wherein the through holes 7 and the via holes 8 are formed by etching.
The second conductive layer 6 in the array substrate 100 prepared and formed by the above method transfers a signal of a portion of the first conductive layer 4 opposite to the metal line layer 2 to another portion of the first conductive layer 4 opposite to the sidewall of the via hole 7. When the first conductive layer 4 cracks at the corner between the surface of the metal wire layer 2 and the side wall of the through hole 7, the signal of the metal wire layer 2 can still be transmitted through the first conductive layer 4, so that the increase of the lap joint impedance is avoided, and the abnormal touch phenomenon is avoided.
Example 2
The embodiment provides a display panel including an array substrate 100.
As shown in fig. 6, the array substrate 100 includes: substrate 1, metal wire layer 2, planarization layer 3, first conductive layer 4, passivation layer 5, and second conductive layer 6.
The substrate 1 comprises a substrate, the substrate can be a flexible substrate and has a water and oxygen blocking effect, and the substrate has good impact resistance and can effectively protect the array substrate 100. The material of the substrate comprises one or more of glass, silicon dioxide, polyethylene, polypropylene, polystyrene, polylactic acid, polyethylene terephthalate, polyimide or polyurethane.
As shown in fig. 6, a metal wire layer 2 is disposed on the substrate 1; the material of the metal wire layer 2 is metal, such as copper Cu or molybdenum Mo.
As shown in fig. 6, a planarization layer 3 is disposed on the metal wire layer 2 and the substrate 1. The planarization layer 3 may provide a planar surface for the preparation of the first conductive layer 4 thereon.
As shown in fig. 6, a through hole 7 is provided in the planarization layer 3, and the through hole 7 penetrates the planarization layer 3 and is disposed opposite to the metal wire layer 2. The through hole 7 is mainly used for connecting the first conductive layer 4 with the metal wiring layer 2, and the effect that signals in the metal wiring layer 2 are transmitted to the first conductive layer 4 is achieved.
As shown in fig. 6, the first conductive layer 4 is disposed on the planarization layer 3, extends into the through hole 7, attaches to the sidewall of the through hole 7, and is connected to the metal wire layer 2. First conductive layer 4 is thus brought into contact with metal wire layer 2, and the effect of transmitting signals in metal wire layer 2 to first conductive layer 4 is achieved. Since ITO (indium tin oxide) has excellent conductivity and transparency and can cut off electron radiation, ultraviolet rays, and far infrared rays harmful to the human body, ITO is preferable as the material of the first conductive layer 4 in this embodiment.
As shown in fig. 6, a passivation layer 5 is disposed on the first conductive layer 4 and extends into the through hole 7.
As shown in fig. 6 and 7, a via hole 8 is formed in the passivation layer 5, and the via hole 8 penetrates through the passivation layer 5 and is disposed opposite to the sidewall of the through hole 7 and/or the metal wire layer 2.
As shown in fig. 6 and 7, in this embodiment, the number of the via holes 8 is one. The via hole 8 is arranged opposite to the side wall of the through hole 7 and the metal wire layer 2. By forming via 8 on passivation layer 5, second conductive layer 6 facilitates the transfer of signals from a portion of first conductive layer 4 opposite metal wire layer 2 to another portion of first conductive layer 4 opposite the sidewall of via 7.
As shown in fig. 6, the second conductive layer 6 is disposed in the via hole 8, attached to the first conductive layer 4, and extends from the hole wall on one side of the via hole 8 to the hole wall on the other side. Since ITO (indium tin oxide) has excellent conductivity and transparency and can cut off electron radiation, ultraviolet rays, and far infrared rays harmful to the human body, ITO is preferable as the material of the second conductive layer 6 in this embodiment.
Thereby, the second conductive layer 6 transmits a signal of a portion of the first conductive layer 4 opposite to the metal wire layer 2 to another portion of the first conductive layer 4 opposite to the side wall of the via hole 7. When the first conductive layer 4 cracks at the corner between the surface of the metal wire layer 2 and the side wall of the through hole 7, the signal of the metal wire layer 2 can still be transmitted through the first conductive layer 4, so that the increase of the lap joint impedance is avoided, and the abnormal touch phenomenon is avoided.
As shown in fig. 8, the present embodiment further provides a method for manufacturing the array substrate 100 according to the present embodiment, which includes the following steps: s1, providing a substrate 1; s2, preparing a metal wire layer 2 on the substrate 1; s3, preparing a flat layer 3 on the metal wire layer 2 and the substrate 1; s4, forming a through hole 7 through the planarization layer 3, wherein the through hole 7 is disposed opposite to the metal wire layer 2; s5, preparing a first conductive layer 4 on the planarization layer 3, wherein the first conductive layer 4 extends into the via 7, attaches to the sidewall of the via 7, and connects to the metal wire layer 2; s6, preparing a passivation layer 5 on the first conductive layer 4, wherein the first conductive layer 4 extends into the through hole 7; s7, forming a via hole 8 through the passivation layer 5, wherein the via hole 8 is arranged opposite to the metal wire layer 2 and the side wall of the through hole 7; and S8, preparing a second conductive layer 6 within the via hole 8, the second conductive layer 6 being connected to a portion of the first conductive layer 4 opposite to the metal wire layer 2 and to another portion of the first conductive layer 4 opposite to the sidewall of the via hole 7.
In S8, the second conductive layer 6 is disposed in the via hole 8, attached to the first conductive layer 4, and extends from the hole wall on one side of the via hole 8 to the hole wall on the other side.
Wherein the through holes 7 and the via holes 8 are formed by etching.
The second conductive layer 6 in the array substrate 100 prepared and formed by the above method transfers a signal of a portion of the first conductive layer 4 opposite to the metal line layer 2 to another portion of the first conductive layer 4 opposite to the sidewall of the via hole 7. When the first conductive layer 4 cracks at the corner between the surface of the metal wire layer 2 and the side wall of the through hole 7, the signal of the metal wire layer 2 can still be transmitted through the first conductive layer 4, so that the increase of the lap joint impedance is avoided, and the abnormal touch phenomenon is avoided.
The array substrate, the manufacturing method thereof, and the display panel provided by the present application are described in detail above, and specific examples are applied in the description to explain the principle and the implementation of the present application, and the description of the above examples is only used to help understand the technical scheme and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims (10)

1. An array substrate, comprising:
a substrate;
the metal wire layer is arranged on the substrate;
the flat layer is arranged on the metal wire layer and the substrate;
the through hole penetrates through the flat layer and is arranged opposite to the metal wire layer;
the first conducting layer is arranged on the flat layer, extends into the through hole, is attached to the side wall of the through hole and is connected to the metal wire layer;
the passivation layer is arranged on the first conductive layer and extends into the through hole;
the through hole penetrates through the passivation layer and is arranged opposite to the side wall of the through hole and/or the metal wire layer; and
and the second conducting layer is arranged in the through hole, is connected to one part of the first conducting layer, which is opposite to the metal wire layer, and is connected to the other part of the first conducting layer, which is opposite to the side wall of the through hole.
2. The array substrate of claim 1, wherein the number of the vias is more than two;
a via hole is arranged opposite to the metal wire layer;
the other via hole is arranged opposite to the side wall of the through hole.
3. The array substrate of claim 2, wherein the second conductive layer is connected to the first conductive layer through one via and connected to the first conductive layer through another via.
4. The array substrate of claim 1, wherein the via is disposed opposite the sidewall of the via and the metal line layer.
5. The array substrate of claim 4, wherein the second conductive layer is disposed within the via, attached to the first conductive layer, and extends from a wall of the via on one side to a wall of the via on the other side.
6. The preparation method of the array substrate is characterized by comprising the following steps:
providing a substrate;
preparing a metal wire layer on the substrate;
preparing a flat layer on the metal wire layer and the substrate;
penetrating through the flat layer to form a through hole, wherein the through hole is arranged opposite to the metal wire layer;
preparing a first conductive layer on the flat layer, wherein the first conductive layer extends into the through hole, is attached to the side wall of the through hole and is connected to the metal wire layer;
preparing a passivation layer on the first conductive layer, wherein the first conductive layer extends into the through hole;
a through hole is formed through the passivation layer and is arranged opposite to the side wall of the through hole and/or the metal wire layer; and
preparing a second conductive layer within the via, the second conductive layer being connected to a portion of the first conductive layer opposite to the metal line layer and to another portion of the first conductive layer opposite to the sidewall of the via.
7. The method for preparing the array substrate according to claim 6, wherein the step of forming a via hole through the passivation layer and disposing the via hole opposite to the sidewall of the through hole and/or the metal line layer comprises: penetrating the passivation layer to form more than two through holes;
a via hole is arranged opposite to the metal wire layer;
the other via hole is arranged opposite to the side wall of the through hole.
8. The method for preparing the array substrate according to claim 6, wherein in the step of forming a via hole through the passivation layer, the via hole being disposed opposite to the sidewall of the through hole and/or the metal line layer, the via hole is disposed opposite to the sidewall of the through hole and the metal line layer.
9. The method for preparing the array substrate according to claim 6, wherein the through holes and the via holes are formed by etching.
10. A display panel comprising the array substrate of any one of claims 1-5.
CN202010470538.4A 2020-05-28 2020-05-28 Array substrate, preparation method thereof and display panel Active CN111564457B (en)

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Citations (5)

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