CN111564379A - Chip packaging method and chip structure - Google Patents
Chip packaging method and chip structure Download PDFInfo
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- CN111564379A CN111564379A CN202010396125.6A CN202010396125A CN111564379A CN 111564379 A CN111564379 A CN 111564379A CN 202010396125 A CN202010396125 A CN 202010396125A CN 111564379 A CN111564379 A CN 111564379A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0651—Function
- H01L2224/06515—Bonding areas having different functions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a chip packaging method and a chip structure, wherein the chip packaging method comprises the following steps: providing a first wafer, wherein a plurality of chips are arranged on the first wafer; forming a rewiring layer on the surface of the first wafer; forming a metal column structure on the surface of the rewiring layer to form a second wafer; cutting the second wafer to form at least one first sub-wafer and at least one second sub-wafer; performing lead bonding packaging on the first wafer; and carrying out flip-chip packaging on the second sub-wafer. The packaging method of the chip provided by the invention can save the number of wafers, thereby saving the cost and improving the efficiency.
Description
Technical Field
The present invention relates to the field of semiconductor packaging, and in particular, to a chip packaging method and a chip structure.
Background
With the increasing integration of electronic devices, the semiconductor packaging field proposes Package on Package (PoP) and Stacked Die Package (Stacked Die Package). The packaging is that a plurality of packaging bodies or bare chips are overlapped in the height direction so as to achieve the purpose of reducing the occupied area of the packaging bodies.
Currently, most of the commonly used Chip stack pops adopt a Wire Bond (WB) or Flip Chip (FC) packaging mode.
Wire Bonding (WB): the thin metal wire is used, heat, pressure and ultrasonic energy are utilized to enable the metal lead wire to be tightly welded with a chip bonding pad and a substrate bonding pad, electric interconnection between the chip and the substrate and information intercommunication between the chips are achieved, and the thin metal wire is widely applied to packaging of radio frequency modules, storage chips and micro-electro-mechanical system devices.
Flip Chip (FC) packaging: the packaging technology is widely applied to packaging products such as CPU, GPU, Chipset and the like.
In general, WB packaging or FC packaging is adopted, but sometimes two packaging methods are also needed, for example, one FC packaging-based chip and also WB packaging are needed, according to the conventional process, after the chip is initially formed (fab out), one batch of WB packaging (corresponding wafer is needed), and the other batch of WB packaging (copper pillar) and FC packaging (corresponding wafer is also needed), so that WB packaging and FC packaging need to be performed separately, and separate wafers are needed, which also needs to be used for FC packaging-based chips, and thus the number of wafers (wafers) is increased, and thus the cost is increased.
Disclosure of Invention
In view of the above, an aspect of the present invention provides a chip packaging method, including:
providing a first wafer, wherein a plurality of chips are arranged on the first wafer;
forming a rewiring layer on the surface of the first wafer;
forming a metal column structure on the surface of the rewiring layer to form a second wafer;
cutting the second wafer to form at least one first sub-wafer and at least one second sub-wafer;
and performing wire bonding packaging on the first wafer.
In an embodiment, the method for packaging a chip further includes:
and performing flip packaging on the second sub-wafer to enable the chip on the second sub-wafer to be electrically connected with a packaging substrate through the metal column structure.
In one embodiment, forming a metal pillar structure on the surface of the redistribution layer includes:
forming a metal column on the surface of the redistribution layer, wherein the metal column is electrically connected with the redistribution layer;
and forming a metal cap on the surface of the metal column.
In one embodiment, the wire bonding packaging of the first sub-wafer includes:
and bonding one end of a lead with the metal cap of the metal column structure of the first wafer, and bonding the other end of the lead on a packaging substrate, so that the chip of the first wafer is electrically connected with the packaging substrate through the lead.
In one embodiment, the leads are secured to and electrically connected with the metal post structure by soldering the leads to the metal cap.
In one embodiment, the metal pillar is made of copper.
In one embodiment, the material of the metal cap is tin.
In an embodiment, the redistribution layer includes an opening.
In one embodiment, the metal pillar structure is more than or equal to 15 μm away from the nearest boundary of the redistribution layer.
In an embodiment, the first wafer includes an uppermost metal layer on a surface of the first wafer, and before forming a redistribution layer on the surface of the first wafer, the method further includes:
and forming a passivation layer on the uppermost metal layer, wherein the passivation layer is provided with an opening to expose part of the uppermost metal layer, and the redistribution layer fills the opening of the passivation layer and is in contact with the uppermost metal layer so as to be electrically connected with the uppermost metal layer.
Another aspect of the present invention provides a chip structure, including:
a chip substrate;
the uppermost metal layer is positioned on the chip substrate;
the passivation layer is positioned on the uppermost metal layer and is provided with an opening so as to expose part of the uppermost metal layer;
the rewiring layer is positioned on the passivation layer and fills the opening of the passivation layer to be contacted with the uppermost metal layer;
the metal column structure is positioned on the redistribution layer and comprises a metal column and a metal cap, the metal column is electrically connected with the redistribution layer, and the metal cap is bonded with a lead;
the metal column structure is connected with the uppermost metal layer through the redistribution layer and is electrically connected with a packaging substrate through the lead.
According to the chip packaging method and the chip structure provided by the invention, one wafer can be used for both an FC packaging process and a WB packaging process, which is particularly beneficial to packaging of chips mainly based on FC packaging, so that the number of wafers is saved, and the cost can be saved. In addition, the lead bonding is directly carried out on the metal column structure, and a nickel plating layer and a gold plating layer do not need to be plated additionally, so that the cost is saved. In addition, because the conventional FC package and WB package are completely separated, for example, passivation layers and redistribution layers are required to be respectively formed, the passivation layers and the redistribution layers are required to be formed twice, and the passivation layers and the redistribution layers are formed together at the earlier stage, that is, the passivation layers or the redistribution layers of the FC package and the WB package can be formed at one time, so that the efficiency is improved.
Drawings
FIG. 1 is a schematic diagram of a WB package;
FIG. 2 depicts a schematic diagram of an FC package;
FIG. 3 is a flow chart illustrating a method for packaging a chip according to an embodiment of the invention; and
fig. 4 is a schematic diagram illustrating a chip structure according to an embodiment of the invention.
Detailed Description
The present invention will be described in detail below with reference to specific embodiments shown in the drawings. These embodiments are not intended to limit the present invention, and structural, methodological, or functional changes made by those skilled in the art according to these embodiments are included in the scope of the present invention.
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their repetitive description will be omitted.
The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention may be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In some instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the invention.
Referring to fig. 1 and 2, fig. 1 is a schematic diagram of a WB package, and fig. 2 is a schematic diagram of an FC package.
As shown in fig. 1, in the WB package, a passivation layer 12 is first formed on an uppermost metal layer 11 of a chip (not shown), an opening is formed on the passivation layer 12, a redistribution layer 13 is then formed on the passivation layer 12, the redistribution layer 13 fills the opening of the passivation layer 12 to contact the uppermost metal layer 11, and a bonding pad 14 is formed on the redistribution layer 13, and the bonding pad 14 is used for bonding a wire (not shown) and is electrically connected to a package substrate through the wire. In addition, for the bonding region 14, it is necessary to plate nickel plating and gold plating, since gold is soft and is convenient for wire bonding.
As shown in fig. 2, in the FC package, a passivation layer 22 is first formed on an uppermost metal layer 21 of a chip (not shown), the passivation layer 22 has an opening, a redistribution layer 23 is then formed on the passivation layer 22, the redistribution layer 23 fills the opening of the passivation layer 22 and contacts the uppermost metal layer 21, a copper pillar 24 is formed on the redistribution layer 23, a solder cap 25 is formed on the copper pillar 24, and the chip is turned over and then soldered to the solder cap 25 to electrically connect the chip to a package substrate.
As can be seen from the above, the WB packaging process and the FC packaging process are completely different and are not compatible, in other words, for one wafer (wafer), either the WB process or the FC process is performed, and one wafer cannot be used for both the WB process and the FC process, so that even when only a small number of chips need to be WB packaged, a complete wafer is required to be performed, which inevitably results in waste of the wafer.
Based on the above, the present invention provides a method for packaging a chip, and in an embodiment, the method includes:
providing a first wafer, wherein a plurality of chips are arranged on the first wafer;
forming a rewiring layer on the surface of the first wafer;
forming a metal column structure on the surface of the rewiring layer to form a second wafer;
cutting the second wafer to form at least one first sub-wafer and at least one second sub-wafer;
and performing wire bonding packaging on the first wafer.
Embodiments of the chip packaging method according to the present invention will be described in detail below with reference to the accompanying drawings.
Referring to fig. 3 and 4, fig. 3 is a schematic flow chart illustrating a chip packaging method according to an embodiment of the invention, and fig. 4 is a schematic diagram illustrating a chip structure according to an embodiment of the invention.
First, in step 310, a first wafer is provided, on which a plurality of chips are disposed, and the first wafer is a wafer that has just been shipped (fab out) and has not been packaged.
Then, in step 320, a redistribution layer (RDL) 43 is formed on the surface of the first wafer, and the material of the RDL 43 may be copper.
In one embodiment, when the uppermost metal layer (fab) 41 is formed on the surface of the chip, i.e., the surface of the first wafer, a Passivation layer (Passivation)42 is formed on the uppermost metal layer 41 before the redistribution layer 43 is formed, and the Passivation layer 42 may be a silicon nitride (silicon nitride) layer, a silicon oxide (silicon oxide) layer, a silicon oxynitride (silicon oxynitride) layer, or a combination thereof. The passivation layer 42 may have one or more openings 42a, and if necessary, the openings 42a may expose a portion of the uppermost metal layer 41, and at this time, the redistribution layer 43 fills the openings 42a to contact the uppermost metal layer 41, thereby electrically connecting the redistribution layer 43 to the uppermost metal layer 41.
Thereafter, in step 330, a metal pillar structure is formed on the surface of the redistribution layer 43 to form a second wafer, which is different from the first wafer without packaging because the redistribution layer 42 and the metal pillar structure are formed, i.e., the second wafer is equivalent to the wafer with the package.
In one embodiment, forming the metal pillar structure includes: forming a metal pillar (pilar) 44 on the surface of the redistribution layer 43, wherein the metal pillar 44 is electrically connected with the redistribution layer 43; a metal cap 45 is formed on the surface of the metal post 44.
In an embodiment, the metal pillar 44 may be a copper pillar, but not limited thereto, and the material of the metal cap 45 is tin, i.e. a tin layer is formed on the metal pillar 44.
Note that the redistribution layer 43 and the metal pillar structure may be formed by using a mask (mask).
Then, in step 340, the second wafer is cut to form at least one first sub-wafer and at least one second sub-wafer, that is, a complete wafer is cut and divided into the first sub-wafer and the second sub-wafer as required, the first sub-wafer can be used for subsequent WB packaging, and the second sub-wafer can be used for subsequent FC packaging.
Then, in step 350, wire bonding packaging is performed on the first sub-wafer, that is, WB packaging is performed on the first sub-wafer.
In one embodiment, the WB packaging for the first wafer includes:
bonding one end of a lead with the metal cap 45 of the metal column structure of the first wafer, wherein the lead and the metal cap 45 can be fixed and electrically connected by welding the lead and the metal cap 45 as the metal cap 45 on the metal column structure is a tin layer; the other end of the lead is bonded to a package substrate (not shown), that is, one end of the lead is fixed to the metal pillar structure, and the other end of the lead is fixed to the package substrate, so that the metal pillar structure is electrically connected to the package substrate through the lead, and the chip of the first sub-wafer is electrically connected to the package substrate through the lead.
In step 360, the second sub-wafer is flip-chip packaged, that is, the second sub-wafer is subjected to subsequent FC process packaging, which is not described herein again for brevity.
And the FC packaging is carried out on the second sub-wafer, so that the chip on the second sub-wafer is electrically connected with the packaging substrate through the metal column structure.
As can be seen from the above, no matter the following WB package or FC package is performed, the electrical connection is performed with the package substrate through the metal pillar structure, which is different from the conventional WB package that employs the redistribution layer to be electrically connected with the package substrate.
It should be noted that, for step 350 and step 360, that is, performing WB encapsulation and FC encapsulation, the operations may be flexibly selected according to needs, and may be performed only by WB encapsulation, only by FC encapsulation, or by both WB encapsulation and FC encapsulation. Because only one wafer is needed, the cost is reduced, and the passivation layer 42, the redistribution layer 43 and the metal column structure are formed together in the earlier stage, so that the efficiency can be improved.
In the embodiment of the invention, a metal column structure is formed on a wafer, and then the wafer is cut, so that a part of the wafer can be taken to be subjected to FC packaging and a part of the wafer can be taken to be subjected to WB packaging, namely, the wafer can be subjected to both FC packaging process and WB packaging process, which is particularly beneficial to packaging of chips mainly subjected to FC packaging, the number of wafers can be saved, and the cost can be saved. In addition, the lead bonding is directly carried out on the metal column structure, and a nickel plating layer and a gold plating layer do not need to be plated additionally, so that the cost is saved. In addition, because the conventional FC package and WB package are completely separated, for example, passivation layers and redistribution layers are required to be respectively formed, the passivation layers and the redistribution layers are required to be formed twice, and the passivation layers and the redistribution layers are formed together at the earlier stage, that is, the passivation layers or the redistribution layers of the FC package and the WB package can be formed at one time, so that the efficiency is improved.
In an embodiment, the redistribution layer 43 may include a plurality of boundaries 43a, and preferably, the distance from the metal pillar structure to the nearest boundary 43a of the redistribution layer 43 is greater than or equal to 15 μm, that is, the distance d from the metal pillar 44 to the boundary of the nearest opening 43a in fig. 4 needs to be greater than or equal to 15 μm, so as to facilitate the subsequent formation of the metal pillar structure, so that the metal pillar structure does not fall outside the boundary 43a, and thus metal contamination or short circuit on the device surface is avoided.
In another embodiment of the present invention, a chip structure includes: a chip substrate (not shown); an uppermost metal layer 41 on the chip substrate; a passivation layer 42 on the uppermost metal layer 41 and having an opening 42a to expose a portion of the uppermost metal layer 41; a rewiring layer 43 on the passivation layer 42, the rewiring layer 43 filling the opening 42a of the passivation layer 42 to contact the uppermost metal layer 41; a metal pillar structure located on the redistribution layer 43 and including a metal pillar 44 and a metal cap 45, wherein the metal pillar 44 is electrically connected to the redistribution layer 43, and the metal cap 45 is bonded to a lead (not shown); the metal pillar structure is connected to the uppermost metal 41 layer through the redistribution layer 43 and electrically connected to a package substrate through a lead, so that the chip and the package substrate are electrically connected through the metal pillar structure. In this embodiment, since the bonding wires are used, the chip structure can be formed by packaging the packaging process of the present invention in combination with the subsequent WB packaging process.
According to the chip packaging method and the chip structure provided by the invention, one wafer can be used for both an FC packaging process and a WB packaging process, which is particularly beneficial to packaging of chips mainly based on FC packaging, so that the number of wafers is saved, and the cost can be saved. In addition, the lead bonding is directly carried out on the metal column structure, and a nickel plating layer and a gold plating layer do not need to be plated additionally, so that the cost is saved. In addition, because the conventional FC package and WB package are completely separated, for example, passivation layers and redistribution layers are required to be respectively formed, the passivation layers and the redistribution layers are required to be formed twice, and the passivation layers and the redistribution layers are formed together at the earlier stage, that is, the passivation layers or the redistribution layers of the FC package and the WB package can be formed at one time, so that the efficiency is improved.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A method for packaging a chip, comprising:
providing a first wafer, wherein a plurality of chips are arranged on the first wafer;
forming a rewiring layer on the surface of the first wafer;
forming a metal column structure on the surface of the rewiring layer to form a second wafer;
cutting the second wafer to form at least one first sub-wafer and at least one second sub-wafer;
and performing wire bonding packaging on the first wafer.
2. The method for packaging a chip according to claim 1, further comprising:
and performing flip packaging on the second sub-wafer to enable the chip on the second sub-wafer to be electrically connected with a packaging substrate through the metal column structure.
3. The method for packaging the chip according to claim 1, wherein forming the metal pillar structure on the surface of the redistribution layer comprises:
forming a metal column on the surface of the redistribution layer, wherein the metal column is electrically connected with the redistribution layer;
and forming a metal cap on the surface of the metal column.
4. The method for packaging chips according to claim 3, wherein the wire bonding packaging of the first sub-wafer comprises:
and bonding one end of a lead with the metal cap of the metal column structure of the first wafer, and bonding the other end of the lead on a packaging substrate, so that the chip of the first wafer is electrically connected with the packaging substrate through the lead.
5. The method of packaging a chip according to claim 4, wherein the leads are fixed and electrically connected to the metal post structures by soldering the leads to the metal caps.
6. The method for packaging a chip according to claim 3, wherein the metal pillar is made of copper.
7. The method for manufacturing a semiconductor device according to claim 3, wherein a material of the metal cap is tin.
8. The method of packaging a chip of claim 3, wherein the metal pillar structure is at a distance greater than or equal to 15 μm from a nearest boundary of the redistribution layer.
9. The method for packaging chips as claimed in claim 1, wherein the surface of the first wafer is provided with an uppermost metal layer, and before the forming the redistribution layer on the surface of the first wafer, the method further comprises:
and forming a passivation layer on the uppermost metal layer, and forming a hole on the passivation layer to expose part of the uppermost metal layer, wherein the redistribution layer fills the hole of the passivation layer and contacts with the uppermost metal layer so as to electrically connect the redistribution layer with the uppermost metal layer.
10. A chip structure, comprising:
a chip substrate;
the uppermost metal layer is positioned on the chip substrate;
the passivation layer is positioned on the uppermost metal layer and is provided with an opening so as to expose part of the uppermost metal layer;
the rewiring layer is positioned on the passivation layer and fills the opening of the passivation layer to be contacted with the uppermost metal layer;
the metal column structure is positioned on the redistribution layer and comprises a metal column and a metal cap, the metal column is electrically connected with the redistribution layer, and the metal cap is bonded with a lead;
the metal column structure is connected with the uppermost metal layer through the redistribution layer and is electrically connected with a packaging substrate through the lead.
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| CN202010396125.6A CN111564379A (en) | 2020-05-12 | 2020-05-12 | Chip packaging method and chip structure |
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| CN202010396125.6A CN111564379A (en) | 2020-05-12 | 2020-05-12 | Chip packaging method and chip structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030057559A1 (en) * | 2001-09-27 | 2003-03-27 | Mis J. Daniel | Methods of forming metallurgy structures for wire and solder bonding |
| US20060079025A1 (en) * | 2004-10-12 | 2006-04-13 | Agency For Science, Technology And Research | Polymer encapsulated dicing lane (PEDL) technology for Cu/low/ultra-low k devices |
| US20090184411A1 (en) * | 2008-01-22 | 2009-07-23 | Samsung Electronics Co., Ltd | Semiconductor packages and methods of manufacturing the same |
| CN203288579U (en) * | 2013-04-17 | 2013-11-13 | 南通富士通微电子股份有限公司 | Wafer encapsulation structure |
-
2020
- 2020-05-12 CN CN202010396125.6A patent/CN111564379A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030057559A1 (en) * | 2001-09-27 | 2003-03-27 | Mis J. Daniel | Methods of forming metallurgy structures for wire and solder bonding |
| US20060079025A1 (en) * | 2004-10-12 | 2006-04-13 | Agency For Science, Technology And Research | Polymer encapsulated dicing lane (PEDL) technology for Cu/low/ultra-low k devices |
| US20090184411A1 (en) * | 2008-01-22 | 2009-07-23 | Samsung Electronics Co., Ltd | Semiconductor packages and methods of manufacturing the same |
| CN203288579U (en) * | 2013-04-17 | 2013-11-13 | 南通富士通微电子股份有限公司 | Wafer encapsulation structure |
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Address after: Room 901-23, 9 / F, west 4 building, Xigang development center, 298 Zhenhua Road, Sandun Town, Xihu District, Hangzhou City, Zhejiang Province Applicant after: Jiehuate Microelectronics Co.,Ltd. Address before: Room 901-23, 9 / F, west 4 building, Xigang development center, 298 Zhenhua Road, Sandun Town, Xihu District, Hangzhou City, Zhejiang Province Applicant before: JOULWATT TECHNOLOGY Inc.,Ltd. |
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Application publication date: 20200821 |