CN111564368A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN111564368A CN111564368A CN202010433459.6A CN202010433459A CN111564368A CN 111564368 A CN111564368 A CN 111564368A CN 202010433459 A CN202010433459 A CN 202010433459A CN 111564368 A CN111564368 A CN 111564368A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
Abstract
The invention provides a semiconductor device and a manufacturing method thereof, and provides a wafer bonding structure, wherein the wafer bonding structure comprises a first wafer and a second wafer which are bonded, the first wafer comprises a first substrate and a first dielectric layer, the surface of the first dielectric layer is used as the bonding surface of the first wafer and the second wafer, a barrier layer is formed in the first substrate, and then the barrier layer is used as an etching stop layer to thin the first substrate from the surface of the first substrate.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly, to a semiconductor device and a method for fabricating the same.
Background
With the continuous development of semiconductor technology, bonding packaging technology is widely used, which is to bond different device stacks together by using bonding technology.
After the wafer is bonded, the substrate of the upper wafer needs to be thinned, and the Total Thickness Variation (TTV) of the thinned substrate surface is large, which affects the subsequent processes and further affects the reliability of the device.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can improve the reliability of the device.
In order to achieve the purpose, the invention has the following technical scheme:
a method of manufacturing a semiconductor device, comprising:
providing a wafer bonding structure; the wafer bonding structure comprises a first wafer and a second wafer which are bonded, the first wafer comprises a first substrate and a first dielectric layer, the surface of the first dielectric layer in the first wafer is used as a bonding surface, and a barrier layer is formed in the first substrate;
and thinning the first substrate from the surface of the first substrate by taking the barrier layer as an etching stop layer.
Optionally, the barrier layer in the first substrate is spaced from both the upper surface and the lower surface of the first substrate by a certain distance, so as to divide the first substrate into a first partial substrate and a second partial substrate.
Optionally, the barrier layer in the first substrate is formed by an ion implantation method.
Optionally, the first substrate is silicon, and the ion-implanted material is carbon ions.
Optionally, the barrier layer is formed before forming the first dielectric layer, or the barrier layer is formed after bonding the first wafer and the second wafer.
Optionally, the thickness of the barrier layer ranges from 1 μm to 2 μm.
Optionally, the method for thinning the first substrate may include:
wet etching and/or chemical mechanical polishing.
Optionally, the solution used in the wet etching is tetramethylammonium hydroxide.
Optionally, the method further includes:
and removing the barrier layer.
Optionally, the method further includes:
etching and forming a silicon through hole from the first substrate;
and forming an extraction structure and/or an interconnection structure between the first wafer and the second wafer in the silicon through hole.
Optionally, the first dielectric layer includes: a first metal bonding layer and a first non-metal bonding layer;
the second wafer includes: a second dielectric layer; the second dielectric layer includes: a second metal bonding layer and a second non-metal bonding layer;
the bonded first and second wafers comprise:
the first medium layer and the second medium layer are bonded, and the first nonmetal bonding layer and the second nonmetal bonding layer are bonded; and bonding the first metal bonding layer and the second metal bonding layer.
Optionally, the bonding the first non-metal bonding layer and the second non-metal bonding layer includes:
contacting the first non-metallic bonding layer and the second non-metallic bonding layer without applying an external force; the first and second non-metallic bonding layers are bonded by van der waals forces.
Optionally, the bonding the first non-metal bonding layer and the second non-metal bonding layer includes:
and contacting the first non-metal bonding layer and the second non-metal bonding layer by applying an external force.
Optionally, the bonding the first metal bonding layer and the second metal bonding layer includes:
and forming the first metal bonding layer and the second metal bonding layer into a whole by heating.
A semiconductor device, comprising: a first wafer and a second wafer;
the first wafer comprises a first substrate and a first dielectric layer, wherein a barrier layer is formed in the first substrate;
and bonding the second wafer and the first wafer, wherein the surface of the first dielectric layer in the first wafer is used as a bonding surface.
Optionally, the first dielectric layer includes: a first metal bonding layer and a first non-metal bonding layer;
the second wafer includes: a second dielectric layer; the second dielectric layer includes: a second metal bonding layer and a second non-metal bonding layer;
wherein the first metal bonding layer and the second metal bonding layer are bonded; the first nonmetal bonding layer and the second nonmetal bonding layer are bonded.
The wafer bonding structure comprises a first wafer and a second wafer which are bonded, the first wafer comprises a first substrate and a first dielectric layer, the surface of the first dielectric layer is used as the bonding surface of the first wafer and the second wafer, a barrier layer is formed in the first substrate, then the barrier layer is used as an etching stop layer, and the first substrate is thinned from the surface of the first substrate, so that the first substrate material above the barrier layer is removed in the process of thinning the first wafer, the barrier layer cannot be damaged, the uniformity of the surface of the thinned first substrate is improved, the subsequent process is facilitated, and the reliability of the device is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 shows a schematic structural diagram of a conventional semiconductor device;
FIG. 2 shows a flow diagram of a method of manufacturing a semiconductor device according to an embodiment of the invention;
fig. 3-7 show schematic structural views of semiconductor devices formed according to fabrication methods of embodiments of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described and will be readily apparent to those of ordinary skill in the art without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.
As described in the background art, referring to fig. 1, after the first wafer 10 and the second wafer 20 are bonded through the first dielectric bonding layer 110 and the second dielectric bonding layer 210, the first substrate 100 of the first wafer 10 needs to be thinned, and a total thickness difference (TTV) of the surface of the thinned first substrate 100 is large, which affects subsequent processes, for example, when a through Via is formed from the back of the wafer by using a Through Silicon Via (TSV) technology, the non-uniform thickness of the substrate surface causes partial through silicon Via to be incompletely etched, or when the non-uniform thickness of the substrate surface affects subsequent bonding with other wafers, which affects reliability of devices.
Therefore, the application provides a manufacturing method of a semiconductor device, which provides a wafer bonding structure, wherein the wafer bonding structure comprises a first wafer and a second wafer which are bonded, the first wafer comprises a first substrate and a first dielectric layer, the surface of the first dielectric layer is used as the bonding surface of the first wafer and the second wafer, a barrier layer is formed in the first substrate, then, the barrier layer is used as an etching stop layer, and the first substrate is thinned from the surface of the first substrate.
In order to better understand the technical solution and technical effects of the present application, the following detailed description will be made on specific embodiments with reference to the flowchart 2 and the accompanying fig. 3-7.
Referring to fig. 2, in step S01, a wafer bonding structure is provided, and in step S02, the wafer bonding structure includes a first wafer 10 and a second wafer 20 which are bonded.
In the embodiment of the application, the wafer bonding structure may be a bonding structure formed by bonding two or more wafers, the two or more wafers may be the same wafer or different wafers, and the wafers may be bonded through a dielectric bonding layer or may be bonded through the dielectric bonding layer and a metal bonding layer in the dielectric bonding layer. The wafer bonding structure includes a first wafer 10 and a second wafer 20 bonded together. The first wafer 10 and the second wafer 20 may be the same wafer or different wafers. In the first wafer 10 and the second wafer 20, the processing of the devices on the substrate may have been completed.
In step S03, the first wafer 10 includes a first substrate 100 and a first dielectric layer 110, as shown in fig. 3, the surface of the first dielectric layer 110 in the first wafer 10 serves as a bonding surface, and in step S04, a barrier layer 102 is formed in the first substrate 100, as shown in fig. 3-7.
In the embodiment of the present application, the first substrate 100 and the second substrate 200 may have formed thereon device structures and interconnect lines (not shown) electrically connecting the device structures, the device structures are respectively covered by the first dielectric layer 110 and the second dielectric layer 120, the first dielectric layer 110 and the second dielectric layer 210 may include multiple layers, for example, may include an interlayer dielectric layer and an intermetal dielectric layer, and the interconnect lines are formed in the first dielectric layer 110 and the second dielectric layer 210.
The device structure may include a MOS device, a sensing device, a storage device, or other passive devices other than capacitors, the storage device may include a nonvolatile memory, such as a floating gate field effect transistor (a NOR flash memory, a NAND flash memory, or the like), a ferroelectric memory, a phase change memory, or the like, the device structure may be a planar device, such as a FIN-FET (FIN field effect transistor), a three-dimensional memory, or the like, the sensing device may be a light sensing device, or the like, and the other passive devices include resistors, inductors, or the like. The device structure in the first wafer 10 may be the same as or different from the device structure in the second wafer 20.
The interconnect line may include multiple layers, different layers of interconnect lines may be interconnected by contact plugs, vias, etc., and the interconnect line may be a metal material, such as tungsten, aluminum, copper, etc. In the illustration of the embodiments of the present application, only the first dielectric layer 110 and the second dielectric layer 210 are illustrated, and the device structure and the interconnection lines are not illustrated, and the illustration is only for the sake of simplifying the drawing, and it is understood that in different designs and applications, the required device structure and the interconnection lines of the required structure can be formed as required.
In the embodiment of the present application, the first substrate 100 and the second substrate 200 may be the same substrate or different substrates. The first substrate 100 and the second substrate 200 are semiconductor substrates, and may be, for example, a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) or a GOI (germanium On Insulator) or the like. In other embodiments, the substrate 100 may also include other elemental or compound semiconductor substrates, such as GaAs, InP, SiC, etc., as well as stacked structures, such as Si/SiGe, etc., as well as other epitaxial structures, such as SGOI (silicon germanium on insulator), etc. In this embodiment, the substrate may be a silicon substrate.
In this embodiment, the first dielectric layer 110 and the second dielectric layer 210 may be a single-layer or stacked structure, and the materials of the first dielectric layer 110 and the second dielectric layer 210 may be the same or different, and may include one or more of Silicon oxide, Silicon nitride, NDC (Nitrogen doped Silicon Carbide), and other dielectric materials, for example. First dielectric layer 110 includes: a first metal bonding layer 111 and a first non-metal bonding layer 112, and a second dielectric layer 210 comprising: a second metal bonding layer 211 and a second non-metal bonding layer 212; the first metal bonding layer 111 and the second metal bonding layer 211 are made of a bonding metal material, for example, copper, and the first non-metal bonding layer 112 and the second non-metal bonding layer 212 are made of a bonding non-metal material, for example, silicon oxide, silicon nitride, or the like, and only these portions are illustrated in the figure to simplify the drawing. In this embodiment, the number of the first metal bonding layers 111 and the number of the first non-metal bonding layers 112 may be the same or different, and the number of the second metal bonding layers 211 and the number of the second non-metal bonding layers 212 may be the same or different, but the number of the first metal bonding layers 111 and the number of the second metal bonding layers 211 are the same, and the number of the first non-metal bonding layers 112 and the number of the second non-metal bonding layers 212 are the same, so as to perform precise bonding.
The bonded first wafer 10 and second wafer 20 include: the first dielectric layer 110 and the second dielectric layer 210 which are bonded, and the first metal bonding layer 111 and the second metal bonding layer 211 which are bonded; a bonded first non-metallic bonding layer 112 and a second non-metallic bonding layer 212. In this embodiment, the first non-metallic bonding layer 112 and the second non-metallic bonding layer 212 may be brought into contact without applying an external force, and then the first non-metallic bonding layer 112 and the second non-metallic bonding layer 212 may be bonded by van der waals force. Bonding of the first non-metallic bonding layer 112 and the second non-metallic bonding layer 212 may also be achieved by applying an external force to bring the first non-metallic bonding layer 112 and the second non-metallic bonding layer 212 into contact. In this embodiment, the first metal bonding layer 111 and the second metal bonding layer 211 may be formed into a whole by heating, so as to complete the bonding of the first metal bonding layer 111 and the second metal bonding layer 211.
For convenience of description, a surface of the first substrate 100 on which devices are formed may be a front surface of the first wafer 10, a surface opposite to the surface of the first substrate 100 on which devices are formed may be a back surface of the first wafer 10, a surface of the second substrate 200 on which devices are formed may be a front surface of the second wafer 20, and a surface opposite to the surface of the second substrate 200 on which devices are formed may be a surface of the second wafer 20.
In this embodiment, after the device processing is completed, the first dielectric layer 110 is continuously formed on the surface of the first wafer 10, the first dielectric layer 110 may be used as a protection layer of the device structure, and may also be used as a dielectric bonding layer, and the surface of the first dielectric layer 110 may be used as a bonding surface.
In the embodiment of the present application, the first substrate 100 has a barrier layer 102 formed therein, and the barrier layer 102 has a higher etching selectivity with respect to the bulk material of the first substrate 100, for example, the barrier layer may be a carbon-doped semiconductor material layer. In a particular embodiment, the thickness of the barrier layer 102 may range from 1-2 μm.
In this embodiment, the barrier layer 102 may be formed by ion implantation, such as carbon ion implantation. Specifically, the position, concentration, thickness, etc. of ion implantation can be controlled by controlling the process parameters. The barrier layer 102 formed in the first substrate 100 is spaced apart from both the upper surface and the lower surface of the first substrate 100 by a certain distance, so that the first substrate 100 can be divided into a first partial substrate 101 and a second partial substrate 103, as shown with reference to fig. 4.
In some embodiments, the barrier layer 102 may be formed before forming the first dielectric layer 110, and specifically, the barrier layer 102 may be formed in the first substrate 100 before forming the device structure on the first substrate 100, and then the device structure processing process and the subsequent bonding process are performed on the first substrate 100. In other embodiments, the barrier layer 102 may also be formed after the first wafer 10 and the second wafer 20 are bonded, for example, the barrier layer 102 may be formed in the first substrate 100 by means of ion implantation from the first substrate 100 side after the first wafer 10 is flipped and the first wafer 10 and the second wafer 20 are bonded.
In this embodiment, the first wafer 10 and the second wafer 20 may be bonded by flipping the first wafer 10, that is, the first dielectric layer 110 may serve as a bonding surface of the first wafer 10. Specifically, the front side of the first wafer 10 and the front side of the second wafer 20 may be bonded relatively, as shown in fig. 4, at this time, the first dielectric layer 110 and the second dielectric layer 210 serve as bonding surfaces, and then, other wafers may be bonded on the back side of the first wafer 10. The front side of the first wafer 10 and the back side of the second wafer 20 may also be bonded to each other, with the first dielectric layer 110 and the second substrate 200 serving as bonding surfaces, and it is understood that the front side of the second wafer 20 may be bonded to other wafers.
In the present embodiment, the "upper" and the "lower" are opposite, and relate to the bonding manner of the first wafer 10 and the second wafer 20. Specifically, the first wafer 10 may be used as an upper wafer, and the first wafer 10 is turned over, so that the original "upper" becomes "lower", that is, the first dielectric layer 110 "on" the first substrate 100 becomes the first dielectric layer 110 "under" the first substrate 100 after being turned over.
In step S05, the first substrate 110 is thinned from the surface of the first substrate 100 by using the barrier layer 102 as an etching stop layer, as shown in fig. 5-7.
In the embodiment of the present application, after the first wafer 10 and the second wafer 20 are bonded to form the wafer bonding structure, the back surface of the first wafer 10 may be thinned, so as to reduce redundant portions and reduce the device volume.
In the embodiment of the application, the barrier layer 102 may be used as an etching stop layer to thin the surface of the first substrate 100, so as to remove the first portion of the substrate 101 above the barrier layer 102, and retain the barrier layer 102 and the second portion of the substrate 103 below the barrier layer 102, because the etching selectivity of the barrier layer 102 with respect to the substrate material is large, after the first portion of the substrate 101 above the barrier layer 102 is removed, the barrier layer 102 can maintain a relatively flat surface, so that the thickness of the surface of the thinned first substrate 100 is uniform, and the TTV of the surface of the substrate is reduced.
In this embodiment, the method for thinning the first substrate 100 may include: wet etching and/or chemical mechanical polishing removes portions of the substrate material. Specifically, a wet etching process may be used to remove the first portion of the substrate 101 above the barrier layer 102, for example, a Tetramethylammonium hydroxide (TMAH) solution may be used to thin the first substrate 100; or removing a part of the first portion of the substrate 101 by using chemical mechanical polishing, wherein unevenness may occur during the chemical mechanical polishing process, as shown in fig. 5, and then removing the remaining first portion of the substrate 101 above the barrier layer 102 by using wet etching, as shown in fig. 6; chemical mechanical polishing can also be used to remove the first portion of the substrate 101; a wet etching process may also be used to remove a portion of the first portion of the substrate 101 above the barrier layer 102, and then a chemical mechanical polishing process may be used to remove the remaining first portion of the substrate 101 above the barrier layer 102.
In the above thinning method, there may be a situation of uneven thinning rate in the process of thinning the first substrate 100, which results in unevenness of the surface of the first substrate 100 in the thinning process, as shown in fig. 5, but due to the existence of the barrier layer 102, even if the thinning rate is different, the thinning process is stopped when the first substrate 100 is thinned to the barrier layer 102, and due to the high flatness of the barrier layer 102, the surface of the thinned first substrate 100 has high flatness, which is beneficial to the subsequent processes.
In this embodiment, after the first substrate 100 is thinned by using the barrier layer 102 as an etching stop layer, the barrier layer 102 can generally maintain a relatively flat surface, so that the barrier layer 102 may be used as an upper protection layer of the wafer bonding structure without removing the barrier layer 102, and of course, the barrier layer 102 may also be removed, as shown in fig. 7, a second portion of the substrate 103 below the barrier layer 102 can ensure a relatively flat surface, which is beneficial to the subsequent process.
For example, a through silicon via may be formed by etching from the first substrate 100 after the barrier layer 102 is removed, and the through silicon via may be connected to a device in the second wafer 20 for leading out a device in the second wafer 20, and may also be connected to a device in the first wafer 10 for leading out a device in the first wafer 10, and of course, the through silicon via may be connected to a device in the first wafer 10 and a device in the second wafer 20, respectively, so as to connect the device in the second wafer 20 and the device in the first wafer 10. And then, forming a dielectric layer on the side wall of the silicon through hole, and filling a metal layer in the silicon through hole. The dielectric layer may prevent diffusion of the filled metal material into the substrate, which may be formed, for example, by electroplating of gold, silver, copper, or nickel.
In this embodiment, after the first substrate 100 is thinned, the barrier layer 102 can generally maintain a relatively flat surface, and therefore the barrier layer 102 can be used as a hard mask layer when forming the through silicon via. Specifically, a photoresist layer is spin-coated on the surface of the barrier layer 102, and a patterned photoresist layer is formed through steps of exposure, development and the like; transferring the pattern to the barrier layer 102; then, the thinned first substrate 100 is etched with the barrier layer 102 as a mask to form a through silicon via penetrating to the device structure in the first wafer 10 and/or the second wafer 20, and then the barrier layer 102 and the photoresist layer may be removed.
The above detailed description has been made on the method for manufacturing a semiconductor device according to the embodiment of the present application, and in addition, the embodiment of the present application also provides a semiconductor device including: a first wafer 10 and a second wafer 20;
the first wafer 10 comprises a first substrate 100 and a first dielectric layer 110, wherein a barrier layer 102 is formed in the first substrate 100;
the second wafer 20 is bonded to the first wafer 10, and the surface of the first dielectric layer 110 in the first wafer 10 serves as a bonding surface.
In this embodiment, first dielectric layer 110 includes: a first metal bonding layer 111 and a first non-metal bonding layer 112; the second wafer 20 includes: a second dielectric layer 210; the second dielectric layer 210 includes: a second metal bonding layer 211 and a second non-metal bonding layer 212. The first dielectric layer 110 and the second dielectric layer 210 are bonded, the first metal bonding layer 111 and the second metal bonding layer 211 are bonded, and the first nonmetal bonding layer 211 and the second nonmetal bonding layer 212 are bonded, thereby forming a bonded first wafer 10 and a bonded second wafer 20.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the device structure embodiment, since it is substantially similar to the manufacturing method embodiment, the description is relatively simple, and the relevant points can be referred to the partial description of the manufacturing method embodiment.
The foregoing is only a preferred embodiment of the present invention, and although the present invention has been disclosed in the preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make numerous possible variations and modifications to the present teachings, or modify equivalent embodiments to equivalent variations, without departing from the scope of the present teachings, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
Claims (16)
1. A method of manufacturing a semiconductor device, comprising:
providing a wafer bonding structure;
the wafer bonding structure comprises a first wafer and a second wafer which are bonded;
the first wafer comprises a first substrate and a first dielectric layer, and the surface of the first dielectric layer in the first wafer is used as a bonding surface;
a barrier layer is formed in the first substrate;
and thinning the first substrate from the surface of the first substrate by taking the barrier layer as an etching stop layer.
2. The method of claim 1, wherein the barrier layer in the first substrate is spaced from both the upper surface and the lower surface of the first substrate to divide the first substrate into a first portion of the substrate and a second portion of the substrate.
3. The method of claim 2, wherein the barrier layer in the first substrate is formed by ion implantation.
4. The method of claim 3, wherein the first substrate is silicon and the ion-implanted material is carbon ions.
5. The method of claim 1, wherein the barrier layer is formed prior to forming the first dielectric layer or wherein the barrier layer is formed after bonding the first wafer and the second wafer.
6. The method of claim 1, wherein the barrier layer has a thickness in the range of 1-2 μm.
7. The method of any of claims 1-6, wherein thinning the first substrate comprises:
wet etching and/or chemical mechanical polishing.
8. The method of claim 7, wherein the wet etching uses a solution of tetramethylammonium hydroxide.
9. The method according to any one of claims 1-6, further comprising:
and removing the barrier layer.
10. The method according to any one of claims 1-6, further comprising:
etching and forming a silicon through hole from the first substrate;
and forming an extraction structure and/or an interconnection structure between the first wafer and the second wafer in the silicon through hole.
11. The method of claim 1, wherein the first dielectric layer comprises: a first metal bonding layer and a first non-metal bonding layer;
the second wafer includes: a second dielectric layer; the second dielectric layer includes: a second metal bonding layer and a second non-metal bonding layer;
the bonded first and second wafers comprise:
the first medium layer and the second medium layer are bonded, and the first nonmetal bonding layer and the second nonmetal bonding layer are bonded; and bonding the first metal bonding layer and the second metal bonding layer.
12. The method of claim 11, wherein the bonding the first non-metallic bonding layer and the second non-metallic bonding layer comprises:
contacting the first non-metallic bonding layer and the second non-metallic bonding layer without applying an external force; the first and second non-metallic bonding layers are bonded by van der waals forces.
13. The method of claim 11, wherein the bonding the first non-metallic bonding layer and the second non-metallic bonding layer comprises:
and contacting the first non-metal bonding layer and the second non-metal bonding layer by applying an external force.
14. The method of claim 11, wherein the bonding the first metal bonding layer and the second metal bonding layer comprises:
and forming the first metal bonding layer and the second metal bonding layer into a whole by heating.
15. A semiconductor device, comprising: a first wafer and a second wafer;
the first wafer comprises a first substrate and a first dielectric layer, wherein a barrier layer is formed in the first substrate;
and bonding the second wafer and the first wafer, wherein the surface of the first dielectric layer in the first wafer is used as a bonding surface.
16. The semiconductor device of claim 15, wherein the first dielectric layer comprises: a first metal bonding layer and a first non-metal bonding layer;
the second wafer includes: a second dielectric layer; the second dielectric layer includes: a second metal bonding layer and a second non-metal bonding layer;
wherein the first metal bonding layer and the second metal bonding layer are bonded; the first nonmetal bonding layer and the second nonmetal bonding layer are bonded.
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| CN111290148A (en) * | 2020-02-19 | 2020-06-16 | 联合微电子中心有限责任公司 | Method for manufacturing modulator with SiO2 substrate formed based on wafer bonding and modulator structure thereof |
| CN112490113A (en) * | 2020-11-12 | 2021-03-12 | 武汉新芯集成电路制造有限公司 | Manufacturing method of semiconductor device |
| CN112542378A (en) * | 2020-12-01 | 2021-03-23 | 武汉新芯集成电路制造有限公司 | Manufacturing method of semiconductor device and semiconductor device |
| CN113437016A (en) * | 2021-06-25 | 2021-09-24 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
| WO2023015611A1 (en) * | 2021-08-10 | 2023-02-16 | 苏州龙驰半导体科技有限公司 | Composite structure of semiconductor wafer, and semiconductor wafer and preparation method therefor and application thereof |
| CN116544181B (en) * | 2023-07-07 | 2023-11-28 | 长鑫存储技术有限公司 | Semiconductor packaging method and semiconductor packaging structure |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110183495A1 (en) * | 2010-01-25 | 2011-07-28 | Nicolas Sousbie | Annealing process for annealing a structure |
| CN102738025A (en) * | 2011-03-31 | 2012-10-17 | Soitec公司 | Method of forming bonded semiconductor structure, and semiconductor structure formed by such method |
| CN104078357A (en) * | 2013-03-28 | 2014-10-01 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing fin type field effect tube |
| CN107887395A (en) * | 2017-11-30 | 2018-04-06 | 长江存储科技有限责任公司 | NAND memory and preparation method thereof |
| CN109314116A (en) * | 2018-07-20 | 2019-02-05 | 长江存储科技有限责任公司 | The method for being used to form three-dimensional storage part |
-
2020
- 2020-05-20 CN CN202010433459.6A patent/CN111564368A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110183495A1 (en) * | 2010-01-25 | 2011-07-28 | Nicolas Sousbie | Annealing process for annealing a structure |
| CN102738025A (en) * | 2011-03-31 | 2012-10-17 | Soitec公司 | Method of forming bonded semiconductor structure, and semiconductor structure formed by such method |
| CN104078357A (en) * | 2013-03-28 | 2014-10-01 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing fin type field effect tube |
| CN107887395A (en) * | 2017-11-30 | 2018-04-06 | 长江存储科技有限责任公司 | NAND memory and preparation method thereof |
| CN109314116A (en) * | 2018-07-20 | 2019-02-05 | 长江存储科技有限责任公司 | The method for being used to form three-dimensional storage part |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111290148A (en) * | 2020-02-19 | 2020-06-16 | 联合微电子中心有限责任公司 | Method for manufacturing modulator with SiO2 substrate formed based on wafer bonding and modulator structure thereof |
| CN112490113A (en) * | 2020-11-12 | 2021-03-12 | 武汉新芯集成电路制造有限公司 | Manufacturing method of semiconductor device |
| CN112542378A (en) * | 2020-12-01 | 2021-03-23 | 武汉新芯集成电路制造有限公司 | Manufacturing method of semiconductor device and semiconductor device |
| CN112542378B (en) * | 2020-12-01 | 2024-03-26 | 武汉新芯集成电路制造有限公司 | Method for manufacturing semiconductor device and semiconductor device |
| CN113437016A (en) * | 2021-06-25 | 2021-09-24 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
| WO2023015611A1 (en) * | 2021-08-10 | 2023-02-16 | 苏州龙驰半导体科技有限公司 | Composite structure of semiconductor wafer, and semiconductor wafer and preparation method therefor and application thereof |
| CN116544181B (en) * | 2023-07-07 | 2023-11-28 | 长鑫存储技术有限公司 | Semiconductor packaging method and semiconductor packaging structure |
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Application publication date: 20200821 |