CN111552659A - Hot switching system of back picture peg based on CPCI framework - Google Patents
Hot switching system of back picture peg based on CPCI framework Download PDFInfo
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- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
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Abstract
The invention provides a back plug board hot switching system based on a CPCI framework, which can realize a complex test task which can be realized by a plurality of board cards in the past by only utilizing a universal programmable main control board and matching with different back plug boards through certain software and hardware design and utilizing a DPR (Dynamic Partial Reconfiguration) technology of an FPGA (field programmable gate array). In actual test, the control program of the back plug board of the general programmable main control board can be configured on line by the main control computer software, and the whole test equipment does not need to be closed in the configuration process, so that the test efficiency of the test equipment can be effectively improved.
Description
Technical Field
The invention relates to a back flashboard hot switching system based on a CPCI framework.
Background
The CPCI (Compact Peripheral Component Interconnect) bus is a bus interface standard proposed by the international industry Computer manufacturers association (PCI Industrial Computer manufacturers' Group, PICMG for short). The bus standard has wide application in the field of automatic testing.
The automatic test equipment based on the CPCI framework generally comprises a CPCI case, a CPCI power supply, a CPCI back plate, a main control computer, a functional front plug board, a functional rear plug board and matched test software. The CPCI case, the CPCI power supply, the CPCI back plate and the main control computer belong to general equipment and meet the standard CPCI specification. The functional front plug-in board is mainly responsible for functions such as data processing, interface control, etc., the general board carries FPGA (Field-Programmable Gate Array) or CPU (central processing Unit) as the main processing chip, exchange data with the main control computer and carry on interface control to the back plug-in board through the standard CPCI agreement; the rear plug board provides a necessary interface circuit to be connected with the tested equipment, and is used for collecting the state information of the tested equipment, controlling the working state of the tested equipment and exchanging data.
Generally, the functional front board, the back board and the testing software will be different according to the different hardware, interface and software of the testing task. The main control computer can be connected with one or more functional front plug boards through a CPCI bus of the CPCI backboard, and each functional front plug board can be generally connected with only one rear plug board which realizes specific functions through a user-defined interface of the CPCI backboard so as to realize different test functions.
For a specific test task, a specific rear plug board, a functional front plug board and specific test software are needed to realize the required test function. Therefore, before a test task is performed, different programs need to be programmed into an onboard FPGA or CPU on the functional front plug board and different rear plug boards need to be inserted into the onboard FPGA or CPU so as to realize different test functions. However, for some complex test tasks (for example, some test tasks are heavy, the device under test has multiple interfaces, and the test requirement cannot be met by using one backplane board), the complex test tasks can be realized only by matching a plurality of backplane boards with the functional front backplane board connected to the backplane boards, which may result in an increase in hardware cost (for example, N functional front backplane boards + N functional rear backplane boards), and if the number of the board cards is too large, the volume and power consumption of the whole test device may also be increased. However, if a functional front board is used to implement multiple test functions (e.g. 1 functional front board + N rear boards) without increasing hardware cost, the conventional method is to burn different programs into the functional front board before performing different test tasks to meet new test requirements, but the whole test equipment has to be shut down, and the test tasks are interrupted, which results in low test efficiency.
Disclosure of Invention
The invention aims to provide a back flashboard hot switching system based on a CPCI framework.
In order to solve the above problems, the present invention provides a back plug board hot-swap system based on CPCI architecture, including:
a main control computer;
the universal programmable main control board is used for connecting the rear plug board and the main control computer, and comprises an FPGA, a rear plug board power supply monitoring circuit, a CPCI interface circuit and a bidirectional IO circuit, the universal programmable main control board, the rear plug board and the main control computer are connected through a CPCI back board, a main chip of the universal programmable main control board adopts an onboard FPGA, and the universal programmable main control board controls and exchanges data with the interface circuit of the rear plug board through the bidirectional IO circuit; data exchange is carried out with the main control computer through a CPCI interface; the power supply condition of the rear plugboard is controlled and monitored by a rear plugboard power supply monitoring circuit;
and the rear plugboard is used for connecting the tested equipment and the universal programmable main control board and comprises a CPCI interface circuit and a tested equipment interface circuit.
Furthermore, in the system, before switching the rear plug board, the main control computer software writes corresponding rear plug board power-off instruction words into the PCI space designated address of the universal programmable main control board;
after the on-board FPGA of the general programmable main control board receives the power-off instruction word of the rear plug board, the on-board FPGA controls the on-board relay to cut off the power supply of the rear plug board;
after the switching of the rear plugboard, the main control computer writes corresponding rear plugboard electrifying instruction words into the PCI space designated address of the universal programmable main control board;
after the on-board FPGA of the general programmable main control board receives the power-on instruction word of the rear plug board, the on-board relay is controlled to recover the power supply of the rear plug board;
the main control computer sends the configuration file corresponding to the new back plug board to an onboard FPGA of the general programmable main control board through a CPCI bus, the FPGA carries out partial reconfiguration operation on a corresponding area of the FPGA after receiving the configuration file of the new back plug board, and the general programmable main control board finishes function switching of the new back plug board after the configuration is finished;
and the universal programmable main control board accesses the interface circuit of the new rear plug board by utilizing the onboard bidirectional IO circuit.
Further, in the system, the interfaces between the general programmable main control board and the CPCI backplane are divided into a bidirectional IO interface and a power interface, and the general programmable main control board realizes control and data exchange of the rear socket board through the bidirectional IO interface; through the power interface, the universal programmable main control board realizes the power supply control of the rear plug board.
Further, in the above system, the bidirectional IO interface is connected to the bidirectional IO buffer chip output by an IO pin of the FPGA
Further, in the above system, the ± 12V, +5V and +3.3V power supplies of the backplane are provided by corresponding power supply pins in the J1 interface of the CPCI backplane through the power supply monitoring circuit of the general programmable main control board.
Further, in the system, the power supply monitoring circuit comprises a power supply monitoring chip and a relay, a control end of the power supply monitoring circuit is connected to an onboard FPGA of the general programmable main control board, the power supply monitoring chip is used for monitoring the current, the voltage and the like of the connected power supply, and the relay is used for switching on and off the connected power supply.
Further, in the above system, the data interface of the power monitoring chip is connected to the onboard FPGA of the general programmable main control board, and the onboard FPGA outputs 1 channel of IO for controlling the on-off of the relay, and the onboard FPGA program periodically accesses the power state information of the power monitoring chip, and simultaneously monitors the instruction sent by the main control computer through the CPCI bus, when the onboard FPGA program detects a backplane power-off instruction, the onboard FPGA closes the relay through the relay control port, and further cuts off the power supply of the rear plug board, and when the onboard FPGA program detects a backplane power-on instruction, the onboard FPGA opens the relay through the relay control port, and further recovers the power supply of the rear plug board.
Further, in the above system, the onboard FPGA employs a DPR module, and the onboard FPGA is internally divided into two parts: the dynamic logic part is used for storing a rear plug board control program; and the static logic part is used for storing other programs which are not required to be dynamically updated.
Further, in the above system, when a backplane control program is to be switched, the main control computer writes configuration data in a DPR module corresponding to the backplane control program of the current backplane into a PCI space corresponding register of the general programmable main control board, the CPCI interface module of the general programmable main control board continuously reads the data in the register and writes the data into a dynamic logic portion of the backplane control DPR module through HWICAP, and when the configuration data is completely transferred, the HWICAP automatically resets the backplane control DPR module;
the back flashboard control DPR module uses an onboard programmable clock CLK _ EXT _ IN of the general programmable main control board as a local working clock and finishes initialization operation;
after the initialization is completed, the BACK board control DPR module exchanges data with the interface chip of the BACK board through ports such as BACK _ OUT [127:0], BACK _ IN [127:0] and BACK _ TRI [127:0] on one hand, and exchanges data with the CPCI interface module through ports such as USR _ OUT [31:0], USR _ OUT _ EN, USR _ OUT _ CLK, USR _ IN [31:0], USR _ IN _ EN and USR _ IN _ CLK on the other hand.
Compared with the prior art, the back plug board hot switch design based on the CPCI framework provided by the invention has the advantages that the test equipment based on the CPCI framework can realize the complex test task which can be realized by a plurality of board cards only by utilizing one universal programmable main control board and matching with different back plug boards through certain software and hardware design and utilizing the DPR (Dynamic Partial Reconfiguration) technology of the FPGA. In actual test, the control program of the back plug board of the general programmable main control board can be configured on line by the main control computer software, and the whole test equipment does not need to be closed in the configuration process, so that the test efficiency of the test equipment can be effectively improved.
Drawings
FIG. 1 is a schematic diagram illustrating a hot-swap function of a backplane according to an embodiment of the present invention;
FIG. 2 is a diagram showing the relationship between a main control computer, a general programmable main control board and a rear socket interface in the embodiment of the present invention;
FIG. 3 is a schematic diagram of a bidirectional IO buffer of a general programmable main control board according to an embodiment of the present invention;
FIG. 4 is a schematic block diagram of a universal programmable main control board rear plug board power supply monitoring in an embodiment of the present invention;
fig. 5 is a functional schematic block diagram of a general programmable main control board DPR according to an embodiment of the present invention;
FIG. 6 is a diagram illustrating the relationship between the interfaces of a general programmable main control board loaded with an FPGA rear plug board controlling a DPR module according to an embodiment of the present invention;
fig. 7 is a process of generating a configuration bit stream of a general programmable main control board loaded with an FPGA backplane controlling a DPR module in an embodiment of the present invention;
fig. 8 is a flowchart of a hot-swap method of a backplane according to an embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
The invention provides a back flashboard hot switching system based on a CPCI framework, which comprises:
a main control computer;
the universal programmable main control board is used for connecting the rear plug board and the main control computer, and comprises an FPGA, a rear plug board power supply monitoring circuit, a CPCI interface circuit and a bidirectional IO (Input/Output) circuit, the universal programmable main control board, the rear plug board and the main control computer are connected through a CPCI back board, a main chip of the universal programmable main control board adopts the FPGA, and the universal programmable main control board controls and exchanges data with the interface circuit of the rear plug board through the bidirectional IO circuit; data exchange is carried out with the main control computer through a CPCI interface; the power supply condition of the rear plugboard is controlled and monitored by a rear plugboard power supply monitoring circuit;
the general programmable main control board of the embodiment of the invention mainly completes interface control of the back plug board and data exchange of the main control computer, and a main chip of the general programmable main control board is realized by adopting an FPGA (field programmable gate array). due to the programmable characteristic of the FPGA, different FPGA programs can be downloaded according to different test tasks so as to realize different functions;
and the rear plugboard is used for connecting the tested equipment and the universal programmable main control board and comprises a CPCI interface circuit and a tested equipment interface circuit.
Here, since the connection relationship between the backplane board and the device under test and the interface circuit are not directly related to the design described in the present invention, the present invention only describes the related interface relationship between the backplane board and the general programmable main control board.
The main control computer, the CPCI chassis, the CPCI backplane and the like included in the embodiment of the present invention are general-purpose devices, and are not replaceable, so detailed description is omitted here.
In order to realize the hot switching function of the back plug board of the automatic test equipment based on the CPCI framework on the premise of not increasing the hardware cost and keeping higher test efficiency, the embodiment of the invention provides a hot switching system of the back plug board based on the CPCI framework.
Except a CPCI case, a CPCI main control computer and a CPCI back plate which meet the CPCI standard, the CPCI board card is mainly divided into two types according to different implementation functions: a general programmable main control board and a rear plug board.
In one embodiment of the back plug-in board hot switching system based on the CPCI framework, before the back plug-in board is switched, the main control computer software writes corresponding back plug-in board power-off instruction words into a PCI space designated address of the universal programmable main control board;
after the on-board FPGA of the general programmable main control board receives the power-off instruction word of the rear plug board, the on-board FPGA controls the on-board relay to cut off the power supply of the rear plug board;
after the switching of the rear plugboard, the main control computer writes corresponding rear plugboard electrifying instruction words into the PCI space designated address of the universal programmable main control board;
after the on-board FPGA of the general programmable main control board receives the power-on instruction word of the rear plug board, the on-board relay is controlled to recover the power supply of the rear plug board;
after the steps are completed, the main control computer sends the configuration file corresponding to the new back plug board to an onboard FPGA of the general programmable main control board through a CPCI bus, the FPGA carries out partial reconfiguration operation on the corresponding area of the FPGA after receiving the configuration file of the new back plug board, and the general programmable main control board completes the function switching of the new back plug board after the configuration is completed;
and finally, the universal programmable main control board accesses the interface circuit of the new rear plug board by utilizing the onboard bidirectional IO circuit to realize data exchange and control of the new rear plug board.
In one embodiment of the back plug board hot switching system based on the CPCI architecture, interfaces of the general programmable main control board and the CPCI back board are divided into a bidirectional IO interface and a power supply interface, and the general programmable main control board realizes control and data exchange of the back plug board through the bidirectional IO interface; through the power interface, the universal programmable main control board realizes the power supply control of the rear plug board.
Here, the implementation principle of the backplane hot-switch function is shown in fig. 1. The interfaces of the general programmable main control board and the CPCI back board are divided into a bidirectional IO interface and a power interface, and the two bidirectional IO interfaces and the power interface are connected through the CPCI back board. Through the bidirectional IO interface, the universal programmable main control board realizes the control and data exchange of the rear plug board; through the power interface, the universal programmable main control board realizes the power supply control of the rear plug board. Therefore, the universal programmable main control board is provided with a bidirectional IO buffer circuit and a power supply monitoring circuit to realize the functions.
In an embodiment of the back plug board hot-swap system based on the CPCI architecture, the general programmable main control board is connected with the main control computer through a J1 interface of the CPCI backplane, and the general programmable main control board is connected with the back plug board through a J3 interface and a J5 connector of the CPCI backplane.
In the embodiment of the present invention, the relationship between the host computer, the general programmable host control board, and the backplane interface is shown in fig. 2. Since the J1 interface in the CPCI standard protocol is a standard CPCI interface and is not detailed here, and the interfaces of J3 and J5 belong to user-defined interfaces, the present invention defines the signals of J3 and J5, and the interfaces thereof are mainly divided into two categories: power supply interfaces (± 12V, +5V, +3.3V), bidirectional IO interfaces (128-bit wide IO).
In an embodiment of the back plug board hot switching system based on the CPCI architecture, the bidirectional IO interface is connected to the bidirectional IO buffer chip output through the IO pin of the FPGA, and a structure diagram of the bidirectional IO buffer chip is shown in fig. 3.
In an embodiment of the back plug board hot switching system based on the CPCI architecture, the bidirectional IO interface of the universal programmable main control board is connected to the back plug board through the J4 interface or the J5 interface of the CPCI backplane.
In the embodiment of the invention, 128-bit bidirectional IO is used, so that the FPGA can communicate with interface chips (such as 422 bus and SPI bus) of different back plug boards.
In an embodiment of the back board hot-switch system based on the CPCI architecture, the ± 12V, +5V and +3.3V power supplies of the back board are provided by corresponding power supply pins in the J1 interface of the CPCI backplane through a power supply monitoring circuit of the general programmable main control board.
In an embodiment of the back plug board hot switching system based on the CPCI architecture, a +12V power supply is monitored as an example, a schematic block diagram of the power supply monitoring circuit is shown in fig. 4, and the power supply monitoring circuit includes a power supply monitoring chip and a relay. In order to avoid device damage possibly caused by hot plug of the back plug board, the embodiment of the invention uses the relay to independently control the power on and off of the back plug board, so that the power supply of the universal programmable main control board is not influenced when the back plug board is powered off. The power supply monitoring chip is used for monitoring the current, the voltage and the like of the connected power supply, and the relay is used for switching on and off the connected power supply. And the control end of the power supply monitoring circuit is connected to the FPGA of the universal programmable main control board, so that the FPGA can monitor the power supply condition of the rear plug board.
In the embodiment of the back plug board hot switching system based on the CPCI architecture, a data interface (such as SCL and SDA in fig. 4) of the power supply monitoring chip is connected to an on-board FPGA of the general programmable main control board, and the on-board FPGA outputs 1 IO for controlling the on-off of the relay. And periodically accessing the power state information of the power monitoring chip by the onboard FPGA program, and monitoring the instruction sent by the main control computer through the CPCI bus. When the onboard FPGA program detects a backboard power-off instruction, the onboard FPGA closes the relay through the relay control port, and then cuts off the power supply of the rear plug board.
In an embodiment of the back socket hot-swap system based on the CPCI architecture, after the back socket is swapped to a new back socket, the general programmable main control board needs to update a corresponding back socket control module program, so as to complete control and data exchange of the new back socket. To this end, embodiments of the present invention use on-board FPGA DPR technology. DPR is a technique for dynamically modifying FPGA logic blocks. Through the technology, a designer can download part of the reconfiguration bit stream to the FPGA to realize different functions while not influencing the normal operation of other logics, so that the design flexibility of the FPGA is greatly improved.
In the embodiment of the invention, logic resources of an onboard FPGA can be divided into two types according to whether DPR is needed or not: static logic (no reconfiguration required) and dynamic logic (reconfigurable). Static logic cannot be changed in the operation process, and dynamic logic can be dynamically modified according to requirements in the operation process of the FPGA. In the early design stage, a plurality of fixed areas can be divided on the FPGA for storing dynamic logic. These regions can be injected with different bit streams during operation by external or internal configuration ports, which enables the FPGA to dynamically switch functions during operation.
In the embodiment of the present invention, a functional block diagram of the DPR is shown in fig. 5. The on-board FPGA of the general programmable main control board is internally divided into two parts: a dynamic logic portion and a static logic portion. The dynamic logic part is used for storing a rear plug-in board control program. Because the dynamic logic part can realize dynamic update, different rear plugboard control programs can be stored according to different types of rear plugboards; and the static logic part is used for storing other programs which do not need to be dynamically updated, such as a CPCI interface module, a dynamic logic control module, a power supply monitoring module and the like.
In specific implementation, the update of the dynamic logic part is realized by a HWICAP (hardware internal Configuration Access Port) inside an onboard FPGA. The HWICAP module is connected with a CPCI interface module in the FPGA so that the main control computer can send a DPR bitstream file controlled by the back plug board to the general programmable main control board through the CPCI interface to update a back plug board control module program.
In specific implementation, an interface of the DPR module controlled by the backplane board may be defined according to actual application requirements, and for convenience of description, the interface of the DPR module controlled by the backplane board in the embodiment of the present invention is described as shown in fig. 6.
When the back plug board control program needs to be switched, main control computer software of the main control computer writes configuration data in a DPR file corresponding to the back plug board control program of the current back plug board into a PCI space corresponding register of the general programmable main control board, a CPCI interface module of the general programmable main control board continuously reads the data in the register and writes the data into a dynamic logic part of the back plug board control DPR module through HWICAP, and the HWICAP automatically resets the back plug board control DPR module when the configuration data is transmitted. And the back flashboard control DPR module uses an onboard programmable clock CLK _ EXT _ IN of the universal programmable main control board as a local working clock and finishes initialization operation. After the initialization is completed, the BACK board control DPR module exchanges data with the interface chip of the BACK board through ports such as BACK _ OUT [127:0], BACK _ IN [127:0] and BACK _ TRI [127:0] on one hand, and exchanges data with the CPCI interface module through ports such as USR _ OUT [31:0], USR _ OUT _ EN, USR _ OUT _ CLK, USR _ IN [31:0], USR _ IN _ EN and USR _ IN _ CLK on the other hand, for example, the control instruction sent by the interface CPCI module feeds BACK the state information to the CPCI module.
The back plug board hot switch design based on the CPCI framework provided by the invention enables the testing equipment based on the CPCI framework to realize the complex testing task which can be realized by a plurality of board cards in the past only by utilizing one universal programmable main control board and matching with different back plug boards through certain software and hardware design and utilizing the DPR (Dynamic Partial Reconfiguration) technology of the FPGA. In actual test, the control program of the back plug board of the general programmable main control board can be configured on line by the main control computer software, and the whole test equipment does not need to be closed in the configuration process, so that the test efficiency of the test equipment can be effectively improved.
In the embodiment of the backplane hot-swap system based on the CPCI architecture of the present invention, the DPR bitstream file for the backplane control of different functions is generated by the steps shown in fig. 7, which are described as follows:
s101: determining the area size of a DPR module controlled by a rear plug board which needs to carry out DPR operation in a general programmable main control board on-board FPGA, and setting the area size in an FPGA development environment;
s102: compiling each back plug board control DPR module code according to functions required to be realized by different back plug boards, and ensuring the correctness of the codes;
s103: and performing synthesis, layout and wiring operations on each module compiled in the S102 stage by using an FPGA development environment, and finally generating a back plug board control DPR module configuration bit stream file corresponding to each module.
The hot switching method of the rear plug board comprises the following steps:
s201: once the back plug board hot switching operation is detected to be needed, the main control computer software sends a back plug board power-off instruction to the general programmable main control board through the CPCI bus.
As shown in fig. 8, the embodiment of the present invention is implemented by writing a specific instruction word to a specified address of the PCI space of the general programmable main control board.
S202: once the FPGA on the general programmable main control board detects a power-off instruction of the rear plug board, the FPGA on the general programmable main control board controls a relay on the general programmable main control board to cut off the power supply of the rear plug board.
S203: taking out the rear inserting plate 1 and replacing the rear inserting plate with the rear inserting plate 2.
S204: after the rear plug-in board 2 is installed, the main control computer software sends a rear plug-in board power-on instruction to the general programmable main control board through the CPCI bus. The embodiment of the invention is realized by writing a specific instruction word into a PCI space designated address of a universal programmable main control board.
S205: once the FPGA on the general programmable main control board detects a power-on instruction of the rear plug board, the FPGA on the general programmable main control board controls the relay on the general programmable main control board to recover the power supply of the rear plug board.
S206: and the main control computer software opens a back plug board control DPR module configuration bit stream file corresponding to the back plug board 2, and sends data in the file to the general programmable main control board through the CPCI bus until all data transmission is completed. The general programmable main control board carries the FPGA to continuously receive the configuration bit stream data of the back plug board control DPR module of the back plug board 2 sent by the main control computer software. In the embodiment of the invention, the FPGA on board of the universal programmable main control board injects the data into the dynamic configuration area where the DPR module is located through the HWICAP back plug board. Once all data are sent, the FPGA on board of the general programmable main control board detects the initialization state of the DPR module controlled by the back plug board.
S207 to S208: once the back flashboard control DPR module is detected to be failed to initialize, the FPGA on the board of the general programmable main control board returns an error state to the main control computer through the CPCI bus, and the step S206 is repeated.
S209: and once the initialization success of the DPR module is detected, finishing the hot switching operation of the back plug board.
In summary, in order to solve the above problems, the present invention provides a back plug board hot-swap system based on a CPCI architecture, which ensures that the hot-swap of the back plug board of the test equipment is realized without closing the whole test equipment, thereby quickly switching the test function of the test equipment. Therefore, hardware cost can be effectively reduced, higher test efficiency can be guaranteed, all the other operations except conventional board plugging and unplugging operations can be completed by software, and the probability of board damage is effectively reduced.
The embodiment of the invention provides a method for hot switching of a back plug board based on a CPCI framework, which comprises the following steps:
when the hot switching operation of the rear plug-in board is needed (for example, the rear plug-in board 1 in the existing design is replaced by the rear plug-in board 2 with different functions), the main control computer controls a functional front plug-in board (hereinafter referred to as a universal programmable main control board) to cut off the power supply of the rear plug-in board; after the power of the rear plug board is cut off, an operator pulls out the rear plug board 1 and inserts the rear plug board 2; after the replacement of the rear plugboard, the master control computer controls the universal programmable master control board to recover the power supply of the rear plugboard; after power supply is recovered, the main control computer writes software corresponding to the functions of the rear plug-in board 2 into the universal programmable main control board to complete the switching of the functions of the rear plug-in board; after the function switching is completed, the general programmable main control board exchanges data with the back plug board through the CPCI back board to realize the control of the new back plug board.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (9)
1. The utility model provides a back flashboard hot switching system based on CPCI framework which characterized in that includes:
a main control computer;
the universal programmable main control board is used for connecting the rear plug board and the main control computer, and comprises an FPGA, a rear plug board power supply monitoring circuit, a CPCI interface circuit and a bidirectional IO circuit, the universal programmable main control board, the rear plug board and the main control computer are connected through a CPCI back board, a main chip of the universal programmable main control board adopts an onboard FPGA, and the universal programmable main control board controls and exchanges data with the interface circuit of the rear plug board through the bidirectional IO circuit; data exchange is carried out with the main control computer through a CPCI interface; the power supply condition of the rear plugboard is controlled and monitored by a rear plugboard power supply monitoring circuit;
and the rear plugboard is used for connecting the tested equipment and the universal programmable main control board and comprises a CPCI interface circuit and a tested equipment interface circuit.
2. The CPCI architecture-based hot-swap system for a back socket board according to claim 1, wherein before a back socket board is swapped, the main control computer software writes a corresponding back socket board power-off instruction word to a PCI space designated address of the general programmable main control board;
after the on-board FPGA of the general programmable main control board receives the power-off instruction word of the rear plug board, the on-board FPGA controls the on-board relay to cut off the power supply of the rear plug board;
after the switching of the rear plugboard, the main control computer writes corresponding rear plugboard electrifying instruction words into the PCI space designated address of the universal programmable main control board;
after the on-board FPGA of the general programmable main control board receives the power-on instruction word of the rear plug board, the on-board relay is controlled to recover the power supply of the rear plug board;
the main control computer sends the configuration file corresponding to the new back plug board to an onboard FPGA of the general programmable main control board through a CPCI bus, the FPGA carries out partial reconfiguration operation on a corresponding area of the FPGA after receiving the configuration file of the new back plug board, and the general programmable main control board finishes function switching of the new back plug board after the configuration is finished;
and the universal programmable main control board accesses the interface circuit of the new rear plug board by utilizing the onboard bidirectional IO circuit.
3. The CPCI-architecture-based backplane hot-swap system according to claim 1, wherein interfaces of the general programmable main control board and the CPCI backplane are divided into a bidirectional IO interface and a power interface, and the general programmable main control board implements control and data exchange with respect to the backplane through the bidirectional IO interface; through the power interface, the universal programmable main control board realizes the power supply control of the rear plug board.
4. The CPCI architecture-based backplane hot-swap system of claim 3, wherein the bi-directional IO interface is connected by an IO pin of the FPGA to a bi-directional IO buffer chip output.
5. The CPCI architecture based backplane hot-swap system of claim 1, wherein ± 12V, +5V, and +3.3V power supplies of the backplane are provided by corresponding power pins in the J1 interface of the CPCI backplane via power monitoring circuitry of the generic programmable main control board.
6. The CPCI architecture-based backplane hot-switch system according to claim 5, wherein the power monitoring circuit comprises a power monitoring chip and a relay, a control end of the power monitoring circuit is connected to an on-board FPGA of the general programmable main control board, the power monitoring chip is used for monitoring current, voltage and the like of the connected power supply, and the relay is used for powering on and powering off the connected power supply.
7. The CPCI architecture-based hot switching system for the back plug board of claim 6, wherein a data interface of the power supply monitoring chip is connected to an onboard FPGA of the general programmable main control board, the onboard FPGA outputs 1 IO for controlling on-off of the relay, an onboard FPGA program periodically accesses power state information of the power supply monitoring chip and monitors an instruction sent by the main control computer through a CPCI bus, when the onboard FPGA program detects a power-off instruction of the back board, the onboard FPGA closes the relay through a relay control port and further cuts off power supply of the back plug board, and when the onboard FPGA program detects a power-on instruction of the back board, the onboard FPGA opens the relay through the relay control port and further restores power supply of the back plug board.
8. The CPCI architecture-based backplane hot-swap system of claim 7, wherein the onboard FPGA employs a DPR module, and is internally divided into two parts: the dynamic logic part is used for storing a rear plug board control program; and the static logic part is used for storing other programs which are not required to be dynamically updated.
9. The CPCI-architecture-based backplane hot-swap system according to claim 8, wherein when a backplane control program is to be swapped, the host computer writes configuration data in a DPR module corresponding to the backplane control program of the current backplane into a PCI space corresponding register of the general programmable host computer, the CPCI interface module of the general programmable host computer continuously reads the data in the register and writes it into a dynamic logic portion of the backplane control DPR module through HWICAP, and the HWICAP automatically resets the backplane control DPR module when the configuration data is transferred;
the back flashboard control DPR module uses an onboard programmable clock CLK _ EXT _ IN of the general programmable main control board as a local working clock and finishes initialization operation;
after the initialization is completed, the BACK board control DPR module exchanges data with the interface chip of the BACK board through ports such as BACK _ OUT [127:0], BACK _ IN [127:0] and BACK _ TRI [127:0] on one hand, and exchanges data with the CPCI interface module through ports such as USR _ OUT [31:0], USR _ OUT _ EN, USR _ OUT _ CLK, USR _ IN [31:0], USR _ IN _ EN and USR _ IN _ CLK on the other hand.
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Application publication date: 20200818 |