CN111525961A - Analog front-end circuit of optical receiver and optical receiver - Google Patents
Analog front-end circuit of optical receiver and optical receiver Download PDFInfo
- Publication number
- CN111525961A CN111525961A CN202010346116.6A CN202010346116A CN111525961A CN 111525961 A CN111525961 A CN 111525961A CN 202010346116 A CN202010346116 A CN 202010346116A CN 111525961 A CN111525961 A CN 111525961A
- Authority
- CN
- China
- Prior art keywords
- output
- optical receiver
- emitter
- analog front
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
Landscapes
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Amplifiers (AREA)
Abstract
The invention provides an optical receiver analog front end circuit and an optical receiver, comprising: the transimpedance operational amplifier is connected with the photodiode and the direct current bias current and used for converting a photocurrent signal output by the photodiode into a differential voltage signal with set bandwidth and gain; the first inter-stage coupling module is connected with the output end of the transimpedance operational amplifier and used for reducing the output direct-current working point voltage of the transimpedance operational amplifier and realizing impedance matching; the limiting amplifier is connected with the output end of the first inter-stage coupling module and is used for amplifying the signal output by the first inter-stage coupling module and simultaneously widening the bandwidth; the second inter-stage coupling module is connected with the output end of the limiting amplifier and used for reducing the output direct-current working point voltage of the limiting amplifier and realizing impedance matching; and the output buffer is connected with the output end of the second inter-stage coupling module and is used for realizing the matching of output impedance and simultaneously widening the bandwidth. The invention can realize high bandwidth, high gain and low noise.
Description
Technical Field
The present invention relates to the field of integrated circuit design, and in particular, to an analog front-end circuit of an optical receiver and an optical receiver.
Background
The analog front-end circuit of the optical receiver plays an indispensable role in the optical communication system. The optical receiver is an important component of an optical fiber communication system, and the core structure of the optical receiver is a Trans-impedance amplifier (TIA), which is mainly used for converting a photocurrent signal generated by a photodiode, amplifying the photocurrent signal, and converting the amplified photocurrent signal into a voltage signal for sampling and analysis of a subsequent circuit. The noise, gain and bandwidth of the transimpedance amplifier (TIA) directly affect the sensitivity and speed of the overall system, and its performance determines to a large extent the performance of the overall optical receiver and thus the overall communication system. The conventional analog front-end circuit of the optical receiver includes a Limiting Amplifier (LA) (or an Automatic Gain Control (AGC)) in addition to a transimpedance amplifier to form a two-stage amplifier, but this structure is intended to have a certain bottleneck in simultaneously achieving high bandwidth, high Gain, and low noise.
The traditional trans-impedance amplifier is generally divided into a common-source trans-impedance structure and a common-gate trans-impedance structure, wherein a resistor is bridged between a grid electrode and a drain electrode of a common-source amplifier, the equivalent input impedance of the structure is very large, and the structure and an equivalent input capacitor of a detector form a very large pole, so that the bandwidth of the trans-impedance amplifier is greatly reduced. The noise characteristics of the amplifier are poorer than those of a common source trans-impedance amplifier with feedback. The existing RGC structure trans-impedance amplifier has very low input impedance and can support high bandwidth application, but the noise performance of the existing RGC structure trans-impedance amplifier is poorer than that of a band closed loop feedback common source structure trans-impedance amplifier. The traditional Cherry-Hooper structure limiting amplifier pushes the pole to a high frequency position by a method of reducing the inter-stage resistance, so that the bandwidth is expanded, but the structure cannot sufficiently drive the capacitive load of the output end and isolate the influence of the inter-stage capacitance, and the bandwidth expansion is limited. In a conventional multistage active feedback type limiting amplifier, the total bandwidth is ensured by increasing the bandwidth of a single-stage amplifier, but the power consumption is increased, and meanwhile, the peaking gain is increased, so that the noise performance is seriously influenced. The traditional trans-impedance amplifier adopts a two-stage operational amplifier structure, so that the improvement of gain is limited, and weak signals cannot be amplified. The interstage coupling of the trans-impedance amplifier and the limiting amplifier and the interstage coupling of the limiting amplifier and the output buffer circuit adopt the traditional direct coupling mode to cause impedance mismatching, zero pole offset occurs, and the bandwidth is severely limited. The use of capacitive coupling to reduce the coupled dc bias voltage limits the low frequency response and affects noise performance.
Therefore, how to combine the high bandwidth, high gain, and low noise of the analog front-end circuit of the optical receiver has become one of the problems to be solved by those skilled in the art.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an analog front-end circuit of an optical receiver and an optical receiver, which are used to solve the problem that the analog front-end circuit of the optical receiver in the prior art cannot simultaneously achieve high bandwidth, high gain and low noise.
To achieve the above and other related objects, the present invention provides an optical receiver analog front end circuit, which at least includes:
the device comprises a transimpedance operational amplifier, a first inter-stage coupling module, a limiting amplifier, a second inter-stage coupling module and an output buffer;
the first input end of the transimpedance operational amplifier is connected with a photocurrent signal output by the photodiode, and the second input end of the transimpedance operational amplifier receives direct current bias current and is used for converting the photocurrent signal into a differential voltage signal with set bandwidth and gain, wherein the direct current bias current is equal to the direct current part of the photocurrent signal;
the first inter-stage coupling module is connected to the output end of the transimpedance operational amplifier and used for reducing the output direct-current working point voltage of the transimpedance operational amplifier and realizing impedance matching;
the limiting amplifier is connected to the output end of the first inter-stage coupling module and is used for amplifying the signal output by the first inter-stage coupling module and simultaneously widening the bandwidth;
the second inter-stage coupling module is connected with the output end of the limiting amplifier and used for reducing the output direct-current working point voltage of the limiting amplifier and realizing impedance matching;
the output buffer is connected with the output end of the second inter-stage coupling module and used for realizing the matching of output impedance and simultaneously widening the bandwidth.
Optionally, the transimpedance operational amplifier includes a first common-emitter amplification unit, a first emitter following negative feedback unit, a second emitter following negative feedback unit, a first degenerated capacitor and a second degenerated capacitor of a differential structure;
the positive phase input end of the first common-emitter amplification unit is connected with the photocurrent signal, and the negative phase input end of the first common-emitter amplification unit is connected with the direct-current bias current;
the first emitter following negative feedback unit is connected between the positive phase input end and the negative phase output end of the first common-emitter amplification unit, provides a negative feedback signal for the positive phase input end of the first common-emitter amplification unit, and outputs a negative phase output signal;
the second emitter following negative feedback unit is connected between the inverting input end and the positive phase output end of the first common-emitter amplification unit, provides a negative feedback signal for the inverting input end of the first common-emitter amplification unit, and outputs a positive phase output signal;
one end of the first degeneration capacitor is connected with the inverting output end of the first common-emitter amplification unit and the connection node of the first emitter following negative feedback unit, and the other end of the first degeneration capacitor is connected with the non-inverting output end of the first common-emitter amplification unit;
one end of the second degeneration capacitor is connected with the positive phase output end of the first common-emitter amplification unit and the connection node of the second emitter following negative feedback unit, and the other end of the second degeneration capacitor is connected with the inverted phase output end of the first common-emitter amplification unit.
More optionally, the current source in the transimpedance operational amplifier is implemented by an NMOS current mirror.
Optionally, the first inter-stage coupling module comprises an emitter follower.
Optionally, the limiting amplifier includes a two-stage common-emitter amplifying unit with a differential structure, a third emitter following negative feedback unit and a fourth emitter following negative feedback unit;
a collector electrode of a second-stage transistor in the two-stage cascode unit is connected with a source electrode of an NMOS adjustable resistor, a drain electrode of the NMOS adjustable resistor is connected with power supply voltage through a load, a grid electrode of the NMOS adjustable resistor is connected with adjusting voltage, the resistance value of the NMOS adjustable resistor is changed through the adjusting voltage, and then the value of a low-frequency zero point is adjusted;
the third emitter following negative feedback unit and the fourth emitter following negative feedback unit are respectively connected between the drain of the NMOS adjustable resistor and the base of the second-stage transistor, and provide negative feedback signals for the second stage of the two-stage common-emitter amplification unit.
More optionally, the current source in the limiting amplifier is implemented by an NMOS current mirror.
Optionally, the second inter-stage coupling module comprises an emitter follower.
Optionally, the output buffer includes a second cascode unit with a differential structure, a third degenerated capacitor, and a fourth degenerated capacitor;
two loads connected with the transistor in series in the second common-emitter amplification unit are connected to a power supply voltage through a first inductor and a second inductor respectively;
one end of the third degenerated capacitor is connected with the inverting input end of the second cascode unit, and the other end of the third degenerated capacitor is connected with the inverting output end of the second cascode unit;
one end of the fourth degeneration capacitor is connected with the positive phase input end of the second cascode unit, and the other end of the fourth degeneration capacitor is connected with the positive phase output end of the second cascode unit.
More optionally, the current source in the output buffer is implemented by an NMOS current mirror.
Optionally, the output buffer further includes a variable capacitor, and two ends of the variable capacitor are respectively connected to the emitters of the two transistors in the second cascode unit.
More optionally, the optical receiver analog front-end circuit further includes a third inductor, and the third inductor is connected between the photodiode and the first input terminal of the transimpedance operational amplifier.
More optionally, the optical receiver analog front-end circuit further includes a fourth inductor, and the fourth inductor is connected between the output end of the first inter-stage coupling module and the input end of the limiting amplifier.
More optionally, the optical receiver analog front end circuit is designed based on a SiGe BiCMOS process.
To achieve the above and other related objects, the present invention provides an optical receiver including at least:
a photodiode, the optical receiver analog front end circuit, a clock data recovery circuit, a tap and a digital logic circuit;
the photodiode is connected with the input end of the analog front-end circuit of the optical receiver and is used for detecting optical signals and generating corresponding photocurrent signals;
the analog front-end circuit of the optical receiver amplifies the photocurrent signal and converts the photocurrent signal into a voltage signal;
the clock data recovery circuit is connected to the output end of the optical receiver analog front-end circuit, receives an output signal of the optical receiver analog front-end circuit and performs clock recovery;
the demultiplexer is connected to the output end of the clock data recovery circuit and distributes signals output by the clock data recovery circuit into multiple paths of output;
and the digital logic circuit is connected to the output end of the tap and is used for processing the signal output by the tap.
As described above, the analog front-end circuit of an optical receiver and the optical receiver according to the present invention have the following advantageous effects:
1. the analog front-end circuit of the optical receiver and the optical receiver adopt the multistage coupling pseudo-differential structure amplification circuit, the gain accumulation of the multistage circuit can realize high-gain output, the pseudo-differential structure can inhibit common-mode noise interference, low-noise output is realized, the dynamic range of output voltage is improved, and the output gain is improved.
2. The analog front-end circuit of the optical receiver and the optical receiver improve the trans-impedance amplifier, Miller compensation is formed by bridging the degraded capacitor, the pole is pushed to a high-frequency position, and the bandwidth is expanded.
3. The analog front-end circuit of the optical receiver and the optical receiver improve the Cherry-Hooper structure limiting amplifier, adopt the MOS type adjustable resistor to adjust the output voltage gain, not only can reduce the output direct current level and increase the output voltage gain, but also introduce a low-frequency zero point, so that a high-frequency conjugate pole becomes a dominant pole, and the bandwidth expansion and the stability improvement are realized.
4. The optical receiver simulates a front-end circuit and adds a degenerated capacitor in a buffer circuit to form a negative miller compensation structure, so that the miller effect is reduced, and the bandwidth is effectively expanded; and a variable capacitor is also added, an adjustable zero is introduced for zero pole compensation, the zero pole compensation is adjusted to be a proper value, the gain roll-off caused by an output pole can be compensated, the bandwidth is expanded, and the bandwidth flatness is adjusted.
5. The optical receiver analog front-end circuit and the optical receiver adopt the MOS type active current mirror, have low starting voltage and low source-drain voltage when working in a saturation region, are suitable for a low-voltage working circuit and provide proper bias current for the circuit.
Drawings
Fig. 1 is a schematic diagram of an analog front-end circuit of an optical receiver according to the present invention.
Fig. 2 is a schematic circuit diagram of the transimpedance operational amplifier according to the present invention.
Fig. 3 is a schematic diagram showing a circuit configuration of a limiting amplifier according to the present invention.
FIG. 4 is a schematic circuit diagram of an output buffer according to the present invention.
Fig. 5 is a schematic circuit diagram of the optical receiver according to the present invention.
Description of the element reference numerals
1 optical receiver analog front end circuit
11 transimpedance operational amplifier
12 first inter-stage coupling module
13 limiting amplifier
14 second inter-stage coupling module
15 output buffer
2 clock data recovery circuit
3 shunting device
4 digital logic circuit
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 5. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Example one
As shown in fig. 1, the present embodiment provides an optical receiver analog front end circuit 1, where the optical receiver analog front end circuit 1 includes:
the circuit comprises a transimpedance operational amplifier 11, a first inter-stage coupling module 12, a limiting amplifier 13, a second inter-stage coupling module 14 and an output buffer 15.
As shown in fig. 1, a first input terminal of the transimpedance operational amplifier 11 receives a photocurrent signal Iin output by the photodiode, and a second input terminal thereof receives a dc bias current Id for converting the photocurrent signal Iin into a differential voltage signal with a set bandwidth and gain, where the dc bias current Id is equal to a dc component of the photocurrent signal Iin.
Specifically, as shown in fig. 2, in the present embodiment, the transimpedance operational amplifier 11 includes a first common-emitter amplifying unit, a first emitter following negative feedback unit, a second emitter following negative feedback unit, a first degenerated capacitor C1, and a second degenerated capacitor C2 in a differential structure.
More specifically, a non-inverting input terminal of the first cascode unit is connected to the photocurrent signal Iin, and an inverting input terminal thereof is connected to the dc bias current Id. In the present embodiment, the first cascode unit includes a first transistor Q1, a second transistor Q2, a first resistor R1, a second resistor R2, and a first current source. The first transistor Q1 and the second transistor Q2 are NPN transistors. The emitter of the first transistor Q1 is connected to ground via the first current source, the base is connected to the photocurrent signal Iin, and the collector is connected to the power supply voltage VCC via a first resistor R1. The emitter of the second transistor Q2 is connected to ground via the first current source, the base is connected to the dc bias current Id, and the collector is connected to the power supply voltage VCC via a second resistor R2.
More specifically, the first emitter following negative feedback unit is connected between the positive phase input terminal and the inverted phase output terminal of the first cascode unit, provides a negative feedback signal to the positive phase input terminal of the first cascode unit, and outputs an inverted phase output signal. In this embodiment, the first emitter follower negative feedback unit includes a third transistor Q3, a third resistor R3, and a second current source. The third transistor Q3 is an NPN transistor. The collector of the third transistor Q3 is connected to the power supply voltage VCC, the base is connected to the collector of the first transistor Q1, and the emitter is connected to the first end of the third resistor R3 and serves as an inverted output terminal Voutn; the second terminal of the third resistor R3 is connected to the base of the first transistor Q1 and to ground via a second current source.
More specifically, the second emitter following negative feedback unit is connected between the inverting input terminal and the non-inverting output terminal of the first cascode unit, provides a negative feedback signal to the inverting input terminal of the first cascode unit, and outputs a non-inverting output signal. In this embodiment, the second emitter follower negative feedback unit includes a fourth transistor Q4, a fourth resistor R4, and a third current source. The fourth transistor Q4 is an NPN transistor. The collector of the fourth transistor Q4 is connected to the power supply voltage VCC, the base is connected to the collector of the second transistor Q2, and the emitter is connected to the first end of the fourth resistor R4 and serves as a non-inverting output terminal Voutp; a second terminal of the fourth resistor R4 is connected to the base of the second transistor Q2 and to ground via a third current source.
More specifically, one end of the first degeneration capacitor C1 is connected to a connection node between the inverting output terminal of the first common-emitter amplification unit and the first emitter follower negative feedback unit, and the other end is connected to the non-inverting output terminal of the first common-emitter amplification unit. In this embodiment, one end of the first degeneration capacitor C1 is connected to the base of the third transistor Q3, and the other end is connected to the collector of the second transistor Q2.
More specifically, one end of the second degeneration capacitor C2 is connected to a connection node between the non-inverting output terminal of the first common-emitter amplification unit and the second emitter follower negative feedback unit, and the other end is connected to the inverting output terminal of the first common-emitter amplification unit. In this embodiment, one end of the second degeneration capacitor C2 is connected to the base of the fourth transistor Q4, and the other end is connected to the collector of the first transistor Q1.
More specifically, the first current source, the second current source and the third current source are implemented by NMOS current mirrors, and include a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3 and a fourth NMOS transistor N4. In this embodiment, the drain of the first NMOS transistor N1 receives the bias current Ibias and is connected to the gate of the first NMOS transistor N1, and the source of the first NMOS transistor N1 is grounded. The gate of the second NMOS transistor N2 is connected to the gate of the first NMOS transistor N1, the source is grounded, and the drain provides the first current source. The gate of the third NMOS transistor N3 is connected to the gate of the first NMOS transistor N1, the source is grounded, and the drain provides the second current source. The gate of the fourth NMOS transistor N4 is connected to the gate of the first NMOS transistor N1, the source is grounded, and the drain provides the third current source.
The transimpedance operational amplifier 11 is a differential parallel feedback common-emitter circuit with emitter follower, a photocurrent signal Iin output by the photodiode PD is input from an inverting input terminal, amplified by the first transistor Q1, and forms a parallel negative feedback loop with emitter follower by the third transistor Q3 and the third resistor R3, so that signal linearity can be effectively improved, noise can be reduced, a direct current working point can be changed, and the load carrying capacity of an output terminal can be increased; the direct current bias current Id is input from the positive phase input end and used for generating average photocurrent to keep balance with the photocurrent signal Iin, so that the common mode differential voltage output is kept to be zero, the common mode rejection ratio is improved, and the noise is reduced; in addition, the first degenerated capacitor C1 forms miller compensation between the second transistor Q2 and the third transistor Q3, and the second degenerated capacitor C2 forms miller compensation between the first transistor Q1 and the fourth transistor Q4, pushing poles to high frequencies, and further expanding bandwidth.
The closed loop transimpedance gain of the transimpedance operational amplifier 11 can be expressed as:
wherein, gm1Is the transconductance, R, of the first transistor Q1 and the second transistor Q21Is the resistance value of the first resistor R1 and the second resistor R2, RfIs the resistance of the third resistor R3 and the fourth resistor R4. Increase RfThe output gain can be effectively improved, but the bandwidth can be reduced, and R can be considered in practical use according to practical requirementsfThe value of (c).
For damping of
Its-3 dB bandwidth can be expressed as:
wherein A is0For open loop gain, with a value equal to gm1·R1；CinIs the input terminal equivalent capacitance.
The first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, and the fourth NMOS transistor N4 form an active current mirror, and each current output can be expressed as:
Iout＝(W/L)i*Ibias/(W/L)1；
wherein, (W/L)1The ratio of the gate width to the gate length of the first NMOS tube N1, (W/L)i(i is 2,3,4) is a ratio of a gate width to a gate length of the second NMOS transistor N2, the third NMOS transistor N3, and the fourth NMOS transistor N4, and the output current is adjusted by adjusting the gate width and the gate length. The MOS type active current mirror has low starting voltage and low source-drain voltage when working in a saturation region, is suitable for a low-voltage working circuit and provides proper bias current for the circuit.
As shown in fig. 1, the first inter-stage coupling module 12 is connected to the output end of the transimpedance operational amplifier 11, and is configured to reduce an output dc operating point voltage of the transimpedance operational amplifier 11 and implement impedance matching.
Specifically, in the present embodiment, the first inter-stage coupling module 12 adopts an emitter follower structure, and the detailed structure is not repeated herein.
As shown in fig. 1, the limiting amplifier 13 is connected to the output end of the first inter-stage coupling module 12, and is configured to amplify the signal output by the first inter-stage coupling module 12, so as to provide a preset bandwidth and a preset gain for a subsequent circuit.
Specifically, as shown in fig. 3, in the present embodiment, the limiting amplifier 13 includes a two-stage cascode unit having a differential structure, a third emitter following negative feedback unit, and a fourth emitter following negative feedback unit.
More specifically, a collector of a second-stage transistor in the two-stage cascode unit is connected with a source of an NMOS adjustable resistor, a drain of the NMOS adjustable resistor is connected with a power supply voltage through a load, a gate of the NMOS adjustable resistor is connected with an adjusting voltage, a resistance value of the NMOS adjustable resistor is changed through the adjusting voltage, and then a value of a low-frequency zero point is adjusted. In this embodiment, the two-stage cascode amplifying unit includes a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, an eighth transistor Q8, a fifth resistor R5, a sixth resistor R6, a first NMOS adjustable resistor N9, a second NMOS adjustable resistor N10, a fourth current source, a fifth current source, and a sixth current source. The fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are all NPN triodes. The emitter of the fifth transistor Q5 (first stage transistor) is grounded via a fourth current source, the base is used as the inverting input Vn and receives the inverted output signal of the first inter-stage coupling module 12, and the collector is connected to the base of the sixth transistor Q6 (second stage transistor). The emitter of the sixth transistor Q6 is grounded via a sixth current source, the base is connected to the collector of the fifth transistor Q5, and the collector is connected to the source of the first NMOS adjustable resistor N9 and serves as the inverted output terminal Voutn. The gate of the first NMOS adjustable resistor N9 receives an adjustment voltage Vg, and the drain is connected to the supply voltage VCC via the fifth resistor R5. The emitter of the seventh transistor Q7 (the first stage transistor) is connected to ground via a fifth current source, the base thereof is used as the non-inverting input terminal Vp and receives the non-inverting output signal of the first inter-stage coupling module 12, and the collector thereof is connected to the base of the eighth transistor Q8 (the second stage transistor). The emitter of the eighth transistor Q8 is grounded via the sixth current source, the base is connected to the collector of the seventh transistor Q7, and the collector is connected to the source of the second NMOS adjustable resistor N10 and serves as the non-inverting output terminal Voutp. The gate of the second NMOS adjustable resistor N10 receives the adjustment voltage Vg, and the drain is connected to the supply voltage VCC via the sixth resistor R6.
More specifically, the third emitter following negative feedback unit and the fourth emitter following negative feedback unit are respectively connected between the drain of the NMOS adjustable resistor and the base of the second stage transistor, and provide a negative feedback signal for the second stage of the two-stage cascode unit. In this embodiment, the third emitter follower negative feedback unit includes a seventh resistor R7, a ninth transistor Q9, and an eighth resistor R8. The ninth transistor Q9 is an NPN transistor. One end of the seventh resistor R7 is connected to the power supply voltage VCC, and the other end is connected to the collector of the ninth transistor Q9. The base of the ninth transistor Q9 is connected to the drain of the first NMOS adjustable resistor N9, and the emitter is connected to the base of the sixth transistor Q6 via the eighth resistor R8. In the present embodiment, the fourth emitter-follower negative feedback unit includes a ninth resistor R9, a tenth transistor Q10, and a tenth resistor R10. The tenth transistor Q10 is an NPN transistor. One end of the ninth resistor R9 is connected to the power supply voltage VCC, and the other end is connected to the collector of the tenth transistor Q10. The base of the tenth transistor Q10 is connected to the drain of the second NMOS adjustable resistor N10, and the emitter is connected to the base of the eighth transistor Q8 via the tenth resistor R10.
More specifically, the fourth current source, the fifth current source and the sixth current source are implemented by NMOS current mirrors, and include a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7 and an eighth NMOS transistor N8. The drain of the fifth NMOS transistor N5 receives the bias current Ibias and is connected to the gate of the fifth NMOS transistor N5, and the source of the fifth NMOS transistor N5 is grounded. The gate of the sixth NMOS transistor N6 is connected to the gate of the fifth NMOS transistor N5, the source is grounded, and the drain provides the fourth current source. The gate of the seventh NMOS transistor N7 is connected to the gate of the fifth NMOS transistor N5, the source is grounded, and the drain provides the fifth current source. The gate of the eighth NMOS transistor N8 is connected to the gate of the fifth NMOS transistor N5, the source is grounded, and the drain provides the sixth current source.
The limiting amplifier 13 adopts a Cherry-Hooper structure with an adjustable resistor added. The differential circuit is composed of a common emitter amplifying circuit and an emitter follower in two-stage cascade connection, the ninth transistor Q9 and the tenth transistor Q10 are inserted into a feedback path as emitter followers, load capacitance is driven conveniently, meanwhile collectors of the sixth transistor Q6 and the eighth transistor Q8 are separated from the load capacitance, and the output impedance of the emitter followers is further reduced through the feedback path. In addition, the resistances between the collectors of the fifth transistor Q5 and the seventh transistor Q7 and the output end signals are small, so that the poles can be pulled to high frequencies, and the bandwidth can be expanded.
Through the voltage division of the first NMOS adjustable resistor N9 and the second NMOS adjustable resistor N10, the dc level of the output end can be effectively reduced, the output voltage gain is increased, and a low-frequency zero point is also introduced:
ωz≈-(R2+RN)/R2RNCπ1；
wherein R is2Is the resistance of the fifth resistor R5 and the sixth resistor R6; rNThe resistances of the first NMOS adjustable resistor N9 and the second NMOS adjustable resistor N10; cπ1Is the base-emitter capacitance of the ninth transistor Q9 and the tenth transistor Q10. R is realized by adjusting the voltage of the adjusting voltage VgNThe adjustment of the size further adjusts the size of the zero value, realizes zero pole offset, enables a high-frequency conjugate pole to become a dominant pole, realizes the expansion of bandwidth, and simultaneously improves the stability.
Neglecting the length modulation, the adjustable resistance can be equivalent to:
wherein, munFor electron mobility, CoxIs unit area gate oxide capacitance, VGSIs a gate-source voltage, VTHIs the threshold voltage.
The fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7, and the eighth NMOS transistor N8 form an active current mirror, and the relationship of each current output requirement is the same as that in the transimpedance operational amplifier 11, which is not repeated herein. The current mirror formed by the NMOS tubes can realize low-voltage operation and provide proper bias current.
As the output voltage increases, the dc level of the collector output voltages of the sixth transistor Q6 and the eighth transistor Q8 does not increase, and the output swing of the output signal can be further increased, which is favorable for improving the gain. The circuit gain of the limiting amplifier 13 can be expressed as:
wherein, gm2Is the transconductance of the fifth transistor Q5 and the seventh transistor Q7; gm3Is the transconductance of the sixth transistor Q6 and the eighth transistor Q8; gm4Is the transconductance of the ninth transistor Q9 and the tenth transistor Q10; r3The resistance values of the seventh resistor R7 and the ninth resistor R9; cπ2Is the base-emitter capacitance, C, of the sixth transistor Q6 and the eighth transistor Q8LIs an output load capacitance; s is a Laplacian factor.
As shown in fig. 1, the second inter-stage coupling module 14 is connected to the output end of the limiting amplifier 13, and is configured to reduce the output dc operating point voltage of the limiting amplifier 13, and perform impedance matching with a subsequent circuit.
Specifically, in the present embodiment, the second inter-stage coupling module 14 adopts an emitter follower structure, and the detailed structure is not repeated herein.
As shown in fig. 1, the output buffer 15 is connected to the output end of the second inter-stage coupling module 14, and is used for matching output impedance, implementing an equalization effect, improving bandwidth and flatness, and providing a certain gain.
Specifically, as shown in fig. 4, the output buffer 15 includes a second cascode unit having a differential structure, a third degeneration capacitor C3 and a fourth degeneration capacitor C4.
More specifically, two loads connected in series with the transistor in the second cascode cell are connected to the power supply voltage VCC through the first inductor L1 and the second inductor L2, respectively. In this embodiment, the second cascode unit includes an eleventh transistor Q11, a twelfth transistor Q12, an eleventh resistor R11, a twelfth resistor R12, a first inductor L1, a second inductor L2, and a seventh current source. The eleventh transistor Q11 and the twelfth transistor Q12 are both NPN transistors. The emitter of the eleventh transistor Q11 is grounded via the seventh current source, the base thereof is used as the inverting input terminal Vn and receives the inverting output signal of the second inter-coupling module 14, and the collector thereof is connected to the first terminal of the eleventh resistor R11 and is used as the non-inverting output terminal Voutp. A second terminal of the eleventh resistor R11 is connected to the supply voltage VCC via the first inductor L1. The emitter of the twelfth transistor Q12 is grounded via the seventh current source, the base thereof is used as the non-inverting input terminal Vp, and the collector thereof is connected to the first terminal of the twelfth resistor R12 and is used as the inverting output terminal Voutn. A second end of the twelfth resistor R12 is connected to the power supply voltage VCC via the second inductor L2.
More specifically, one end of the third degeneration capacitor C3 is connected to the inverting input terminal of the second cascode unit, and the other end is connected to the inverting output terminal of the second cascode unit. In this embodiment, one end of the third degeneration capacitor C3 is connected to the base of the eleventh transistor Q11, and the other end is connected to the collector of the twelfth transistor Q12.
More specifically, one end of the fourth degeneration capacitor C4 is connected to the non-inverting input terminal of the second cascode unit, and the other end is connected to the non-inverting output terminal of the second cascode unit. In this embodiment, one end of the fourth degeneration capacitor C4 is connected to the base of the twelfth transistor Q12, and the other end is connected to the collector of the eleventh transistor Q11.
More specifically, the seventh current source is implemented by an NMOS current mirror, and includes an eleventh NMOS transistor N11 and a twelfth NMOS transistor N12. The drain of the eleventh NMOS transistor N11 receives the bias current Ibias and is connected to the gate of the twelfth NMOS transistor N12, and the source of the eleventh NMOS transistor N11 is grounded. The gate of the twelfth NMOS transistor N12 is connected to the gate of the eleventh NMOS transistor N11, the source is grounded, and the drain provides the seventh current source.
The output buffer 15 is a common emitter amplifier circuit with a differential structure, wherein the eleventh resistor R11 and the twelfth resistor R12 are resistors matched with an output terminal (in this embodiment, the resistance thereof is a constant value of 50 Ω), and the first inductor L1 and the second inductor L2 are parallel inductors to perform peaking for extending bandwidth. The third degenerated capacitor C3 and the fourth degenerated capacitor C4 form a negative Miller compensation structure, so that the Miller effect is reduced, and the bandwidth can be effectively expanded.
More specifically, as another implementation form of the present invention, the output buffer 15 further includes a variable capacitor Cvar, one end of the variable capacitor Cvar is connected to the emitter of the eleventh transistor Q11, and the other end of the variable capacitor Cvar is connected to the emitter of the twelfth transistor Q12. The variable capacitor Cvar introduces an adjustable zero for zero-pole compensation, adjusts the zero-pole compensation to a proper value (the zero-pole compensation is set according to actual needs, and details are not repeated here), can compensate gain roll-off caused by an output pole, expands bandwidth and adjusts bandwidth flatness.
The eleventh NMOS transistor N11 and the twelfth NMOS transistor N12 form an active current mirror, and the relationship of each current output is the same as that in the transimpedance operational amplifier 11, which is not described herein again. The current mirror formed by the NMOS tubes can realize low-voltage operation and provide proper bias current.
The gain of the output buffer 15 can be expressed as:
AV3＝gm5R4
wherein, gm5Is transconductance of the eleventh transistor Q11 and the twelfth transistor Q12, R4Is the resistance of the eleventh resistor R11 and the twelfth resistor R12.
As shown in fig. 1, as an implementation manner of the present invention, the optical receiver analog front-end circuit 1 further includes a third inductor L3, where the third inductor L3 is connected between the photodiode PD and the first input terminal of the transimpedance operational amplifier 11, and is used for peaking a signal and increasing a bandwidth.
As shown in fig. 1, as another implementation manner of the present invention, the optical receiver analog front-end circuit 1 further includes a fourth inductor L4, where the fourth inductor L4 is connected between the output end of the first inter-stage coupling module 12 and the input end of the limiting amplifier 13; the fourth inductor L4 includes two coils, which are respectively connected to the two differential signals. The fourth inductor L4 is used to supplement the gain drop caused by the previous stage circuit and expand the bandwidth.
As an implementation manner of the present invention, the analog front-end circuit of the optical receiver of the present invention is designed based on the SiGe BiCMOS process, and in practical use, the BiCMOS process of other materials is also applicable to the present invention, which is not limited to this embodiment.
The analog front-end circuit of the optical receiver can realize high gain by adopting a multi-stage coupling pseudo-differential amplifying circuit, and pseudo-differential can effectively inhibit power supply noise and substrate noise and realize low-noise output; the improved parallel feedback common emitter stage circuit structure with emitter stage following can realize high-bandwidth and low-noise output; the improved Cherry-Hooper structure limiting amplifier can drive the capacitance load of the output end, further expand the bandwidth and simultaneously improve the output gain and stability; the improved output stage Buffer circuit is adopted to realize the equalization effect, improve the bandwidth and the flatness and further improve the gain; the inter-stage coupling mode can reduce the direct current bias voltage and meet the requirement of impedance matching; the bandwidth can be effectively expanded by adopting an inductance peaking technology and a capacitance degradation technology; and the multistage trans-impedance amplifier designed based on the SiGe BiCMOS process realizes high gain, high bandwidth and low noise.
Example two
As shown in fig. 5, the present embodiment provides an optical receiver including: the optical receiver comprises a photodiode PD, an optical receiver analog front end circuit 1, a clock data recovery circuit 2, a demultiplexer 3 and a digital logic circuit 4.
As shown in fig. 5, the photodiode PD is connected to an input end of the analog front-end circuit 1 of the optical receiver, and is configured to detect an optical signal and generate a corresponding photocurrent signal Iin.
As shown in fig. 5, the optical receiver analog front end circuit 1 amplifies and converts the photocurrent signal Iin into a voltage signal.
Specifically, the specific structure and principle of the analog front-end circuit 1 of the optical receiver refer to the first embodiment, which is not described herein again.
As shown in fig. 5, the Clock Data Recovery (CDR) circuit 2 is connected to an output end of the optical receiver analog front end circuit 1, and receives an output signal of the optical receiver analog front end circuit 1 and performs Clock recovery.
Specifically, the clock data recovery circuit 2 recovers an embedded clock from data, more specifically, extracts a receiving bit synchronization clock from a received digital signal with large interference and jitter, and resamples the data signal with the clock to recover an original data signal with a standard waveform, which is basically intended to determine an optimal clock phase of read data and sample. The circuit structure of the clock data recovery circuit 2 is not limited, and any hardware and software that can realize the clock data recovery are applicable, which are not described herein again.
As shown in fig. 5, the demultiplexer 3(DMUX) is connected to the output end of the clock data recovery circuit 2, and distributes the signals output by the clock data recovery circuit 2 into multiple outputs.
As shown in fig. 5, the digital logic circuit 4 is connected to the output terminal of the tap 3, and processes the signal output from the tap 3.
Specifically, the digital logic circuit 4 may be configured with different functions based on actual needs, which is not described in detail herein.
In summary, the present invention provides an analog front end circuit of an optical receiver and an optical receiver, including: the transimpedance operational amplifier is connected with the photodiode at a first input end, receives direct current bias current at a second input end, and is used for converting a photocurrent signal output by the photodiode into a differential voltage signal with set bandwidth and gain, wherein the direct current bias current is equal to the direct current part of the photocurrent signal; the first inter-stage coupling module is connected to the output end of the transimpedance operational amplifier and used for reducing the output direct-current working point voltage of the transimpedance operational amplifier and realizing impedance matching; the limiting amplifier is connected to the output end of the first inter-stage coupling module and used for amplifying the signal output by the first inter-stage coupling module and simultaneously widening the bandwidth; the second inter-stage coupling module is connected with the output end of the limiting amplifier and used for reducing the output direct-current working point voltage of the limiting amplifier and realizing impedance matching; and the output buffer is connected with the output end of the second inter-stage coupling module and is used for realizing the matching of output impedance. The analog front-end circuit of the optical receiver and the optical receiver can realize high bandwidth, high gain and low noise. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (14)
1. An optical receiver analog front-end circuit, comprising:
the device comprises a transimpedance operational amplifier, a first inter-stage coupling module, a limiting amplifier, a second inter-stage coupling module and an output buffer;
the first input end of the transimpedance operational amplifier is connected with a photocurrent signal output by the photodiode, and the second input end of the transimpedance operational amplifier receives direct current bias current and is used for converting the photocurrent signal into a differential voltage signal with set bandwidth and gain, wherein the direct current bias current is equal to the direct current part of the photocurrent signal;
the first inter-stage coupling module is connected to the output end of the transimpedance operational amplifier and used for reducing the output direct-current working point voltage of the transimpedance operational amplifier and realizing impedance matching;
the limiting amplifier is connected to the output end of the first inter-stage coupling module and is used for amplifying the signal output by the first inter-stage coupling module and simultaneously widening the bandwidth;
the second inter-stage coupling module is connected with the output end of the limiting amplifier and used for reducing the output direct-current working point voltage of the limiting amplifier and realizing impedance matching;
the output buffer is connected with the output end of the second inter-stage coupling module and used for realizing the matching of output impedance and simultaneously widening the bandwidth.
2. The optical receiver analog front-end circuit of claim 1, wherein: the trans-impedance operational amplifier comprises a first common-emitter amplification unit, a first emitter following negative feedback unit, a second emitter following negative feedback unit, a first degenerated capacitor and a second degenerated capacitor, wherein the first common-emitter amplification unit, the first emitter following negative feedback unit, the second emitter following negative feedback unit, the first degenerated capacitor and the second degenerated capacitor are of a differential structure;
the positive phase input end of the first common-emitter amplification unit is connected with the photocurrent signal, and the negative phase input end of the first common-emitter amplification unit is connected with the direct-current bias current;
the first emitter following negative feedback unit is connected between the positive phase input end and the negative phase output end of the first common-emitter amplification unit, provides a negative feedback signal for the positive phase input end of the first common-emitter amplification unit, and outputs a negative phase output signal;
the second emitter following negative feedback unit is connected between the inverting input end and the positive phase output end of the first common-emitter amplification unit, provides a negative feedback signal for the inverting input end of the first common-emitter amplification unit, and outputs a positive phase output signal;
one end of the first degeneration capacitor is connected with the inverting output end of the first common-emitter amplification unit and the connection node of the first emitter following negative feedback unit, and the other end of the first degeneration capacitor is connected with the non-inverting output end of the first common-emitter amplification unit;
one end of the second degeneration capacitor is connected with the positive phase output end of the first common-emitter amplification unit and the connection node of the second emitter following negative feedback unit, and the other end of the second degeneration capacitor is connected with the inverted phase output end of the first common-emitter amplification unit.
3. The optical receiver analog front-end circuit of claim 2, wherein: the current source in the transimpedance operational amplifier is realized by an NMOS current mirror.
4. The optical receiver analog front-end circuit of claim 1, wherein: the first inter-stage coupling module includes an emitter follower.
5. The optical receiver analog front-end circuit of claim 1, wherein: the limiting amplifier comprises a two-stage common-emitter amplification unit with a differential structure, a third emitter following negative feedback unit and a fourth emitter following negative feedback unit;
a collector electrode of a second-stage transistor in the two-stage cascode unit is connected with a source electrode of an NMOS adjustable resistor, a drain electrode of the NMOS adjustable resistor is connected with power supply voltage through a load, a grid electrode of the NMOS adjustable resistor is connected with adjusting voltage, the resistance value of the NMOS adjustable resistor is changed through the adjusting voltage, and then the value of a low-frequency zero point is adjusted;
the third emitter following negative feedback unit and the fourth emitter following negative feedback unit are respectively connected between the drain of the NMOS adjustable resistor and the base of the second-stage transistor, and provide negative feedback signals for the second stage of the two-stage common-emitter amplification unit.
6. The optical receiver analog front-end circuit of claim 5, wherein: the current source in the limiting amplifier is realized by an NMOS current mirror.
7. The optical receiver analog front-end circuit of claim 1, wherein: the second inter-stage coupling module includes an emitter follower.
8. The optical receiver analog front-end circuit of claim 1, wherein: the output buffer comprises a second common-emitter amplification unit with a differential structure, a third degenerated capacitor and a fourth degenerated capacitor;
two loads connected with the transistor in series in the second common-emitter amplification unit are connected to a power supply voltage through a first inductor and a second inductor respectively;
one end of the third degenerated capacitor is connected with the inverting input end of the second cascode unit, and the other end of the third degenerated capacitor is connected with the inverting output end of the second cascode unit;
one end of the fourth degeneration capacitor is connected with the positive phase input end of the second cascode unit, and the other end of the fourth degeneration capacitor is connected with the positive phase output end of the second cascode unit.
9. The optical receiver analog front-end circuit of claim 8, wherein: the current source in the output buffer is realized by an NMOS current mirror.
10. The optical receiver analog front-end circuit of claim 8, wherein: the output buffer further comprises a variable capacitor, and two ends of the variable capacitor are respectively connected with the emitters of the two transistors in the second common-emitter amplification unit.
11. The optical receiver analog front-end circuit according to any one of claims 1 to 10, wherein: the optical receiver analog front-end circuit further comprises a third inductor, and the third inductor is connected between the photodiode and the first input end of the transimpedance operational amplifier.
12. The optical receiver analog front-end circuit of claim 11, wherein: the optical receiver analog front-end circuit further comprises a fourth inductor, and the fourth inductor is connected between the output end of the first inter-stage coupling module and the input end of the limiting amplifier.
13. The optical receiver analog front-end circuit of claims 1 to 10, wherein: the optical receiver analog front end circuit is designed based on a SiGe BiCMOS process.
14. An optical receiver, characterized in that it comprises at least:
a photodiode, an analog front end circuit of an optical receiver according to any one of claims 1 to 13, a clock data recovery circuit, a demultiplexer, and a digital logic circuit;
the photodiode is connected with the input end of the analog front-end circuit of the optical receiver and is used for detecting optical signals and generating corresponding photocurrent signals;
the analog front-end circuit of the optical receiver amplifies the photocurrent signal and converts the photocurrent signal into a voltage signal;
the clock data recovery circuit is connected to the output end of the optical receiver analog front-end circuit, receives an output signal of the optical receiver analog front-end circuit and performs clock recovery;
the demultiplexer is connected to the output end of the clock data recovery circuit and distributes signals output by the clock data recovery circuit into multiple paths of output;
and the digital logic circuit is connected to the output end of the tap and is used for processing the signal output by the tap.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010346116.6A CN111525961A (en) | 2020-04-27 | 2020-04-27 | Analog front-end circuit of optical receiver and optical receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010346116.6A CN111525961A (en) | 2020-04-27 | 2020-04-27 | Analog front-end circuit of optical receiver and optical receiver |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111525961A true CN111525961A (en) | 2020-08-11 |
Family
ID=71902983
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010346116.6A Pending CN111525961A (en) | 2020-04-27 | 2020-04-27 | Analog front-end circuit of optical receiver and optical receiver |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111525961A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112910565A (en) * | 2021-01-22 | 2021-06-04 | 天津大学 | PAM4 signal receiving and demodulating circuit applied to high-speed optical interconnection |
| CN114039562A (en) * | 2021-11-16 | 2022-02-11 | 成都明夷电子科技有限公司 | Low-cost over-frequency high-speed trans-impedance amplifier |
| CN114095092A (en) * | 2022-01-21 | 2022-02-25 | 微龛(广州)半导体有限公司 | Optical receiving module and equalization compensation method |
| CN114221626A (en) * | 2021-12-17 | 2022-03-22 | 厦门亿芯源半导体科技有限公司 | High-speed trans-impedance amplifier with bandwidth expansion characteristic in full temperature range and bandwidth expansion method |
| CN114337841A (en) * | 2022-03-10 | 2022-04-12 | 华中科技大学 | Analog front end module of ultra-wideband optical receiver |
| CN115694660A (en) * | 2022-09-13 | 2023-02-03 | 北京无线电测量研究所 | T-shaped matching resonance enhanced photoelectric detector receiving network |
| CN116317966A (en) * | 2023-03-29 | 2023-06-23 | 南京米乐为微电子科技有限公司 | Amplifying circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090245807A1 (en) * | 2008-03-25 | 2009-10-01 | Rintaro Nomura | Optical power monitoring circuit, optical transceiver, optical module, optical receiver, amplifier circuit, and integrated circuit |
| CN106027159A (en) * | 2016-07-06 | 2016-10-12 | 天津大学 | Analog front-end circuit for fully-differential optical receiver based on adjustable common-emitter common-base structure |
| CN109698723A (en) * | 2018-12-29 | 2019-04-30 | 武汉大学 | A kind of fully integrated photoreceiver of silica-based high speed for chip chamber light network |
-
2020
- 2020-04-27 CN CN202010346116.6A patent/CN111525961A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090245807A1 (en) * | 2008-03-25 | 2009-10-01 | Rintaro Nomura | Optical power monitoring circuit, optical transceiver, optical module, optical receiver, amplifier circuit, and integrated circuit |
| CN106027159A (en) * | 2016-07-06 | 2016-10-12 | 天津大学 | Analog front-end circuit for fully-differential optical receiver based on adjustable common-emitter common-base structure |
| CN109698723A (en) * | 2018-12-29 | 2019-04-30 | 武汉大学 | A kind of fully integrated photoreceiver of silica-based high speed for chip chamber light network |
Non-Patent Citations (4)
| Title |
|---|
| 宋奇伟: "基于标准SiGe BiCMOS工艺的宽带全差分光接收机的研制", 《中国博士学位论文全文数据库 信息科技辑》 * |
| 毕查德·拉扎维（BEHZAD RAZAVI）: "《模拟CMOS集成电路设计》", 28 February 2003 * |
| 谷由之: "基于SiGe BiCMOS工艺的光接收机模拟前端电路的研究", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
| 黄丽薇，王迷迷: "《模拟电子电路》", 31 December 2016 * |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112910565A (en) * | 2021-01-22 | 2021-06-04 | 天津大学 | PAM4 signal receiving and demodulating circuit applied to high-speed optical interconnection |
| CN112910565B (en) * | 2021-01-22 | 2021-10-26 | 天津大学 | PAM4 signal receiving and demodulating circuit applied to high-speed optical interconnection |
| CN114039562A (en) * | 2021-11-16 | 2022-02-11 | 成都明夷电子科技有限公司 | Low-cost over-frequency high-speed trans-impedance amplifier |
| CN114221626A (en) * | 2021-12-17 | 2022-03-22 | 厦门亿芯源半导体科技有限公司 | High-speed trans-impedance amplifier with bandwidth expansion characteristic in full temperature range and bandwidth expansion method |
| WO2023108793A1 (en) * | 2021-12-17 | 2023-06-22 | 厦门亿芯源半导体科技有限公司 | High-speed trans-impedance amplifier having bandwidth extension characteristic within full-temperature range, and bandwidth extension method |
| CN114095092A (en) * | 2022-01-21 | 2022-02-25 | 微龛(广州)半导体有限公司 | Optical receiving module and equalization compensation method |
| CN114337841A (en) * | 2022-03-10 | 2022-04-12 | 华中科技大学 | Analog front end module of ultra-wideband optical receiver |
| CN114337841B (en) * | 2022-03-10 | 2022-06-07 | 华中科技大学 | Analog front end module of ultra-wideband optical receiver |
| CN115694660A (en) * | 2022-09-13 | 2023-02-03 | 北京无线电测量研究所 | T-shaped matching resonance enhanced photoelectric detector receiving network |
| CN115694660B (en) * | 2022-09-13 | 2023-09-22 | 北京无线电测量研究所 | T-shaped matching resonance enhanced photoelectric detector receiving network |
| CN116317966A (en) * | 2023-03-29 | 2023-06-23 | 南京米乐为微电子科技有限公司 | Amplifying circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111525961A (en) | Analog front-end circuit of optical receiver and optical receiver | |
| WO2010100741A1 (en) | Optical communication apparatus | |
| CN105393453A (en) | Apparatus and method for transimpedance amplifiers with wide input current ranges | |
| CN101180793A (en) | Fast setting, low noise, low offset operational amplifier and method | |
| Meyer et al. | A wideband low-noise variable-gain BiCMOS transimpedance amplifier | |
| JP3541750B2 (en) | Optical receiving preamplifier | |
| CN112039452B (en) | Broadband trans-impedance amplifier | |
| CN110601663B (en) | High-speed voltage feedback amplifier with current feedback amplifier characteristics | |
| CN103840775B (en) | Limiting amplifier allowing direct-current offset eliminating function to be achieved on sheet | |
| CN111835299A (en) | Variable gain amplifier with variable bandwidth | |
| US6107883A (en) | High gain, high speed rail-to-rail amplifier | |
| JP2000223963A (en) | High frequency amplifier | |
| CN110798162B (en) | Radio frequency ultra-wideband driving amplifier chip | |
| JP7344506B2 (en) | transimpedance amplifier | |
| CN113630096B (en) | Rail-to-rail output circuit of high-speed fully-differential amplifier and high-speed fully-differential amplifier | |
| CN107592086B (en) | High-gain ultrahigh-working-rate amplifier circuit | |
| CN112272061A (en) | Analog front-end circuit of optical receiver | |
| CN111756343B (en) | Rail-to-rail output circuit for high-speed operational amplifier | |
| US5963085A (en) | Input to output stage interface with virtual ground circuitry for rail to rail comparator | |
| Zhang et al. | A low-noise 71-dBΩ transimpedance 31-GHz bandwidth optical receiver with automatic gain control in 0.13-µm SiGe BiCMOS | |
| Liang et al. | 2.5 Gb/s CMOS RGC transimpedance amplifier | |
| CN113328711B (en) | Constant cross-rail-to-rail input differential output high-speed programmable gain amplifier | |
| CN115412041B (en) | Low-noise fully-differential amplifier comprising common-mode feedback circuit | |
| CN117411445B (en) | Broadband variable gain amplifier for optical receiver | |
| CN113422582A (en) | High bandwidth linear variable gain amplifier |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200811 |