CN111525896A - High-gain high-bandwidth variable gain amplifier and amplifier chip - Google Patents
High-gain high-bandwidth variable gain amplifier and amplifier chip Download PDFInfo
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Abstract
The invention discloses a high-gain high-bandwidth variable gain amplifier and an amplifier chip, wherein the variable gain amplifier comprises a transconductance amplifier and a trans-impedance amplifier which are arranged in two stages; the input end of the first-stage transconductance amplifier receives an input signal, amplifies the input voltage signal and converts the amplified voltage signal into a current signal; and the input end of the second-stage trans-impedance amplifier is connected with the output end of the first-stage trans-impedance amplifier and is used for further amplifying the signal and converting the current signal into a voltage signal. The variable gain amplifier chip adopts the variable gain amplifier. When the gain of the second-stage TIA of the variable gain amplifier is changed, the invention only changes the resistance value of the variable resistor connected across the input end, does not influence the stability of the TIA, and reduces the input resistor under the condition of large signals, thereby improving the linearity. The invention is applied to the high-speed optical receiving chip for PAM-4 mode transmission and coherent light detection in 100G/200G/400G Ethernet.
Description
Technical Field
The invention belongs to the technical field of optical communication chip design, and particularly relates to a high-gain high-bandwidth variable gain amplifier and an amplifier chip.
Background
In recent years, with the continuous popularization and development of cloud computing, high-performance computing, high-definition video on demand and the like, high-bandwidth network applications are ubiquitous, and the network bandwidth of a core and data center is increasing at an exponential rate. From the early 10Gb/s and 40Gb/s Ethernet to the mature commercial use of the 100Gb/s technology, the industry is further accelerated to advance the development and industrialization process of the 400Gb/s or even 1Tb/s ultra-high speed transmission technology, and the demand for larger capacity and higher transmission rate is higher in the future.
An optical receiver generally includes a transimpedance amplifier (TIA), a Variable Gain Amplifier (VGA), a data clock recovery Circuit (CDR), and the like. The optical signal from the optical fiber is received by the photodetector to generate a photocurrent proportional to the intensity of the received light. The trans-impedance amplifier amplifies the photocurrent and converts the photocurrent into a voltage signal, and the voltage signal is further amplified by the VGA so that the voltage signal can be processed by the CDR.
The main performance indicators of a variable gain amplifier include bandwidth, gain and linearity. The circuit must have sufficient bandwidth for signal transmission quality. Because the TIA output is small and the input signal required by CDR is large, a VGA with high gain is required for amplification, and the gain of VGA is generally not less than 20 dB. Currently, PAM-4 modulation has replaced NRZ modulation at 50Gb/s and above, thus requiring the amplification circuit to operate in the linear region all the time; in contrast, NRZ modulation does not have high requirements on circuit linearity. For the PAM-4 signal, in order to ensure that 4 levels can be well distinguished, the 4 levels are required to be distributed at equal intervals, so that the circuit has high requirements on linearity.
Common VGA architectures include: the VGA is based on a Gilbert unit, because output nodes of the VGA are connected with 4 output tubes, parasitic capacitance is large, and in addition, when gain is changed, half of the input tubes can cause reduction of linearity because of reduction of current, and the VGA is not beneficial to signal transmission; the VGA can generate an in-band zero point due to the fact that a large capacitor is added in a source stage by changing a common source amplifier of a source feedback resistor, and therefore multi-degree peaking is generated in frequency response to influence signal transmission quality. Therefore, the performance of the VGA circuits is compromised, and thus high-speed optical communication systems are required to have VGAs with high gain, high bandwidth, and high linearity.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a high-gain high-bandwidth variable gain amplifier and an amplifier chip, which solve the high requirements of the system on the bandwidth and the gain, thereby achieving excellent performance.
The invention is realized by adopting the following technical scheme:
a high-gain high-bandwidth variable gain amplifier comprises a transconductance amplifier and a trans-impedance amplifier which are arranged in two stages; the input end of the first-stage transconductance amplifier receives an input signal, amplifies the input voltage signal and converts the amplified voltage signal into a current signal; and the input end of the second-stage trans-impedance amplifier is connected with the output end of the first-stage trans-impedance amplifier and is used for further amplifying the signal and converting the current signal into a voltage signal.
The invention has the further improvement that the transconductance amplifier adopts two pairs of differential input tubes, and both adopt a source negative feedback structure;
the input tube of the first differential pair is composed of two P-type MOS tubes M5 and M6, the load is composed of two N-type MOS tubes M1 and M2, and the negative feedback resistors are all variable resistors Rs；
In the second pair of differential pairs, the input tube is composed of two P-type MOS tubes M7 and M8, the load is composed of two N-type MOS tubes M3 and M4, and the negative feedback resistors are all variable resistors Rs1；
The first pair of differential pairs are connected as follows:
the gate end of M5 is connected with the gate ends of input ends VINN and M7, the source end of M5 is connected with a current source I1 and a resistor Rs, and the drain end of M5 is connected with the drains of output ends VOUTP and M1;
the gate end of M6 is connected with the gate ends of input ends VINPP and M8, the source end of M6 is connected with a current source I2 and a resistor Rs, and the drain end of M6 is connected with the drain ends of output ends VOUTN and M2;
the grid end of the M1 is connected with the drain ends of the resistors Rp1 and M7 and the drain end of the M3, the source end of the M1 is connected with the ground, and the drain end of the M1 is connected with the drain ends of the output ends VOUTP and M5;
the grid end of the M2 is connected with the drain ends of the resistors Rp2 and M8 and the drain end of the M4, the source end of the M2 is connected with the ground, and the drain end of the M2 is connected with the drain ends of the output ends VOUTN and M6;
one end of the resistor Rs is connected with the source ends of the current sources I1 and M5, and the other end of the resistor Rs is connected with the source ends of the current sources I2 and M6;
the connection mode of the second pair of differential pairs is as follows:
the gate end of M7 is connected with the gate ends of input ends VINN and M5, the source end of M7 is connected with a current source I3 and a resistor Rs1, and the drain end of M7 is connected with the gate end of M1 and the drain ends of resistors Rp1 and M3;
the gate end of M8 is connected with the gate ends of input ends VINP and M6, the source end of M8 is connected with a current source I4 and a resistor Rs1, and the drain end of M8 is connected with the gate end of M2 and the drain ends of resistors Rp2 and M4;
the gate end of the M3 is connected with the resistor Rp1, the source end of the M3 is grounded, and the drain end of the M3 is connected with the gate ends of the resistors Rp1 and M1 and the drain end of the M7;
the gate end of the M4 is connected with the resistor Rp2, the source end of the M4 is grounded, and the drain end of the M4 is connected with the gate ends of the resistors Rp2 and M2 and the drain end of the M8;
one end of a resistor Rp1 is connected with the gate end of M1, the drain end of M7 and the drain end of M3, and the other end of the resistor Rp1 is connected with the gate end of M3;
one end of a resistor Rp2 is connected with the gate end of M2, the drain end of M8 and the drain end of M4, and the other end of the resistor Rp2 is connected with the gate end of M4;
resistance Rs1One end of the resistor R is connected with the source ends of the current sources I3 and M7s1The other end is connected with the source ends of the current source I4 and M8.
The invention has the further improvement that the trans-impedance amplifier is formed by adopting a feedforward path and a feedback path, the feedforward path adopts a structure of an inverter, the performance is changed by adopting a variable resistor, and the performance compensation is carried out by adopting an inductor; the feedback circuit adopts a resistance feedback mode;
the feed-forward path consists of two P-type MOS tubes M9 and M10, three N-type MOS tubes M11, M12 and M13, a current source Itail and two inductors L5 and L6;
the feedback circuit consists of a resistor RF1 and a resistor RF 2;
the connection mode of the feedforward circuit is as follows:
the gate end of M9 is connected with the gate ends of resistors RF1 and M11 and the drain ends of input ends VINN and M13, the source end of M9 is connected with the source ends of current sources Itail and M10, and the drain end of M9 is connected with the drain ends of resistors RF1, inductors L5 and M11;
the gate end of M10 is connected with the gate ends of resistors RF2 and M12 and the gate ends of input ends VINP and M13, the source end of M10 is connected with the source ends of current sources Itail and M9, and the drain end of M10 is connected with the drain ends of resistors RF2, inductors L6 and M12;
the gate end of M11 is connected with the drain ends of input ends VINN and M13 and the gate ends of resistors RF1 and M9, the source end of M11 is connected with the ground, and the drain end of M11 is connected with the drain ends of a resistor RF1, an inductor L5 and an inductor M9;
the gate end of M12 is connected with the source ends of input ends VINP and M13 and the gate ends of resistors RF2 and M10, the source end of M12 is connected with the ground, and the drain end of M12 is connected with the drain ends of a resistor RF2, an inductor L6 and an inductor M10;
the gate end of M13 is connected with input end VGA _ Ctrl, the source end of M13 is connected with input end VINP, the gate end of M10, the gate end of M12 and resistor RF2, the drain end of M13 is connected with input end VINN, the gate end of M9, the gate end of M11 and resistor RF 1;
one end of an inductor L5 is connected with the drain terminals of the resistors RF1 and M9 and the drain terminal of the resistor M11, and the other end of the inductor L5 is connected with an output terminal VOUTP;
one end of an inductor L6 is connected with the drain terminals of the resistors RF2 and M10 and the drain terminal of the resistor M12, and the other end of the inductor L6 is connected with an output terminal VOUTN;
the feedback circuit is connected in the following way:
one end of the resistor RF1 is connected with the input end VINN, the gate end of the M9, the gate end of the M11 and the drain end of the M13, and the other end of the resistor RF1 is connected with the drain ends of the inductors L5 and M9 and the drain end of the M11;
one end of the resistor RF2 is connected with the input end VINP, the gate end of the M10, the gate end of the M12 and the source end of the M13, and the other end of the resistor RF2 is connected with the drain ends of the inductors L6 and M10 and the drain end of the M12.
A high-gain high-bandwidth variable gain amplifier chip adopts the high-gain high-bandwidth variable gain amplifier.
Compared with the prior art, the invention has at least the following beneficial technical effects:
the variable gain amplifier with high gain and high bandwidth provided by the invention adopts a two-stage structure, and the gain of the two-stage circuit structure is variable, so that the effect of high gain can be obtained; the transconductance amplifier adopted by the first stage changes the gain by changing the resistance value of the feedback resistor instead of changing the current, so that the linearity of the circuit is not reduced; the first-stage transconductance amplifier adopts a mirror-image circuit structure, the transconductance of the circuit is increased, and the gain of the amplifier is increased; the second-stage trans-impedance amplifier changes the gain by changing the size of the parallel resistor, so that the stability of the circuit is not influenced when the gain is changed, the linearity of the circuit can be kept unchanged along with the increase of an input signal, and the complexity of the circuit is reduced; the second-stage trans-impedance amplifier is parallel-parallel feedback, so that the output impedance of an output point is reduced, and the bandwidth of the circuit is increased.
The variable gain amplifier chip with high gain and high bandwidth provided by the invention can be widely applied to a high-speed optical communication system due to the high bandwidth performance; because of the characteristic of high linearity, the method can be widely applied to high-order signal transmission systems; because of its high gain performance, it can be widely applied to optical receiver and optical transmitter system; because each performance is excellent, the chip can be widely applied to high-speed optical receiving chips of PAM-4 mode transmission and coherent light detection in 100G/200G/400G Ethernet.
In conclusion, at the receiving end of optical communication, the invention can ensure both the high gain and the high bandwidth of the variable gain amplifier, and can ensure the high linearity of signal transmission in the transmission of PAM-4 signals; meanwhile, when the gain is changed, the stability of the system is not influenced.
Drawings
FIG. 1 is a schematic diagram of a variable gain amplifier design according to the present invention;
FIG. 2 is a schematic diagram of a transconductance amplifier design according to the present invention;
FIG. 3 is a schematic diagram of a conventional transimpedance amplifier design;
FIG. 4 is a schematic diagram of a transimpedance stage amplifier design according to the present invention;
FIG. 5 is a schematic diagram of a transimpedance stage amplifier circuit design according to the present invention;
FIG. 6 is a schematic diagram of a variable gain amplifier applied to a 28nm CMOS process according to the present invention.
Detailed Description
The invention is further described below with reference to the following figures and examples.
The invention provides a high-gain high-bandwidth variable gain amplifier, which comprises a transconductance amplifier and a transimpedance amplifier which are arranged in two stages; the input end of the first-stage transconductance amplifier receives an input signal, amplifies the input voltage signal and converts the amplified voltage signal into a current signal; and the input end of the second-stage trans-impedance amplifier is connected with the output end of the first-stage trans-impedance amplifier and is used for further amplifying the signal and converting the current signal into a voltage signal.
The transconductance amplifier adopts two pairs of differential input tubes and adopts a source-level negative feedback structure.
The input tube of the first differential pair is composed of two P-type MOS tubes M5 and M6, the load is composed of two N-type MOS tubes M1 and M2, and the negative feedback resistors are all variable resistors Rs(ii) a In the second pair of differential pairs, the input tube is composed of two P-type MOS tubes M7 and M8, the load is composed of two N-type MOS tubes M3 and M4, and the negative feedback resistors are all variable resistors Rs1。
The first pair of differential pairs are connected as follows:
the gate end of M5 is connected with the gate ends of input ends VINN and M7, the source end of M5 is connected with a current source I1 and a resistor Rs, and the drain end of M5 is connected with the drains of output ends VOUTP and M1; the gate end of M6 is connected with the gate ends of input ends VINPP and M8, the source end of M6 is connected with a current source I2 and a resistor Rs, and the drain end of M6 is connected with the drain ends of output ends VOUTN and M2; the grid end of the M1 is connected with the drain ends of the resistors Rp1 and M7 and the drain end of the M3, the source end of the M1 is connected with the ground, and the drain end of the M1 is connected with the drain ends of the output ends VOUTP and M5; the grid end of the M2 is connected with the drain ends of the resistors Rp2 and M8 and the drain end of the M4, the source end of the M2 is connected with the ground, and the drain end of the M2 is connected with the drain ends of the output ends VOUTN and M6; one end of the resistor Rs is connected with the source ends of the current sources I1 and M5, and the other end of the resistor Rs is connected with the source ends of the current sources I2 and M6.
The connection mode of the second pair of differential pairs is as follows:
the gate end of M7 is connected with the gate ends of input ends VINN and M5, the source end of M7 is connected with a current source I3 and a resistor Rs1, and the drain end of M7 is connected with the gate end of M1 and the drain ends of resistors Rp1 and M3; the gate end of M8 is connected with the gate ends of input ends VINP and M6, the source end of M8 is connected with a current source I4 and a resistor Rs1, and the drain end of M8 is connected with the gate end of M2 and the drain ends of resistors Rp2 and M4; the gate end of the M3 is connected with the resistor Rp1, the source end of the M3 is grounded, and the drain end of the M3 is connected with the gate ends of the resistors Rp1 and M1 and the drain end of the M7; the gate end of the M4 is connected with the resistor Rp2, the source end of the M4 is grounded, and the drain end of the M4 is connected with the gate ends of the resistors Rp2 and M2 and the drain end of the M8; one end of a resistor Rp1 is connected with the gate end of M1, the drain end of M7 and the drain end of M3, and the other end of the resistor Rp1 is connected with the gate end of M3; one end of a resistor Rp2 is connected with the gate end of M2, the drain end of M8 and the drain end of M4, and the other end of the resistor Rp2 is connected with the gate end of M4; resistance Rs1One end of the resistor R is connected with the source ends of the current sources I3 and M7s1The other end is connected with the source ends of the current source I4 and M8.
The trans-impedance amplifier is composed of a feedforward path and a feedback path, the feedforward path adopts a structure of an inverter, a variable resistor is adopted to change the performance, and an inductor is adopted to perform performance compensation; the feedback circuit adopts a resistance feedback mode; the feed-forward path consists of two P-type MOS tubes M9 and M10, three N-type MOS tubes M11, M12 and M13, a current source Itail and two inductors L5 and L6; the feedback circuit consists of a resistor RF1 and a resistor RF 2.
The connection mode of the feedforward circuit is as follows:
the gate end of M9 is connected with the gate ends of resistors RF1 and M11 and the drain ends of input ends VINN and M13, the source end of M9 is connected with the source ends of current sources Itail and M10, and the drain end of M9 is connected with the drain ends of resistors RF1, inductors L5 and M11; the gate end of M10 is connected with the gate ends of resistors RF2 and M12 and the gate ends of input ends VINP and M13, the source end of M10 is connected with the source ends of current sources Itail and M9, and the drain end of M10 is connected with the drain ends of resistors RF2, inductors L6 and M12; the gate end of M11 is connected with the drain ends of input ends VINN and M13 and the gate ends of resistors RF1 and M9, the source end of M11 is connected with the ground, and the drain end of M11 is connected with the drain ends of a resistor RF1, an inductor L5 and an inductor M9; the gate end of M12 is connected with the source ends of input ends VINP and M13 and the gate ends of resistors RF2 and M10, the source end of M12 is connected with the ground, and the drain end of M12 is connected with the drain ends of a resistor RF2, an inductor L6 and an inductor M10; the gate end of M13 is connected with input end VGA _ Ctrl, the source end of M13 is connected with input end VINP, the gate end of M10, the gate end of M12 and resistor RF2, the drain end of M13 is connected with input end VINN, the gate end of M9, the gate end of M11 and resistor RF 1; one end of an inductor L5 is connected with the drain terminals of the resistors RF1 and M9 and the drain terminal of the resistor M11, and the other end of the inductor L5 is connected with an output terminal VOUTP; one end of the inductor L6 is connected with the drain terminals of the resistors RF2 and M10 and the drain terminal of the resistor M12, and the other end of the inductor L6 is connected with the output terminal VOUTN.
The feedback circuit is connected in the following way:
one end of the resistor RF1 is connected with the input end VINN, the gate end of the M9, the gate end of the M11 and the drain end of the M13, and the other end of the resistor RF1 is connected with the drain ends of the inductors L5 and M9 and the drain end of the M11; one end of the resistor RF2 is connected with the input end VINP, the gate end of the M10, the gate end of the M12 and the source end of the M13, and the other end of the resistor RF2 is connected with the drain ends of the inductors L6 and M10 and the drain end of the M12.
The invention provides a high-gain high-bandwidth variable gain amplifier chip, which adopts the high-gain high-bandwidth variable gain amplifier.
Examples
For a high-speed variable gain amplifier for 112Gb/s PAM-4 signals, high bandwidth, high gain, high linearity are required, and therefore how this can be achieved is described below.
Referring to fig. 1, the present invention is a schematic diagram of a design scheme of a variable gain amplifier, and the overall structure is divided into two stages, including a transconductance amplifier and a transimpedance amplifier (TIA), and this structure may also be referred to as a Cherry-Hooper amplifier. The first stage realizes the conversion from voltage to current, and the second stage TIA amplifies the current into voltage.
Referring to fig. 2, the present invention is a schematic diagram of a transconductance amplifier design, in which the size of the inner differential pair M7 and M8 is one fourth of the size of the outer differential pair transistors M5 and M6, and the current generated by the inner differential pair is amplified twice by the NMOS current mirror, which can double the total transconductance of the circuit. Compared with the traditional CML circuit, the new structure improves the effective transconductance by two times, but the power consumption and the input capacitance are only increased by 1.25 times.
Fig. 3 is a schematic diagram of a commonly used design scheme of a transimpedance amplifier, which changes the gain by changing the resistance of a feedback resistor. Reducing the feedback resistance to reduce the transimpedance gain alone causes loop stability problems because the open loop dominant pole is raised while the open loop secondary dominant pole is unchanged, resulting in a reduced phase margin, which can cause undesirable peaks in the closed loop frequency response and ringing and overshoot in the time domain, thereby degrading eye diagram quality. The traditional method for solving the problem is as follows: the gain of the built-in forward amplifier is reduced by the same multiple, so that the loop gain reduction multiple is the same as the lifting multiple of the dominant pole, and the loop is ensured to be
Invariant, where A is the feed forward amplifier gain, CinTIs the total input capacitance, CinT＝Cin1,2+CD1,2。
The disadvantages of this method are reflected in: on the one hand, it is necessary to change R simultaneouslyF3,4A, a circuit is complex, the operation is complicated, and the same change multiple of the circuit and the operation is difficult to ensure in application; on the other hand, the trans-impedance amplifier has differential input impedance
The input voltage swing borne by the TIA input end increases and the linearity becomes worse as the input AC current increases. Therefore, the second-stage trans-impedance amplifier of the variable gain amplifier of the invention does not adopt the structure.
The invention provides a circuit design method of a linear trans-impedance amplifier applied to a second stage of a variable gain amplifier, which comprises a specific design form of the trans-impedance amplifier and a new scheme for improving linearity. The invention realizes that the trans-impedance amplifier can realize higher linearity, solves the higher requirement on the linearity when transmitting large signals, and further realizes excellent system performance. And the gain changing mode does not affect the stability of the circuit system, and meanwhile, compared with the traditional method, the implementation scheme is simpler and is easy to implement.
Referring to fig. 4, a schematic diagram of a design scheme of a transimpedance stage amplifier of the present invention includes a differential amplifier AMP and two feedback resistors RF1 and RF2, the feedback resistors are connected in parallel to an input terminal and an output terminal of the amplifier AMP, and a MOS transistor is connected across the two input terminals, and a resistance value of the MOS resistor is controlled by changing a voltage value of a gate terminal of the MOS transistor, so as to change a transimpedance value of a second stage TIA of a circuit. The advantage of this structure is that its trans-resistance RT＝RF1,2//A1·R，
A1Is the feed forward amplifier gain. With the continuous increase of the input current, the input resistance of the TIA can be continuously reduced, and the voltage input is basically kept unchanged, so the linearity of the transimpedance amplifier provided by the invention is better than that of the conventional transimpedance amplifier. Meanwhile, because the loop gain and the frequency of the dominant pole are adjusted by the same multiple, the phase margin of the second-stage TIA of the variable gain amplifier is not reduced, and the stability is not changed.
Referring to fig. 5, a schematic diagram of a design scheme of a transimpedance amplifier circuit is shown, in which the gain is changed by controlling the magnitude of the parallel resistor through a VGA _ Ctrl control signal. And the two inductances at output points L5, L6 are for increasing the bandwidth by series peaking.
Referring to fig. 6, it is a schematic diagram of a variable gain amplifier applied to a 28nm CMOS process according to the present invention, in which a first stage transconductance amplifier realizes gain variation by controlling a feedback resistance value; the second stage is to control the gate voltage VGA _ Ctrl, changing the gain of the second stage circuit. The design performance of the simulated circuit is as follows: in the high gain mode, the VGA provides 18.5dB gain and 29GHz bandwidth, and in the low gain mode, the VGA provides 3.8dB gain and 48GHz bandwidth, and the variable gain range is 14.7 dB.
In addition, the design method of the variable gain amplifier with high gain and high bandwidth comprises the following steps:
s1, designing a variable gain amplifier, wherein the requirement of gain bandwidth needs to be met;
the Cherry-Hooper amplifier is adopted, so that high gain is kept, and high bandwidth is guaranteed. In the first-stage transconductance amplifier, as shown in fig. 2, the introduction of the resistor Rp1(Rp2) generates an inductance effect at high frequency, thereby effectively expanding the bandwidth. The output terminals are connected with the inductors L5 and L6 in series to improve the bandwidth through series peaking.
S2, designing a variable gain amplifier, wherein the linearity of the circuit needs to be ensured;
as shown in FIG. 2, the transconductance stage is controlled by controlling the degeneration resistors Rs and R of the source stages1To achieve variable gain. Conventional gain control is usually achieved by changing the magnitude of the tail current source, but this reduces the linearity of the circuit when a large signal is input. As shown in fig. 4, the second stage TIA changes the gain by controlling the magnitude of the parallel resistor via the VGA Ctrl control signal without changing the feedback resistor. The advantage of this structure is that RT＝RF1,2//A1·R，
A1The input resistance of the operational amplifier is continuously reduced along with the continuous increase of the input AC current for feed forward amplifier gain, so that the actual voltage input of the operational amplifier is basically kept unchanged, and the linearity of the transimpedance stage amplifier provided by the invention is better than that of the traditional transimpedance stage amplifier.
S3, designing a variable gain amplifier, and ensuring the stability of the system when the gain is changed;
because the second stage of the circuit adopts a TIA structure, as shown in FIG. 4, the TIA operational amplifier is connected across a MOS resistor, and the equivalent transimpedance is RT＝RF1,2//A1R, loop gain of
Has a dominant pole of
A1For feed forward amplifier gain, CinT1Is the total input capacitance, CinT1＝Cin3,4+CD3,4. Therefore, the gain-bandwidth product is not changed along with the change of the gain, and the closed loop system TIA is kept stable.
Table 1 compares the performance of the TIA of the second stage application of the present invention with that of the TIA of conventional construction, which is excellent in ensuring high gain and high bandwidth requirements. The designed variable gain amplifier based on the CMOS process has an excellent design scheme, and the requirement on high linearity in the PAM-4 signal transmission process is well guaranteed. The designed variable gain amplifier based on the CMOS process has the advantages that the stability of a system is guaranteed well, and the complexity of a circuit and the complexity of operation are reduced.
The above-mentioned contents are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modification made on the basis of the technical idea of the present invention falls within the protection scope of the claims of the present invention.
TABLE 1 comparison of two TIA gain variation modes
Claims (4)
1. A high-gain high-bandwidth variable gain amplifier is characterized by comprising a transconductance amplifier and a transimpedance amplifier which are arranged in two stages; wherein the content of the first and second substances,
the input end of the first-stage transconductance amplifier receives an input signal, amplifies the input voltage signal and converts the amplified voltage signal into a current signal;
and the input end of the second-stage trans-impedance amplifier is connected with the output end of the first-stage trans-impedance amplifier and is used for further amplifying the signal and converting the current signal into a voltage signal.
2. The high-gain high-bandwidth variable gain amplifier according to claim 1, wherein the transconductance amplifier adopts two pairs of differential input tubes, both adopting a source-level negative feedback structure;
the input tube of the first differential pair is composed of two P-type MOS tubes M5 and M6, the load is composed of two N-type MOS tubes M1 and M2, and the negative feedback resistors are all variable resistors Rs；
In the second pair of differential pairs, the input tube is composed of two P-type MOS tubes M7 and M8, the load is composed of two N-type MOS tubes M3 and M4, and the negative feedback resistors are all variable resistors Rs1；
The first pair of differential pairs are connected as follows:
the gate end of M5 is connected with the gate ends of input ends VINN and M7, the source end of M5 is connected with a current source I1 and a resistor Rs, and the drain end of M5 is connected with the drains of output ends VOUTP and M1;
the gate end of M6 is connected with the gate ends of input ends VINPP and M8, the source end of M6 is connected with a current source I2 and a resistor Rs, and the drain end of M6 is connected with the drain ends of output ends VOUTN and M2;
the grid end of the M1 is connected with the drain ends of the resistors Rp1 and M7 and the drain end of the M3, the source end of the M1 is connected with the ground, and the drain end of the M1 is connected with the drain ends of the output ends VOUTP and M5;
the grid end of the M2 is connected with the drain ends of the resistors Rp2 and M8 and the drain end of the M4, the source end of the M2 is connected with the ground, and the drain end of the M2 is connected with the drain ends of the output ends VOUTN and M6;
one end of the resistor Rs is connected with the source ends of the current sources I1 and M5, and the other end of the resistor Rs is connected with the source ends of the current sources I2 and M6;
the connection mode of the second pair of differential pairs is as follows:
the gate end of M7 is connected with the gate ends of input ends VINN and M5, the source end of M7 is connected with a current source I3 and a resistor Rs1, and the drain end of M7 is connected with the gate end of M1 and the drain ends of resistors Rp1 and M3;
the gate end of M8 is connected with the gate ends of input ends VINP and M6, the source end of M8 is connected with a current source I4 and a resistor Rs1, and the drain end of M8 is connected with the gate end of M2 and the drain ends of resistors Rp2 and M4;
the gate end of the M3 is connected with the resistor Rp1, the source end of the M3 is grounded, and the drain end of the M3 is connected with the gate ends of the resistors Rp1 and M1 and the drain end of the M7;
the gate end of the M4 is connected with the resistor Rp2, the source end of the M4 is grounded, and the drain end of the M4 is connected with the gate ends of the resistors Rp2 and M2 and the drain end of the M8;
one end of a resistor Rp1 is connected with the gate end of M1, the drain end of M7 and the drain end of M3, and the other end of the resistor Rp1 is connected with the gate end of M3;
one end of a resistor Rp2 is connected with the gate end of M2, the drain end of M8 and the drain end of M4, and the other end of the resistor Rp2 is connected with the gate end of M4;
resistance Rs1One end of the resistor R is connected with the source ends of the current sources I3 and M7s1The other end is connected with the source ends of the current source I4 and M8.
3. The high-gain high-bandwidth variable gain amplifier according to claim 2, wherein the transimpedance amplifier is formed by a feed-forward path and a feedback path, the feed-forward path is in the structure of an inverter, the performance is changed by a variable resistor, and the performance is compensated by an inductor; the feedback circuit adopts a resistance feedback mode;
the feed-forward path consists of two P-type MOS tubes M9 and M10, three N-type MOS tubes M11, M12 and M13, a current source Itail and two inductors L5 and L6;
the feedback circuit consists of a resistor RF1 and a resistor RF 2;
the connection mode of the feedforward circuit is as follows:
the gate end of M9 is connected with the gate ends of resistors RF1 and M11 and the drain ends of input ends VINN and M13, the source end of M9 is connected with the source ends of current sources Itail and M10, and the drain end of M9 is connected with the drain ends of resistors RF1, inductors L5 and M11;
the gate end of M10 is connected with the gate ends of resistors RF2 and M12 and the gate ends of input ends VINP and M13, the source end of M10 is connected with the source ends of current sources Itail and M9, and the drain end of M10 is connected with the drain ends of resistors RF2, inductors L6 and M12;
the gate end of M11 is connected with the drain ends of input ends VINN and M13 and the gate ends of resistors RF1 and M9, the source end of M11 is connected with the ground, and the drain end of M11 is connected with the drain ends of a resistor RF1, an inductor L5 and an inductor M9;
the gate end of M12 is connected with the source ends of input ends VINP and M13 and the gate ends of resistors RF2 and M10, the source end of M12 is connected with the ground, and the drain end of M12 is connected with the drain ends of a resistor RF2, an inductor L6 and an inductor M10;
the gate end of M13 is connected with input end VGA _ Ctrl, the source end of M13 is connected with input end VINP, the gate end of M10, the gate end of M12 and resistor RF2, the drain end of M13 is connected with input end VINN, the gate end of M9, the gate end of M11 and resistor RF 1;
one end of an inductor L5 is connected with the drain terminals of the resistors RF1 and M9 and the drain terminal of the resistor M11, and the other end of the inductor L5 is connected with an output terminal VOUTP;
one end of an inductor L6 is connected with the drain terminals of the resistors RF2 and M10 and the drain terminal of the resistor M12, and the other end of the inductor L6 is connected with an output terminal VOUTN;
the feedback circuit is connected in the following way:
one end of the resistor RF1 is connected with the input end VINN, the gate end of the M9, the gate end of the M11 and the drain end of the M13, and the other end of the resistor RF1 is connected with the drain ends of the inductors L5 and M9 and the drain end of the M11;
one end of the resistor RF2 is connected with the input end VINP, the gate end of the M10, the gate end of the M12 and the source end of the M13, and the other end of the resistor RF2 is connected with the drain ends of the inductors L6 and M10 and the drain end of the M12.
4. A high-gain high-bandwidth variable gain amplifier chip, characterized in that a high-gain high-bandwidth variable gain amplifier of any one of claims 1 to 3 is used.
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| CN114389629A (en) * | 2022-02-24 | 2022-04-22 | 成都信息工程大学 | Front-end circuit of CMOS radio frequency receiver |
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| CN118264513A (en) * | 2024-05-27 | 2024-06-28 | 成都电科星拓科技有限公司 | Chip with data mode conversion module |
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