CN111522588B - Chip operation interaction method and communication system based on SWD protocol - Google Patents
Chip operation interaction method and communication system based on SWD protocol Download PDFInfo
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- CN111522588B CN111522588B CN202010301374.2A CN202010301374A CN111522588B CN 111522588 B CN111522588 B CN 111522588B CN 202010301374 A CN202010301374 A CN 202010301374A CN 111522588 B CN111522588 B CN 111522588B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4403—Processor initialisation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
- H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
- H04L1/1607—Details of the supervisory signal
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses a chip operation interaction method and a communication system based on SWD protocol, which are characterized in that an address A, an address B, an address C and corresponding storage space are preset in a CORTEX chip, and a specific command interaction mode is adopted, so that the normal operation interaction of an upper computer and the CORTEX chip is ensured, the CORTEX chip can receive data simultaneously in the process of processing own transaction, no extra expenditure is generated due to the received data, the integrity of data transmission can be ensured, and the operation interaction process of the upper computer and the chip is simplified.
Description
Technical Field
The invention relates to the technical field of operation control of electronic circuits, in particular to a chip operation interaction method and a communication system based on an SWD protocol.
Background
Products of ARM company after the classic processor ARM11 are named after Cortex, and are divided into A, R and M types, and the products are used for providing services for various markets. ARM Cortex TM The a-series application-type processor may provide an all-round solution to devices hosting rich OS platforms and user applications, from ultra-low cost cell phones, smart phones, mobile computing platforms, digital televisions and set-top boxes to enterprise networks, printers and server solutions. ARM Cortex-R series application type processor capable of providing high-performance meter for embedded system requiring reliability, high availability, fault tolerance function, maintainability and real-time response by real-time processorA solution is calculated. ARM Cortex TM The M-series application-type processor is an upwardly compatible, energy-efficient, easy-to-use series of processors intended to help developers meet the needs of future embedded applications. These needs include providing more functionality at lower cost, increasing connections, improving code reuse, and improving energy efficiency.
Although the Cortex series chip has strong processing capability, if the core X chip receives data again in the process of processing own transaction, additional expenditure is generated, and normal interaction between the upper computer and the core X chip can be obviously affected.
Disclosure of Invention
The invention aims to provide a chip operation interaction method based on an SWD protocol, and the mechanism can realize that a CORTEX series chip can simultaneously receive data in the process of processing own transactions, does not generate any extra overhead due to the received data, can ensure the integrity of data transmission and simplifies the operation interaction process of an upper computer and the chip. The invention is realized by the following technical scheme:
the chip operation interaction mechanism based on the SWD protocol is characterized in that:
the steps executed by the upper computer end comprise:
(1) Initializing a SWD bus;
(2) Taking out a command to be sent to the core chip;
(3) Sending commands over the SWD bus, comprising:
(3-1) transmitting the writing length and the command data content to a preset address A in the CORTEX chip;
(3-2) sending a command code to a preset address B in the CORTEX chip;
(4) Reading ACK response content stored in a preset address C in the CORTEX chip after the CORTEX chip finishes processing the command;
(5) Repeating the steps (2) to (4) until all commands of the upper computer are sent;
the CORTEX chip end execution steps comprise:
(1) initializing a CORTEX chip;
(2) reading a command code in a preset address B;
(3) reading the length in the preset address A and reading corresponding length data;
(4) forming a complete command according to the data read in the steps (2) and (3), and executing the corresponding command;
(5) after the command is executed, clearing a command code in a preset address B so as to receive the next command;
(6) writing ACK response content into a preset address C;
(7) and (5) repeatedly executing the steps (2) - (6).
In the step (4), if the ACK response content in the preset address C in the core chip cannot be read, the reading is repeated until the ACK response content is read.
As a specific technical scheme, in the step (2), if the command code cannot be read in the preset address B in the core chip, repeating the reading until the command code is read.
The invention also provides a communication system, which comprises an upper computer and a CORTEX chip, and is characterized in that: and the upper computer and the CORTEX chip cooperatively execute the chip operation interaction method based on the SWD protocol.
The invention has the beneficial effects that: by presetting the address A, the address B, the address C and the corresponding storage space in the CORTEX chip and adopting a specific command interaction mode, the normal operation interaction of the upper computer and the CORTEX chip is ensured, the CORTEX chip can receive data simultaneously in the process of processing own transactions, no extra overhead is generated due to the received data, the integrity of data transmission can be ensured, and the operation interaction process of the upper computer and the chip is simplified.
Drawings
Fig. 1 is a flowchart of a chip operation interaction mechanism based on SWD protocol according to an embodiment of the present invention.
Detailed Description
According to the communication system provided by the embodiment, the upper computer and the CORTEX chip are communicated through the SWD protocol, and because the SWD protocol can realize asynchronous data transmission, a specific command interaction mode is required to be adopted to ensure that the upper computer and the CORTEX chip are normally interacted in operation.
Referring to fig. 1, in the SWD protocol-based chip operation interaction method provided in this embodiment, an address a, an address B, an address C, and a corresponding storage space are preset in advance in a core chip. The following description is given from the upper computer end and the core chip end, respectively, as follows:
the steps executed by the upper computer end comprise:
(1) Initializing a SWD bus;
(2) Taking out a command to be sent to the core chip;
(3) Sending commands over the SWD bus, comprising:
(3-1) transmitting the writing length and the command data content to a preset address A in the CORTEX chip;
(3-2) sending a command code to a preset address B in the CORTEX chip;
(4) Reading ACK (Acknowledgement character) response content stored in a preset address C in the CORTEX chip after the command processing of the CORTEX chip is finished; if the ACK response content stored in the preset address C in the CORTEX chip cannot be read, repeatedly reading;
(5) Repeating the steps (2) to (4) until all commands of the upper computer are sent;
the CORTEX chip end execution steps comprise:
(1) initializing a CORTEX chip;
(2) reading the content in the preset address B, if the command code is read, executing the step (3), otherwise, executing the step (2);
(3) reading the length in the preset address A and reading corresponding length data;
(4) forming a complete command according to the data read in the steps (2) and (3), and executing the corresponding command;
(5) after the command is executed, clearing a command code in a preset address B so as to receive the next command;
(6) writing ACK response content into a preset address C;
(7) and (5) repeatedly executing the steps (2) - (6).
The above embodiments are merely for fully disclosing the present invention, but not limiting the present invention, and substitution of equivalent technical features based on the gist of the present invention, which can be achieved without inventive labor, should be considered as the scope of the present disclosure.
Claims (4)
1. A chip operation interaction method based on SWD protocol is characterized in that:
the steps executed by the upper computer end comprise:
(1) Initializing a SWD bus;
(2) Taking out a command to be sent to the core chip;
(3) Sending commands over the SWD bus, comprising:
(3-1) transmitting the writing length and the command data content to a preset address A in the CORTEX chip;
(3-2) sending a command code to a preset address B in the CORTEX chip;
(4) Reading ACK response content stored in a preset address C in the CORTEX chip after the CORTEX chip finishes processing the command;
(5) Repeating the steps (2) to (4) until all commands of the upper computer are sent;
the CORTEX chip end execution steps comprise:
(1) initializing a CORTEX chip;
(2) reading a command code in a preset address B;
(3) reading the length in the preset address A and reading corresponding length data;
(4) forming a complete command according to the data read in the steps (2) and (3), and executing the corresponding command;
(5) after the command is executed, clearing a command code in a preset address B so as to receive the next command;
(6) writing ACK response content into a preset address C;
(7) and (5) repeatedly executing the steps (2) - (6).
2. The SWD protocol based chip operation interaction method according to claim 1, wherein in the step (4), if the ACK response content in the preset address C in the core chip cannot be read, the reading is repeated until the ACK response content is read.
3. The SWD protocol based chip operation interaction method according to claim 1, wherein in the step (2), if the command code cannot be read in the preset address B in the core chip, the reading is repeated until the command code is read.
4. The utility model provides a communication system, includes host computer and CORTEX chip, its characterized in that: the upper computer and the core chip cooperate to execute the chip operation interaction method based on the SWD protocol according to any one of claims 1 to 3.
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