CN111522424B - Method and device for enabling NVDIMM (noise, voltage and noise memory Module) to be compatible with super capacitor - Google Patents
Method and device for enabling NVDIMM (noise, voltage and noise memory Module) to be compatible with super capacitor Download PDFInfo
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- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
- G06F1/305—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations in the event of power-supply fluctuations
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/34—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering
- H02J7/345—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering using capacitors as storage or buffering devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J9/00—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting
- H02J9/04—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source
- H02J9/06—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems
- H02J9/068—Electronic means for switching from one power supply to another power supply, e.g. to avoid parallel connection
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Abstract
The invention discloses a method for enabling an NVDIMM (non-volatile memory Module) to be compatible with a super capacitor, wherein the NVDIMM provides a uniform physical interface and an electrical interface for connecting the super capacitor, and further, if a target super capacitor needs to be normally powered on, a super capacitor query instruction can be sent to the target super capacitor according to a preset communication protocol, wherein data transmission of the physical interface and the electrical interface is defined according to the preset communication protocol. In this way, the target super capacitor may also feed back the capacitor parameter corresponding to the super capacitor query instruction based on the preset communication protocol. Furthermore, the target super capacitor can be controlled in a corresponding mode through the capacitor parameter, so that the target super capacitor can normally supply power to the NVDIMM. Therefore, the NVDIMM can be compatible with different types of super capacitors, namely the super capacitors of different types can normally supply power to the NVDIMM, and the NVDIMM does not need to select types according to the types of the super capacitors, so that the configuration is more flexible.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a method and a device for enabling an NVDIMM to be compatible with a super capacitor and a computer storage medium.
Background
A non-volatile dual in-line Memory (NVDIMM) is a nonvolatile Memory, and when a motherboard is abnormally powered down, data in a Random Access Memory (RAM) is stored in a NAND Flash Memory of a computer by supplying power through a standby power supply, so as to achieve the purpose of preventing data loss. The backup power supply for NVDIMMs is typically a super capacitor. With the popularization of NVDIMMs, in order to meet the requirements of different use scenarios of customers and the internal space of a server, various forms of super capacitors must be provided. Due to the fact that different forms of super capacitors are different in capacitance media, charging voltage, current and capacity, the control strategy of the NVDIMM on the super capacitors is different. Currently, the mainstream approach is to match different super capacitors through different NVDIMMs, which results in insufficient flexibility of configuration.
Disclosure of Invention
In view of the above, the present invention has been developed to provide a method, apparatus, and computer storage medium for NVDIMM-compatible supercapacitors that overcome or at least partially address the above-mentioned problems.
In a first aspect, the present embodiment provides a method for enabling an NVDIMM to be compatible with a super capacitor, where the NVDIMM provides a uniform physical interface and an electrical interface for connecting the super capacitor, and includes:
sending a super capacitor query instruction to a target super capacitor according to a preset communication protocol, wherein data transmission between an NVDIMM and the super capacitor is defined according to the preset communication protocol, and the super capacitor query instruction carries address information of the target super capacitor;
receiving a capacitance parameter corresponding to the super-capacitor query instruction fed back by the target super-capacitor based on the preset communication protocol;
and controlling the target super capacitor based on the capacitance parameter.
Optionally, the preset communication protocol includes a read protocol for NVDIMM to read parameters of the super capacitor, and the sending the super capacitor query instruction to the target super capacitor according to the preset communication protocol includes:
writing the capacitance parameter to be queried into the target super capacitor according to the reading protocol, and sending a reading signal to the target super capacitor after the target super capacitor is confirmed, so that the target super capacitor feeds back the capacitance parameter corresponding to the capacitance parameter to be queried to the NVDIMM after receiving the reading signal.
Optionally, the capacitance parameter to be queried at least includes: the type of the super capacitor, a power supply switch of the super capacitor, the working state of the super capacitor, an input voltage threshold, a charging voltage, the electric quantity of the super capacitor, a low voltage alarm threshold, an electric quantity measuring period, an output voltage threshold, reporting enabling of abnormal interruption of the capacitor, clearing of abnormal interruption of the capacitor, and the temperature of the super capacitor or a combination thereof.
Optionally, the read protocol is sequentially provided with a field carrying address information of the target super capacitor, a field carrying the capacitor query instruction, and a field carrying the capacitor parameter corresponding to the super capacitor query instruction and fed back by the target super capacitor according to a processing sequence.
Optionally, the preset communication protocol includes a write protocol for writing NVDIMM into configuration parameters of a super capacitor, and the controlling the target super capacitor based on the capacitor parameters includes:
writing parameters to be written into the target super capacitor according to the writing protocol based on the capacitor parameters, and writing data corresponding to the parameters to be written into the target super capacitor after the target super capacitor is confirmed so that the target super capacitor operates according to the data corresponding to the parameters to be written into.
Optionally, the parameter to be written at least includes: the system comprises a super capacitor power supply switch, an input voltage threshold, a charging voltage, a low voltage alarm threshold, an electric quantity measurement period, an output voltage threshold, a reporting enabling of abnormal capacitor interruption and a clearing of abnormal capacitor interruption, or any one or combination of the super capacitor power supply switch, the input voltage threshold, the charging voltage, the low voltage alarm threshold and the electric quantity measurement period.
Optionally, the write protocol is sequentially provided with a field carrying address information of the target super capacitor, a field carrying the parameter to be written, and a field carrying data corresponding to the parameter to be written according to a processing sequence.
Optionally, the controlling the target super capacitor based on the capacitance parameter includes:
determining a management strategy corresponding to the target super capacitor based on the capacitor parameter, wherein the management strategy comprises any one or more combinations of a power health detection strategy, a charge and discharge management strategy and a power update strategy;
and controlling the target super capacitor according to the management strategy.
Optionally, a system management bus is used between the NVDIMM and the target super capacitor to perform data transmission, and a data field of the data transmission is 4 bytes long.
In a second aspect, the present embodiment provides a device for an NVDIMM compatible with a super capacitor, where the NVDIMM provides a unified physical interface and an electrical interface for connecting the super capacitor, and includes:
the device comprises a sending unit, a receiving unit and a sending unit, wherein the sending unit is used for sending a super capacitor query instruction to a target super capacitor according to a preset communication protocol, data transmission between the NVDIMM and the super capacitor is defined according to the preset communication protocol, and the super capacitor query instruction carries address information of the target super capacitor;
the receiving unit is used for receiving a capacitance parameter which is fed back by the target super capacitor based on the preset communication protocol and corresponds to the super capacitor query instruction;
and the control unit is used for controlling the target super capacitor based on the capacitance parameter.
Optionally, the preset communication protocol includes a read protocol for reading a parameter of the super capacitor by the NVDIMM, and the sending unit is specifically configured to:
writing the capacitance parameter to be queried into the target super capacitor according to the reading protocol, and sending a reading signal to the target super capacitor after the target super capacitor is confirmed, so that the target super capacitor feeds back the capacitance parameter corresponding to the capacitance parameter to be queried to the NVDIMM after receiving the reading signal.
Optionally, the capacitance parameter to be queried at least includes: the type of the super capacitor, a power supply switch of the super capacitor, the working state of the super capacitor, an input voltage threshold, a charging voltage, the electric quantity of the super capacitor, a low voltage alarm threshold, an electric quantity measuring period, an output voltage threshold, reporting enabling of abnormal interruption of the capacitor, clearing of abnormal interruption of the capacitor, and the temperature of the super capacitor or a combination thereof.
Optionally, the read protocol is sequentially provided with a field carrying address information of the target super capacitor, a field carrying the capacitor query instruction, and a field carrying the capacitor parameter corresponding to the super capacitor query instruction and fed back by the target super capacitor according to a processing sequence.
Optionally, the preset communication protocol includes a write protocol for writing configuration parameters of the super capacitor into the NVDIMM, and the control unit is specifically configured to:
writing parameters to be written into the target super capacitor according to the writing protocol based on the capacitor parameters, and writing data corresponding to the parameters to be written into the target super capacitor after the target super capacitor is confirmed so that the target super capacitor operates according to the data corresponding to the parameters to be written into.
Optionally, the parameter to be written at least includes: the system comprises a super capacitor power supply switch, an input voltage threshold, a charging voltage, a low voltage alarm threshold, an electric quantity measurement period, an output voltage threshold, a reporting enabling of abnormal capacitor interruption and a clearing of abnormal capacitor interruption, or any one or combination of the super capacitor power supply switch, the input voltage threshold, the charging voltage, the low voltage alarm threshold and the electric quantity measurement period.
Optionally, the write protocol is sequentially provided with a field carrying address information of the target super capacitor, a field carrying the parameter to be written, and a field carrying data corresponding to the parameter to be written according to a processing sequence.
Optionally, the control unit is specifically configured to:
determining a management strategy corresponding to the target super capacitor based on the capacitor parameter, wherein the management strategy comprises any one or more combinations of a power health detection strategy, a charge and discharge management strategy and a power update strategy;
and controlling the target super capacitor according to the management strategy.
Optionally, a system management bus is used between the NVDIMM and the target super capacitor to perform data transmission, and a data field of the data transmission is 4 bytes long.
In a third aspect, the present embodiment provides an NVDIMM-compatible super capacitor apparatus, including at least one processor, and at least one memory and a bus connected to the processor; the processor and the memory complete mutual communication through a bus; the processor is configured to invoke program instructions in the memory to perform the method of any of the foregoing first aspects of NVDIMM-compatible supercapacitors.
In a fourth aspect, the present application provides a computer storage medium having a program stored thereon, where the program when executed by a processor implements the method for NVDIMM-compatible supercapacitors according to any of the previous first aspects.
One or more technical solutions in the embodiments of the present application have at least one or more of the following technical effects:
in the technical scheme of the embodiment of the invention, the NVDIMM provides a uniform physical interface and an electrical interface for connecting the super capacitor, and further, if the target super capacitor needs to be normally powered, a super capacitor query instruction can be sent to the target super capacitor according to a preset communication protocol, wherein data transmission between the NVDIMM and the super capacitor is defined according to the preset communication protocol, and the super capacitor query instruction carries address information of the target super capacitor. In this way, the target super capacitor may also feed back the capacitor parameter corresponding to the super capacitor query instruction based on the preset communication protocol. Furthermore, the target super capacitor can be controlled in a corresponding mode through the capacitor parameter, so that the target super capacitor can normally supply power to the NVDIMM. Therefore, the NVDIMM can be compatible with different types of super capacitors, namely the super capacitors of different types can normally supply power to the NVDIMM, and the NVDIMM does not need to select types according to the types of the super capacitors, so that the configuration is more flexible.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
fig. 1 is a flowchart of a method for NVDIMM to be super capacitor compliant in a first embodiment of the present invention;
fig. 2 is a schematic interface signal diagram of the connection between the NVDIMM and the super capacitor in the first embodiment of the present invention;
FIG. 3 is a schematic diagram of a read protocol between the NVDIMM and the super capacitor according to a first embodiment of the present invention;
FIG. 4 is a diagram illustrating the corresponding labels of different capacitance parameters in a first embodiment of the present invention;
FIG. 5 is a schematic diagram of a write protocol between the NVDIMM and the super capacitor according to a first embodiment of the present invention;
FIG. 6 is a schematic view of a prosthetic device according to a second embodiment of the invention;
fig. 7 is a schematic diagram of an NVDIMM-compatible super capacitor apparatus according to a third embodiment of the present invention.
Detailed Description
The embodiment discloses a method and a device for enabling an NVDIMM to be compatible with a super capacitor and a computer storage medium. The method for the compatibility of the NVDIMM with the super capacitor is applied to the NVDIMM, the NVDIMM provides a unified physical interface and an electrical interface which are used for connecting the super capacitor, and the method comprises the following steps: sending a super capacitor query instruction to a target super capacitor according to a preset communication protocol, wherein data transmission between the NVDIMM and the super capacitor is defined according to the preset communication protocol, and the super capacitor query instruction carries address information of the target super capacitor; receiving a capacitance parameter corresponding to the super-capacitor query instruction fed back by the target super-capacitor based on the preset communication protocol; based on the capacitance parameter, controlling the target super capacitor so that the target super capacitor normally powers the NVDIMM.
The technical solutions of the present invention are described in detail below with reference to the drawings and specific embodiments, and it should be understood that the specific features in the embodiments and examples of the present invention are described in detail in the technical solutions of the present application, and are not limited to the technical solutions of the present application, and the technical features in the embodiments and examples of the present application may be combined with each other without conflict.
The term "and/or" herein is merely an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
Examples
A first embodiment of the present invention provides a method for enabling an NVDIMM to be compatible with a super capacitor, where the NVDIMM provides a uniform physical interface and an electrical interface for connecting the super capacitor, and a flowchart of the method is shown in fig. 1, and includes the following steps:
s101: sending a super capacitor query instruction to a target super capacitor according to a preset communication protocol, wherein data transmission between an NVDIMM and the super capacitor is defined according to the preset communication protocol, and the super capacitor query instruction carries address information of the target super capacitor;
s102: receiving a capacitance parameter corresponding to the super-capacitor query instruction fed back by the target super-capacitor based on the preset communication protocol;
s103: and controlling the target super capacitor based on the capacitance parameter.
Specifically, the method for enabling the NVDIMM to be compatible with the super capacitor in the embodiment is applied to the NVDIMM which serves as a master device, the NVDIMM mounts the target super capacitor through a system management bus SMBus, and the SMBus is based on an I2C bus and is a specific application of the I2C bus in the field of servers. The SMBus bus provides a control bus for the NVDIMM and the super capacitor, and the NVDIMM using the SMBus bus can send and receive messages among devices through the SMBus bus instead of using a separate control line, so that the pin count of the devices can be saved. Using the SMBus bus, a device may also provide its production information, tell the system its model, part number, etc., save its status for a pending event, report different classes of errors, receive control parameters, and return its status, etc. In this way, NVDIMM is enabled to recognize the target super-capacitor through system management bus SMBus.
The signal diagram of the interface of the connection between the NVDIMM and the super capacitor is shown in fig. 2, and the NVDIMM and the different super capacitors have the same physical and electrical interface. Wherein I2C _ SCL and I2C _ SDA are signals specified by the SMBus protocol for data transfer between the NVDIMM and the super capacitor. PRESENT is a POWER supply on/off signal, POWER _ FAIL _ INT is a POWER failure interrupt signal, GND is ground, and VCC is 12V POWER.
Further, a preset communication protocol for data transmission is defined between the NVDIMM and the super capacitor, and the preset communication protocol is set according to a bus SMBus and comprises a reading protocol for reading parameters of the super capacitor by the NVDIMM and a writing protocol for writing configuration parameters of the super capacitor by the NVDIMM. The reading protocol is used for reading the capacitance parameters in the super capacitor by the NVDIMM, and the writing protocol is used for writing the configuration parameters of the capacitor into the super capacitor.
Further, step S101 can be implemented by: and sending the capacitance parameter to be queried to the target super capacitor corresponding to the address information according to the address information carried in the reading protocol, and sending a reading signal to the target super capacitor after the target super capacitor is confirmed, so that the target super capacitor feeds back the capacitance parameter corresponding to the capacitance parameter to be queried to the NVDIMM after receiving the reading signal. Wherein, the capacitance parameter to be inquired at least comprises: the type of the super capacitor, a power supply switch of the super capacitor, the working state of the super capacitor, an input voltage threshold, a charging voltage, the electric quantity of the super capacitor, a low voltage alarm threshold, an electric quantity measuring period, an output voltage threshold, reporting enabling of abnormal interruption of the capacitor, clearing of abnormal interruption of the capacitor, and the temperature of the super capacitor or a combination thereof.
And the reading protocol is sequentially provided with a field carrying address information of the target super capacitor, a field carrying the capacitor query instruction and a field carrying the capacitor parameter which is fed back by the target super capacitor and corresponds to the super capacitor query instruction according to a processing sequence.
Specifically, in this embodiment, the set read protocol is as shown in fig. 3, where white blocks are sent out by NVDIMMs, and gray blocks are sent out by target supercapacitors. The upper digit of the diagram is the command length in bits. Specifically, when the NVDIMM reads the super capacitor, the NVDIMM first sends a white 1-bit Start signal, and then sends a 7-bit Address signal, that is, a field of Address information of the target super capacitor, where the Address signal is an Address of the target super capacitor mounted on the bus, and through the Address, data can be accurately sent to the corresponding super capacitor. The NVDIMM sends out a Write signal of 1bit again, and the super capacitor SuperCap needs to return an Ack confirmation signal of 1bit to the NVDIMM after receiving the Write signal. Then the NVDIMM continues to send 8-bit Offset signal, which is the capacitance parameter to be queried that needs to be read, that is: a field of the capacitance query instruction.
Since the super capacitor has many capacitance parameters, different capacitance parameters correspond to different identifiers, and fig. 4 shows the identifiers corresponding to the capacitance parameters, that is, the value of Offset, and when Offset is set to 0x0, it indicates that the NVDIMM needs to read the type of the super capacitor. By analogy, an Offset set to 0x1 indicates that the NVDIMM needs to read the state of the super capacitor power switch. When Offset is set to 0x2, it indicates that the NVDIMM needs to read the super capacitor operating status. With Offset set to 0x3, this indicates the input voltage threshold that the NVDIMM needs to read the super capacitor. With Offset set to 0x4, this indicates that the NVDIMM needs to read the charging voltage of the super capacitor. When Offset is set to 0x5, it indicates that the NVDIMM needs to read the amount of power of the super capacitor. With Offset set to 0x6, it indicates that the NVDIMM needs to read the low voltage alarm threshold of the super capacitor. With Offset set to 0x7, this indicates that the NVDIMM needs to read the charge measurement period of the super capacitor. With Offset set to 0x8, this indicates the output voltage threshold that the NVDIMM needs to read the super capacitor. And when Offset is set to be 0x9, reporting enabling is interrupted due to the capacitor exception indicating that the NVDIMM needs to read the super capacitor. When Offset is set to 0xA, a capacitance abort clear indicating that the NVDIMM needs to read the super capacitor. With Offset set to 0xB, this indicates the capacitance temperature that the NVDIMM needs to read the super capacitor. In a specific implementation process, Offset may also be set as another type of capacitance parameter, and this embodiment is not limited herein.
Furthermore, the Offset signal can be set as an identifier of a parameter that needs to be read by the NVDIMM, and the parameter is written into the super capacitor. Therefore, after the super capacitor SuperCap receives the response, the super capacitor SuperCap knows which corresponding capacitor parameter needs to be fed back, and then returns an Ack confirmation signal.
And then, the NVDIMM continuously sends a 1-bit read Start restart signal, continuously sends a 7-bit Address signal, and then sends a 1-bit read signal, so that the super capacitor can be identified to feed back the capacitor parameter corresponding to the offset signal.
After receiving the read signal, the super capacitor SuperCap feeds back a capacitance parameter of 4 bytes based on the read protocol through step S102, that is: the field of the capacitance parameter corresponding to the super-capacitor query command fed back by the target super-capacitor occupies 4 bytes, specifically, a 1-bit Ack confirmation signal is sent, then 8-bit Data of the 1 st byte is sent, and after the NVDIMM receives the Data, the 1-bit Ack is sent. After receiving the Ack confirmation signal, the super-capacitor SuperCap continues to send 8-bit Data of the 2 nd byte, after receiving the Data, the NVDIMM sends a 1-bit Ack confirmation signal, after receiving the Ack confirmation signal, the super-capacitor SuperCap continues to send 8-bit Data of the 3 rd byte, after receiving the Data, the NVDIMM sends a 1-bit Ack confirmation signal, after receiving the Ack confirmation signal, the super-capacitor SuperCap continues to send 8-bit Data of the 4 th byte, after receiving the Data, the NVDIMM sends a 1-bit Nack response signal and a 1-bit Stop signal, and the reading operation is finished. Thus, one-time operation of reading the capacitance parameter by the NVDIMM is completed
In this embodiment, for convenience of SMBus bus processing, the field length of the transmitted capacitance parameter is set to 4 bytes, and the data field length is fixed to 4 bytes, which is conveniently introduced when the data receiver processes the data. After the length of the data field is fixed, the receiving party can clearly know the amount of data to be received when receiving the data every time, and the receiving control processing is convenient. In a specific implementation process, the setting may be performed according to actual needs, and the embodiment is not limited herein.
Further, after reading a capacitance parameter corresponding to a target super capacitor through the read protocol in steps S101 and S102, step S103 is executed, and based on the capacitance parameter, the target super capacitor is controlled, so that the NVDIMM is normally powered by the target super capacitor. Specifically, the control of the target super capacitor can be divided into the following two aspects:
in a first aspect, the NVDIMM may complete configuration of parameters of the super capacitor through a write protocol with the super capacitor, and specifically may implement the following steps: writing parameters to be written into the target super capacitor according to the writing protocol based on the capacitor parameters, and writing data corresponding to the parameters to be written into the target super capacitor after the target super capacitor is confirmed so that the target super capacitor operates according to the data corresponding to the parameters to be written into. Wherein the parameters to be written at least comprise: the system comprises a super capacitor power supply switch, an input voltage threshold, a charging voltage, a low voltage alarm threshold, an electric quantity measurement period, an output voltage threshold, a reporting enabling of abnormal capacitor interruption and a clearing of abnormal capacitor interruption, or any one or combination of the super capacitor power supply switch, the input voltage threshold, the charging voltage, the low voltage alarm threshold and the electric quantity measurement period.
And the write protocol is sequentially provided with a field carrying address information of the target super capacitor, a field carrying the parameter to be written and a field carrying data corresponding to the parameter to be written according to a processing sequence.
Specifically, in this embodiment, the set write protocol is as shown in fig. 5, and like the read protocol, the white blocks are sent out by the NVDIMM, and the gray blocks are sent out by the target super capacitor. The upper digit of the diagram is the command length in bits. Specifically, when the NVDIMM writes the corresponding parameter into the super capacitor, the NVDIMM first sends a white 1-bit Start signal, and then sends a 7-bit Address signal, that is: and the address signal is the address of the target super capacitor mounted on the bus, and data can be accurately transmitted to the corresponding super capacitor through the address. The NVDIMM sends out a Write signal of 1bit again, and the super capacitor SuperCap needs to return an Ack confirmation signal of 1bit to the NVDIMM after receiving the Write signal. Then the NVDIMM continues to send 8-bit Offset signal, which is the parameter to be written in the super capacitor, that is: fields to be written with parameters.
Since the super capacitor has a plurality of configurable capacitance parameters, different capacitance parameters correspond to different identifiers, and fig. 4 shows the identifiers corresponding to the capacitance parameters, i.e., Offset values, some of the parameters are configurable by the NVDIMM, i.e., the NVDIMM can configure some capacitance parameters in the target super capacitor according to the read capacitance parameters. The configurable parameters comprise a super capacitor power supply switch, an input voltage threshold, a charging voltage, a low voltage alarm threshold, an electric quantity measurement period, an output voltage threshold, a reporting enabling of abnormal capacitor interruption and an abnormal capacitor interruption clearing.
When Offset in the write protocol is set to 0x1, this indicates that the NVDIMM needs to write to the super capacitor power switch. With Offset set to 0x3, this indicates the input voltage threshold that the NVDIMM needs to write to the super capacitor. With Offset set to 0x4, this indicates that the NVDIMM needs to write the charging voltage of the super capacitor. With Offset set to 0x6, this indicates a low voltage alarm threshold that NVDIMM needs to write to the super capacitor. With Offset set to 0x7, this indicates that the NVDIMM needs to write a power measurement cycle of the super capacitor. With Offset set to 0x8, this indicates the output voltage threshold that the NVDIMM needs to write to the super capacitor. And when the Offset is set to 0x9, the reporting of the abnormal capacitor interrupt is enabled, which indicates that the NVDIMM needs to be written into the super capacitor. When Offset is set to 0xA, a capacitance abort clear indicating that the NVDIMM needs to write to the super capacitor.
Furthermore, the Offset signal may be set as an identifier of a parameter that needs to be written by the NVDIMM, and the parameter is written into the super capacitor. Therefore, after receiving the offset signal, the super capacitor SuperCap knows which corresponding capacitor parameter needs to be configured, and then returns an Ack acknowledgement signal.
The NVDIMM may then write the capacitance parameter corresponding to the offset. As with the read protocol described above, the write parameters specified in the write protocol also occupy 4 bytes, i.e., the field of the data corresponding to the parameters to be written occupies 4 bytes. Specifically, the NVDIMM sends 8-bit Data of the 1 st byte first, and the super capacitor SuperCap sends 1-bit ack after receiving the Data. After receiving the Ack confirmation signal, the NVDIMM continues to send 8-bit Data of the 2 nd byte, after receiving the Data, the super capacitor SuperCap sends a 1-bit Ack confirmation signal, after receiving the Ack confirmation signal, the NVDIMM continues to send 8-bit Data of the 3 rd byte, after receiving the Data, the super capacitor SuperCap sends a 1-bit Ack confirmation signal, after receiving the Ack confirmation signal, the NVDIMM continues to send 8-bit Data of the 4 th byte, after receiving the Data, the super capacitor SuperCap sends a 1-bit Ack confirmation signal, after receiving the Ack confirmation signal, the NVDIMM sends a 1-bit Stop signal, and the end of the suction operation is identified. Thus, one writing operation of the NVDIMM to write the capacitance parameter is completed. In this way, the NVDIMM may perform parameter configuration on the target super capacitor, so that the target super capacitor operates according to the configured parameters to normally supply power to the NVDIMM.
In a second aspect, in addition to configuring relevant capacitance parameters of the super capacitor itself, the NVDIMM further needs to formulate relevant policies for managing the super capacitor according to the parameters of the super capacitor, such as the type of the super capacitor, so as to implement control over the target super capacitor, which may specifically be implemented by the following steps:
determining a management strategy corresponding to the target super capacitor based on the capacitor parameter, wherein the management strategy comprises any one or more combinations of a power health detection strategy, a charge and discharge management strategy and a power update strategy; and controlling the target super capacitor according to the management strategy.
Specifically, in this embodiment, corresponding management strategies need to be formulated according to different types of super capacitors, including a power health detection strategy, a charge-discharge management strategy, and a power update strategy. The power health detection strategy comprises a detection mode, a detection period and the like which are matched in a self-adaptive mode according to the target super capacitor. The power supply updating strategy comprises updating content, updating period and the like which are matched according to the target super capacitor in a self-adaptive mode. The charge and discharge management strategy comprises a charge mode and a discharge mode which are matched in a self-adaptive mode according to the target super capacitor. In terms of charging, different supercapacitors provide different voltages and currents for different media, which results in different charging strategies. Such as: the target super capacitor is supplied with voltage of 7.5V and electric quantity of 22W, and because the medium is a lithium battery, the super capacitor is charged by 500mA current under 7V, and is buffered by 50mA trickle current when the voltage exceeds 7.5V.
Thus, by the compatible method in this embodiment, if the NVDIMM needs the target super capacitor to normally supply power to the NVDIMM, the super capacitor query instruction may be sent to the target super capacitor according to the preset communication protocol, and the target super capacitor may also be based on the capacitor parameter corresponding to the super capacitor query instruction fed back by the preset communication protocol. Furthermore, the target super capacitor can be controlled in a corresponding mode through the capacitor parameter, so that the target super capacitor can normally supply power to the NVDIMM. Therefore, the NVDIMM can be compatible with different types of super capacitors, namely the super capacitors of different types can normally supply power to the NVDIMM, and the NVDIMM does not need to select types according to the types of the super capacitors, so that the configuration is more flexible.
Referring to fig. 6, a second embodiment of the present invention provides a device for enabling an NVDIMM to be compatible with a super capacitor, where the NVDIMM provides a unified physical interface and an electrical interface for connecting the super capacitor, and includes:
a sending unit 601, configured to send a super capacitor query instruction to a target super capacitor according to a preset communication protocol, where data transmission between the NVDIMM and the super capacitor is defined according to the preset communication protocol, and the super capacitor query instruction carries address information of the target super capacitor;
a receiving unit 602, configured to receive a capacitance parameter, corresponding to the super capacitor query instruction, fed back by the target super capacitor based on the preset communication protocol;
a control unit 603, configured to control the target super capacitor based on the capacitance parameter.
As an optional embodiment, the preset communication protocol includes a read protocol for NVDIMM to read a parameter of the super capacitor, and the sending unit 601 is specifically configured to:
writing the capacitance parameter to be queried into the target super capacitor according to the reading protocol, and sending a reading signal to the target super capacitor after the target super capacitor is confirmed, so that the target super capacitor feeds back the capacitance parameter corresponding to the capacitance parameter to be queried to the NVDIMM after receiving the reading signal.
As an optional embodiment, the capacitance parameter to be queried at least includes: the type of the super capacitor, a power supply switch of the super capacitor, the working state of the super capacitor, an input voltage threshold, a charging voltage, the electric quantity of the super capacitor, a low voltage alarm threshold, an electric quantity measuring period, an output voltage threshold, reporting enabling of abnormal interruption of the capacitor, clearing of abnormal interruption of the capacitor, and the temperature of the super capacitor or a combination thereof.
As an optional embodiment, the read protocol is sequentially provided with a field carrying address information of the target super capacitor, a field carrying the capacitor query instruction, and a field carrying a capacitor parameter corresponding to the super capacitor query instruction and fed back by the target super capacitor according to a processing sequence.
As an optional embodiment, the preset communication protocol includes a write protocol for writing configuration parameters of a super capacitor to an NVDIMM, and the control unit 603 is specifically configured to:
writing parameters to be written into the target super capacitor according to the writing protocol based on the capacitor parameters, and writing data corresponding to the parameters to be written into the target super capacitor after the target super capacitor is confirmed so that the target super capacitor operates according to the data corresponding to the parameters to be written into.
As an alternative embodiment, the parameters to be written at least include: the system comprises a super capacitor power supply switch, an input voltage threshold, a charging voltage, a low voltage alarm threshold, an electric quantity measurement period, an output voltage threshold, a reporting enabling of abnormal capacitor interruption and a clearing of abnormal capacitor interruption, or any one or combination of the super capacitor power supply switch, the input voltage threshold, the charging voltage, the low voltage alarm threshold and the electric quantity measurement period.
As an optional embodiment, the write protocol is sequentially provided with a field carrying address information of the target super capacitor, a field carrying the parameter to be written, and a field carrying data corresponding to the parameter to be written according to a processing sequence.
As an optional embodiment, the control unit 603 is specifically configured to:
determining a management strategy corresponding to the target super capacitor based on the capacitor parameter, wherein the management strategy comprises any one or more combinations of a power health detection strategy, a charge and discharge management strategy and a power update strategy;
and controlling the target super capacitor according to the management strategy.
As an optional embodiment, a system management bus is used between the NVDIMM and the target super capacitor for data transmission, and a data field of the data transmission is 4 bytes long.
Specifically, in this embodiment, a specific implementation manner of the compatibility method adopted by the NVDIMM-compatible super capacitor apparatus has been described in detail in the foregoing first embodiment, and here, this embodiment is not described again.
Referring to fig. 7, for convenience of description, only the parts related to the embodiment of the present invention are shown, and details of the method in the first embodiment of the present invention are not disclosed.
Fig. 7 is a schematic diagram illustrating a partial structure of a super capacitor compatible NVDIMM apparatus according to an embodiment of the present invention. The NVDIMM-compatible super capacitor apparatus includes a memory 701, and the memory 701 is used for storing a program for executing the compatible method in the foregoing first embodiment. The NVDIMM-compatible super capacitor apparatus further includes a processor 702 coupled to the memory 701, the processor 702 configured to execute the program stored in the memory 701.
The processor 702, when executing the computer program, performs the steps in the method for NVDIMM-compatible supercapacitors in the first embodiment described above. Alternatively, the processor, when executing the computer program, implements the functions of each module/unit in the NVDIMM-compatible supercapacitor device according to the second embodiment.
Illustratively, the computer program may be partitioned into one or more modules/units that are stored in the memory and executed by the processor to implement the invention. The one or more modules/units may be a series of computer program instruction segments capable of performing specific functions, which are used to describe the execution of the computer program in the computer apparatus. For example, the computer program may be divided into functions of a transmitting unit, a receiving unit, and a control unit, and the specific functions of each unit are as follows:
the device comprises a sending unit, a receiving unit and a sending unit, wherein the sending unit is used for sending a super capacitor query instruction to a target super capacitor according to a preset communication protocol, data transmission between the NVDIMM and the super capacitor is defined according to the preset communication protocol, and the super capacitor query instruction carries address information of the target super capacitor;
the receiving unit is used for receiving a capacitance parameter which is fed back by the target super capacitor based on the preset communication protocol and corresponds to the super capacitor query instruction;
and the control unit is used for controlling the target super capacitor based on the capacitance parameter.
The NVDIMM-compatible super capacitor device may include, but is not limited to, a processor, a memory. Those skilled in the art will appreciate that the schematic diagram 7 is merely an exemplary diagram of functional components of an NVDIMM-compatible supercapacitor device, and does not constitute a limitation of the NVDIMM-compatible supercapacitor device, and may include more or less components than those shown, or combine some components, or different components, for example, the NVDIMM-compatible supercapacitor device may further include input-output devices, network access devices, buses, and the like.
The Processor 702 may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, discrete hardware components, etc. The general purpose processor may be a microprocessor or the processor may be any conventional processor or the like which is the control center for the computer device and which connects the various parts of the overall computer device using various interfaces and lines.
The memory 701 may be used for storing the computer programs and/or modules, and the processor may implement various functions of the computer apparatus by operating or executing the computer programs and/or modules stored in the memory and calling data stored in the memory. The memory may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required by at least one function (such as a sound playing function, an image playing function, etc.), and the like; the storage data area may store data (such as audio data, video data, etc.) created from use of the NVDIMM-compliant supercapacitor device, and the like. In addition, the memory may include high speed random access memory, and may also include non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), at least one magnetic disk storage device, a Flash memory device, or other volatile solid state storage device.
In an embodiment of the present invention, the processor 702 has the following functions:
sending a super capacitor query instruction to a target super capacitor according to a preset communication protocol, wherein data transmission between an NVDIMM and the super capacitor is defined according to the preset communication protocol, and the super capacitor query instruction carries address information of the target super capacitor;
receiving a capacitance parameter corresponding to the super-capacitor query instruction fed back by the target super-capacitor based on the preset communication protocol;
and controlling the target super capacitor based on the capacitance parameter.
In this embodiment of the present invention, the processor 702 further has the following functions:
the preset communication protocol comprises a reading protocol for reading parameters of a super capacitor by an NVDIMM, the super capacitor query instruction is sent to a target super capacitor according to the preset communication protocol, the capacitor parameters to be queried are written into the target super capacitor according to the reading protocol, and a reading signal is sent to the target super capacitor after the target super capacitor is confirmed, so that the target super capacitor feeds back the capacitor parameters corresponding to the capacitor parameters to be queried to the NVDIMM after receiving the reading signal.
In this embodiment of the present invention, the capacitance parameter to be queried at least includes: the type of the super capacitor, a power supply switch of the super capacitor, the working state of the super capacitor, an input voltage threshold, a charging voltage, the electric quantity of the super capacitor, a low voltage alarm threshold, an electric quantity measuring period, an output voltage threshold, reporting enabling of abnormal interruption of the capacitor, clearing of abnormal interruption of the capacitor, and the temperature of the super capacitor or a combination thereof.
In the embodiment of the present invention, the read protocol is sequentially provided with a field carrying address information of the target super capacitor, a field carrying the capacitor query instruction, and a field carrying the capacitor parameter corresponding to the super capacitor query instruction and fed back by the target super capacitor according to a processing sequence.
In this embodiment of the present invention, the processor 702 further has the following functions:
the preset communication protocol comprises a write protocol for writing configuration parameters of a super capacitor into an NVDIMM, based on the capacitor parameters, writing parameters to be written into the target super capacitor according to the write protocol, and after the target super capacitor is confirmed, writing data corresponding to the parameters to be written into the target super capacitor so that the target super capacitor operates according to the data corresponding to the parameters to be written into the target super capacitor.
In this embodiment of the present invention, the parameters to be written at least include: the system comprises a super capacitor power supply switch, an input voltage threshold, a charging voltage, a low voltage alarm threshold, an electric quantity measurement period, an output voltage threshold, a reporting enabling of abnormal capacitor interruption and a clearing of abnormal capacitor interruption, or any one or combination of the super capacitor power supply switch, the input voltage threshold, the charging voltage, the low voltage alarm threshold and the electric quantity measurement period.
In the embodiment of the present invention, the write protocol is sequentially provided with a field carrying address information of the target super capacitor, a field carrying the parameter to be written, and a field carrying data corresponding to the parameter to be written according to a processing sequence.
In this embodiment of the present invention, the processor 702 further has the following functions:
determining a management strategy corresponding to the target super capacitor based on the capacitor parameter, wherein the management strategy comprises any one or more combinations of a power health detection strategy, a charge and discharge management strategy and a power update strategy;
and controlling the target super capacitor according to the management strategy.
In the embodiment of the invention, a system management bus is adopted between the NVDIMM and the target super capacitor for data transmission, and the data field of the data transmission is 4 bytes in length.
A fourth embodiment of the present invention provides a computer readable storage medium, on which a computer program is stored, wherein the functional unit integrated with the NVDIMM-compatible super capacitor device in the second embodiment of the present invention can be stored in a computer readable storage medium if it is implemented in the form of a software functional unit and sold or used as a stand-alone product. Based on such understanding, all or part of the flow of the method for implementing NVDIMM-compatible super capacitors according to the first embodiment of the present invention can also be implemented by a computer program instructing related hardware, where the computer program can be stored in a computer readable storage medium, and when the computer program is executed by a processor, the computer program can implement the steps of the above-described method embodiments. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying said computer program code, medium, usb disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution medium, etc. It should be noted that the computer readable medium may contain content that is subject to appropriate increase or decrease as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, computer readable media does not include electrical carrier signals and telecommunications signals as is required by legislation and patent practice.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (18)
1. A method for enabling an NVDIMM to be compatible with a super capacitor is applied to the NVDIMM, and the NVDIMM is characterized in that a unified physical interface and an electrical interface for connecting the super capacitor are provided, and the method comprises the following steps:
sending a super capacitor query instruction to a target super capacitor according to a preset communication protocol, wherein data transmission between an NVDIMM and the super capacitor is defined according to the preset communication protocol, and the super capacitor query instruction carries address information of the target super capacitor;
receiving a capacitance parameter corresponding to the super-capacitor query instruction fed back by the target super-capacitor based on the preset communication protocol;
controlling the target supercapacitor based on the capacitance parameter, including: determining a management strategy corresponding to the target super capacitor based on the capacitor parameter, wherein the management strategy comprises any one or more combinations of a power health detection strategy, a charge and discharge management strategy and a power update strategy; and controlling the target super capacitor according to the management strategy.
2. The method of claim 1, wherein the preset communication protocol comprises a read protocol for NVDIMM to read parameters of the super capacitor, and the sending the super capacitor query command to the target super capacitor according to the preset communication protocol comprises:
writing the capacitance parameter to be queried into the target super capacitor according to the reading protocol, and sending a reading signal to the target super capacitor after the target super capacitor is confirmed, so that the target super capacitor feeds back the capacitance parameter corresponding to the capacitance parameter to be queried to the NVDIMM after receiving the reading signal.
3. The method of claim 2, wherein the capacitance parameters to be queried comprise at least: the type of the super capacitor, a power supply switch of the super capacitor, the working state of the super capacitor, an input voltage threshold, a charging voltage, the electric quantity of the super capacitor, a low voltage alarm threshold, an electric quantity measuring period, an output voltage threshold, reporting enabling of abnormal interruption of the capacitor, clearing of abnormal interruption of the capacitor, and the temperature of the super capacitor or a combination thereof.
4. The method according to claim 2, wherein the read protocol is sequentially provided with a field carrying address information of the target super capacitor, a field carrying the capacitor query instruction, and a field carrying capacitor parameters corresponding to the super capacitor query instruction and fed back by the target super capacitor according to a processing order.
5. The method of claim 1, wherein the preset communication protocol comprises a write protocol for NVDIMM to write configuration parameters for a supercapacitor, and wherein the controlling the target supercapacitor based on the capacitance parameters comprises:
writing parameters to be written into the target super capacitor according to the writing protocol based on the capacitor parameters, and writing data corresponding to the parameters to be written into the target super capacitor after the target super capacitor is confirmed so that the target super capacitor operates according to the data corresponding to the parameters to be written into.
6. The method according to claim 5, wherein the parameters to be written comprise at least: the system comprises a super capacitor power supply switch, an input voltage threshold, a charging voltage, a low voltage alarm threshold, an electric quantity measurement period, an output voltage threshold, a reporting enabling of abnormal capacitor interruption and a clearing of abnormal capacitor interruption, or any one or combination of the super capacitor power supply switch, the input voltage threshold, the charging voltage, the low voltage alarm threshold and the electric quantity measurement period.
7. The method according to claim 5, wherein the write protocol is sequentially provided with a field carrying address information of the target super capacitor, a field carrying the parameter to be written, and a field carrying data corresponding to the parameter to be written in a processing order.
8. The method of any one of claims 1-7, wherein a system management bus is used for data transfer between the NVDIMM and the target supercapacitor, and a data field of the data transfer is 4 bytes long.
9. An NVDIMM (non-volatile memory Module) compatible super capacitor device applied to an NVDIMM, wherein the NVDIMM provides a unified physical interface and an electrical interface for connecting a super capacitor, and comprises:
the device comprises a sending unit, a receiving unit and a sending unit, wherein the sending unit is used for sending a super capacitor query instruction to a target super capacitor according to a preset communication protocol, data transmission between the NVDIMM and the super capacitor is defined according to the preset communication protocol, and the super capacitor query instruction carries address information of the target super capacitor;
the receiving unit is used for receiving a capacitance parameter which is fed back by the target super capacitor based on the preset communication protocol and corresponds to the super capacitor query instruction;
the control unit is used for controlling the target super capacitor based on the capacitance parameter and comprises: determining a management strategy corresponding to the target super capacitor based on the capacitor parameter, wherein the management strategy comprises any one or more combinations of a power health detection strategy, a charge and discharge management strategy and a power update strategy; and controlling the target super capacitor according to the management strategy.
10. The apparatus of claim 9, wherein the preset communication protocol comprises a read protocol for NVDIMM to read parameters of the super capacitor, and the sending unit is specifically configured to:
writing the capacitance parameter to be queried into the target super capacitor according to the reading protocol, and sending a reading signal to the target super capacitor after the target super capacitor is confirmed, so that the target super capacitor feeds back the capacitance parameter corresponding to the capacitance parameter to be queried to the NVDIMM after receiving the reading signal.
11. The apparatus of claim 10, wherein the capacitance parameters to be queried comprise at least: the type of the super capacitor, a power supply switch of the super capacitor, the working state of the super capacitor, an input voltage threshold, a charging voltage, the electric quantity of the super capacitor, a low voltage alarm threshold, an electric quantity measuring period, an output voltage threshold, reporting enabling of abnormal interruption of the capacitor, clearing of abnormal interruption of the capacitor, and the temperature of the super capacitor or a combination thereof.
12. The apparatus according to claim 10, wherein the read protocol is sequentially provided with a field carrying address information of the target super capacitor, a field carrying the capacitor query instruction, and a field carrying a capacitor parameter corresponding to the super capacitor query instruction and fed back by the target super capacitor in a processing order.
13. The apparatus of claim 9, wherein the preset communication protocol comprises a write protocol for NVDIMM to write configuration parameters of the super capacitor, and the control unit is specifically configured to:
writing parameters to be written into the target super capacitor according to the writing protocol based on the capacitor parameters, and writing data corresponding to the parameters to be written into the target super capacitor after the target super capacitor is confirmed so that the target super capacitor operates according to the data corresponding to the parameters to be written into.
14. The apparatus of claim 13, wherein the parameters to be written comprise at least: the system comprises a super capacitor power supply switch, an input voltage threshold, a charging voltage, a low voltage alarm threshold, an electric quantity measurement period, an output voltage threshold, a reporting enabling of abnormal capacitor interruption and a clearing of abnormal capacitor interruption, or any one or combination of the super capacitor power supply switch, the input voltage threshold, the charging voltage, the low voltage alarm threshold and the electric quantity measurement period.
15. The apparatus according to claim 13, wherein the write protocol is sequentially provided with, in order of processing, a field carrying address information of the target super capacitor, a field carrying the parameter to be written, and a field carrying data corresponding to the parameter to be written.
16. The apparatus of any of claims 9-15, wherein a system management bus is used for data transfer between the NVDIMM and the target supercapacitor, and a data field of the data transfer is 4 bytes long.
17. An NVDIMM (non-volatile memory Module) -compatible super capacitor device is characterized by comprising at least one processor, at least one memory and a bus, wherein the at least one memory and the bus are connected with the processor; the processor and the memory complete mutual communication through a bus; a processor is configured to call program instructions in memory to perform the method of NVDIMM-compatible supercapacitors of any one of the claims 1 to 8.
18. A computer storage medium having stored thereon a program that, when executed by a processor, performs the method of any of claims 1-8 for NVDIMM-compatible supercapacitors.
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