CN111512294A

CN111512294A - Storage device and electronic equipment

Info

Publication number: CN111512294A
Application number: CN201880083554.9A
Authority: CN
Inventors: 肖勇军; 孔飞; 耿剑锋; 何彪; 夏邓伟; 张广宇
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2018-09-18
Filing date: 2018-09-18
Publication date: 2020-08-07
Also published as: WO2020056610A1

Abstract

A storage device and an electronic apparatus for performing efficient data migration between storage media of different memories. The device includes: a package (201), a first memory (202), a second memory (203), a third memory (204), and a controller (205); the controller (205), coupled to the first memory (202), the second memory (203), and the third memory (204), to migrate data between at least two of the first memory (202), the second memory (203), and the third memory (204); the first memory (202), the second memory (203) and the third memory (204) are different types of memory; the package (201) is for packaging the first memory (202), the second memory (203), the third memory (204) and the controller (205).

Description

Storage device and electronic equipment

Technical Field

The present application relates to the field of information storage technologies, and in particular, to a storage device and an electronic apparatus.

Background

The data storage medium may generally include both Random Access Memory (RAM) and Read-Only Memory (ROM) types. The RAM has the characteristics of high access speed but power-down Data loss (volatility), such as Double Data Rate (DDR) Synchronous Dynamic RAM (DDR SDRAM for short); ROM has the characteristics that power-down data is not lost (non-volatile), but access speed is slow, such as NAND flash memory. At present, a Non-Volatile Random Access Memory (NVRAM) is also available, which combines the priority of RAM and RAM, and has the characteristics of fast Access speed and no loss of power-down data, such as Resistive RAM (ReRAM), Ferroelectric RAM (FRAM), Magnetic RAM (MRAM), etc.

In practical applications, considering the characteristics, size and price of storage media of different memories, it is often necessary to deploy a hybrid memory in an electronic device, such as a mobile terminal, that is, different types of data storage media are deployed in a hybrid memory. For example, a hybrid memory including DDR SDRAM, NAND, and NVRAM at the same time, etc. is deployed in the mobile terminal. When deploying a hybrid memory in a mobile terminal, there may be a need for data migration between different storage media of the hybrid memory. How to perform efficient data migration on different storage media becomes a problem.

Disclosure of Invention

Embodiments of the present application provide a storage device and an electronic apparatus for efficient data migration between different memories packaged in the storage device.

In order to achieve the above purpose, the embodiment of the present application adopts the following technical solutions:

in a first aspect, there is provided a storage apparatus, the apparatus comprising: a package, a first memory, a second memory, a third memory; the controller, coupled to the first memory, the second memory and the third memory, for migrating data between at least two of the first memory, the second memory and the third memory; the first memory, the second memory and the third memory are different types of memory; the package is used for packaging the first memory, the second memory, the third memory and the controller. In the technical scheme, the controller can migrate data among at least two memories of the first memory, the second memory and the third memory which are packaged in the same package, the data do not need to be transferred to the outside of the storage device when the data are migrated, the efficiency is improved, and the storage device is small in size and low in cost.

In a possible implementation manner of the first aspect, the first Memory is a Non-Volatile Random Access Memory (NVRAM), and the second Memory is a NAND flash Memory. Further, the third Memory is a Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM), which is abbreviated as DDR SDRAM. The storage device using the technical scheme is a hybrid memory, and different types of memories are fused.

In a possible implementation manner of the first aspect, the apparatus further includes: a bus and a processor, the controller, the first memory, the second memory, and the third memory coupled to the bus, the package further for packaging the bus and the processor; the controller is also used for acquiring bus control authority from the processor and migrating data between the at least two memories by using the bus; and the processor is used for granting the bus control authority to the controller. In the above possible implementation, the controller can perform efficient data migration between different storage media by using the bus.

In a possible implementation manner of the first aspect, the controller is further configured to receive an operation request for migrating data from at least one of the at least two memories before migrating the data between the at least two memories. In the above possible implementation, the controller is capable of performing efficient data migration between different storage media based on an operation request of the at least one memory.

In a possible implementation manner of the first aspect, the controller is further configured to send a response to the at least one memory granting the operation request. In the above possible implementation, the controller is capable of notifying the at least one memory after acquiring the bus control authority.

In a possible implementation manner of the first aspect, the processor is further configured to release the bus control authority of the controller after the controller completes the migration data. In the possible implementation manner, by releasing the bus control authority of the controller in time, the problem that the controller controls the bus for a long time and affects the relevant operations of the processor can be avoided.

In a possible implementation manner of the first aspect, the apparatus further includes: an interface coupled to the controller for coupling the first memory, the second memory and the third memory to a processing device located outside the enclosure of the storage apparatus. In the above possible implementation, a coupling manner of the storage apparatus and the processing device is provided.

In one possible implementation form of the first aspect, the interface includes at least two interfaces. In the above possible implementation, a coupling manner of the storage apparatus and the processing device is provided.

In a possible implementation manner of the first aspect, any one of the at least two interfaces is: peripheral component interconnect standard PCIe interface, double data rate synchronous dynamic random access memory DDR SDRAM interface or universal flash memory UFS interface. In the above possible implementations, several possible at least two interfaces are provided.

In one possible implementation form of the first aspect, the package comprises a chip package. For example, the memory device includes one or more chip grains (Die) such that the first memory, the second memory, the third memory, the controller, the bus, and the processor are located on the one or more chip grains. The package encapsulates one or more chip particles to form the memory device, enabling miniaturization of the memory device.

In a second aspect, an electronic device is provided, which includes a storage apparatus and a processing device, where the storage apparatus may be the storage apparatus provided in the first aspect or any one of the possible implementation manners of the first aspect. Optionally, the processing device is a System on Chip (SoC).

In the above technical solution, the controller in the storage device can migrate data between at least two memories among the first memory, the second memory, and the third memory packaged in the same package, thereby implementing efficient data migration between storage media of different memories. Meanwhile, the participation of external processing equipment is not needed in the whole data migration process, so that the power consumption of the electronic equipment during data migration is reduced, and the performance of the electronic equipment is improved.

Drawings

Fig. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure;

fig. 2 is a first schematic structural diagram of a memory device according to an embodiment of the present disclosure;

fig. 3 is a schematic flow chart of migrating data according to an embodiment of the present application;

fig. 4 is a second schematic structural diagram of a memory device according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of a memory device according to an embodiment of the present application;

fig. 6 is a fourth schematic structural diagram of a memory device according to an embodiment of the present application.

Detailed Description

In the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone, wherein A and B can be singular or plural. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a-b, a-c, b-c or a-b-c, wherein a, b and c can be single or multiple. In addition, in the embodiments of the present application, the words "first", "second", and the like do not limit the number and the execution order.

It is noted that, in the present application, words such as "exemplary" or "for example" are used to mean exemplary, illustrative, or descriptive. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion. "coupled" in this application may be understood as a direct connection or an indirect connection, e.g., a coupled to B, which may mean: a and B are directly connected or A and B are indirectly connected.

Fig. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure, where the electronic device may be a mobile phone, a tablet computer, a video camera, a wearable device, an in-vehicle device, or a portable device. For convenience of description, the above-mentioned devices are collectively referred to as electronic devices in this application. The embodiment of the present application is described by taking the electronic device as a mobile phone as an example, and referring to fig. 1, the mobile phone includes a System on Chip (SoC) 101 and a hybrid memory 102 coupled to the SoC 101.

The SoC101 is a control center of the mobile phone, connects various parts of the whole device by using various interfaces and lines, and executes various functions and processes data of the mobile phone by running or executing software programs and/or software modules stored in the hybrid memory and calling data stored in the hybrid memory, thereby integrally monitoring the mobile phone. In some possible embodiments, SoC101 may include a central processor unit, other various general purpose processors such as a digital signal processor, an artificial intelligence processor, a microcontroller or microprocessor, or the like. The SoC101 may further include a Graphics Processing Unit (GPU), an Image Signal Processor (ISP), or a voice Processor, among others. SoC101 may further include other hardware circuits or accelerators, such as application specific integrated circuits, field programmable gate arrays or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

In the embodiment of the present application, different types of memories may be included in the hybrid memory 102, and the SoC101 may be used to access any type of memory or storage medium in the hybrid memory 102. In fig. 1, the hybrid memory 102 includes a Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) (DDR SDRAM for short), an NVRAM, and a NAND flash memory, and the DDR SDRAM, the NVRAM, and the NAND flash memory are integrated together as an example.

The hybrid memory 102 of FIG. 1 incorporates different types of memory, such as DDR SDRAM, NVRAM, and NAND flash memory, and may further include other types of memory. Reference may be made in particular to the following description of embodiments. At least one memory in hybrid memory 102 or storage medium therein may be used to store data, software programs, and modules. For example, any of the memories may include a stored program area and a stored data area, wherein the stored program area may store a software program including instructions formed in code, including but not limited to an operating system, an application program required for at least one function, such as a sound playing function, an image playing function, etc.; the storage data area may store data created according to the use of the cellular phone, such as audio data, image data, a phonebook, and the like.

Further, referring to fig. 1, the mobile phone may further include a sensor component 103, a multimedia component 104, an input/output interface 105, and the like, which are described in detail below.

Wherein the sensor component 103 includes one or more sensors for providing various aspects of state assessment for the handset. For example, the sensor assembly 103 may include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications, i.e., as an integral part of a camera or a video camera. In addition, the sensor assembly 103 may further include an acceleration sensor, a gyro sensor, a magnetic sensor, a pressure sensor or a temperature sensor, and acceleration/deceleration, orientation, on/off state of the cellular phone, relative positioning of the components, or temperature change of the cellular phone, etc. may be detected by the sensor assembly 103.

The multimedia component 104 provides a screen, which may be a display panel or a touch panel, as an output interface between the cellular phone and the user, and when the screen is a touch panel, the screen may be implemented as a touch screen to receive an input signal from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundary of a touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In addition, the multimedia component 104 may further include at least one camera, for example, the multimedia component 104 may include a front camera and/or a rear camera. When the handset is in an operational mode, such as a capture mode or a video mode, the front-facing camera and/or the rear-facing camera may sense external multimedia signals that are used to form image frames. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

The input/output interface 105 provides an interface between the SoC101 and a peripheral interface module, for example, the peripheral interface module may include a keyboard, a mouse, or a USB (universal serial bus) device. In one possible implementation, the input/output interface 105 may have only one input/output interface or a plurality of input/output interfaces.

Although not shown, the mobile phone may further include an audio component, a communication component, and the like, for example, the audio component includes a microphone, and the communication component includes a Wireless Fidelity (WiFi) module, a bluetooth module, and the like, which is not described herein again. Those skilled in the art will appreciate that the handset configuration shown in fig. 1 is not intended to be limiting and may include more or fewer components than those shown, or some components may be combined, or a different arrangement of components. It is understood that all components shown in fig. 1 may be located on the same circuit board, and this embodiment is not limited thereto.

To specifically illustrate the hybrid memory 102 in fig. 1, fig. 2 is a schematic structural diagram of a storage device according to an embodiment of the present application, where the storage device corresponds to the hybrid memory 102 and includes: a package 201, a first memory 202, a second memory 203, a third memory 204, a controller 205, a processor 206, and a bus 207. Wherein a first memory 202, a second memory 203, a third memory 204, a controller 205, and a processor 206 are coupled to a bus 207. It should be noted that, the embodiment corresponding to fig. 2 is described by way of example only, but not by way of limitation, in the storage device including three memories, and actually, a greater number of memories may be included in the storage device, and types of the memories are usually different to form a hybrid memory.

In the present embodiment, the controller 205 is configured to migrate data between at least two of the first memory 202, the second memory 203, and the third memory 204. For convenience of description, the following only takes as an example that the at least two memories include the first memory 202 and the second memory 203, and the migration data between the first memory 202 and the second memory 203 includes at least one of the following: migrating data from the first memory 202 to the second memory 203, or migrating data from the second memory 203 to the first memory 202. The package 201 is used to package a first memory 202, a second memory 203, a third memory 204, a controller 205, a processor 206, and a bus 207. Due to the existence of the package 201, the storage device is small in size, low in cost and capable of achieving better performance. When the data migration is executed, the data does not need to be transferred to the outside of the storage device, namely the data migration is completed in the package, and the efficiency is high. For example, the controller 205 is a Direct Memory Access (DMA) device.

The package 201 mentioned in this embodiment may be a chip package for packaging one or more chip particles. For example, the memory device includes the one or more chip particles (Die) such that the first memory 202, the second memory 203, the third memory 204, the controller 205, the processor 206, and the bus 207 are located on the one or more chip particles. The package 201 encapsulates the one or more chip particles to form the memory device, enabling miniaturization of the memory device. The specific technology adopted for chip packaging can be selected from the existing packaging technologies, which is not limited in this embodiment. Because the storage device exists as a whole, the internal data migration does not depend on the outside, and the efficiency is high. The package 201 encloses the first memory 202, the second memory 203, the third memory 204, the controller 205, the processor 206 and the bus 207, which is preferably dustproof, waterproof, or antistatic, so that the storage device is a stand-alone device on a circuit board.

Wherein the first memory 202, the second memory 203 and the third memory 204 are different types of memories. In one possible implementation, the first Memory 202 is a Non-Volatile Random Access Memory (NVRAM), the second Memory 203 is a NAND flash Memory, and the third Memory 204 is a double data rate synchronous dynamic Random Access Memory (DDR SDRAM). Any one of the first memory 202, the second memory 203 and the third memory 204 may include a storage medium, and may further include necessary circuits, such as a control circuit for reading and writing the storage medium, for example, an addressing circuit, which is not limited in this embodiment. Different types of memory, which have different types of storage media, may also have different types of control circuitry.

In addition, here, taking the example that the controller 204 migrates data from the first memory 202 to the second memory 203 as an example, the controller 204 is used for migrating data between at least two memories among the first memory 202, the second memory 203, and the third memory 204. Specifically, the specific process of the controller 205 migrating data from the first storage 202 to the second storage 203 may include: 1. the first memory 202 sends an operation request to the controller 205, the operation request requesting that data in the first memory 202 be migrated to the second memory 203; 2. when the controller 205 receives the operation request, the controller 205 may acquire the bus control authority from the processor 206, for example, the controller 205 sends a bus control request for requesting to acquire the bus control authority to the processor 206; 3. the processor 206 grants the bus control authority to the controller 205, for example, the processor 206 sends a response to the controller 205 to grant the bus control request; 4. after the controller 205 acquires the bus control authority, the controller 205 may send a response to the first memory 202 granting the operation request; 5. the controller 205 uses the bus 207 to migrate the data in the first memory to the second memory, for example, the controller 205 enables a read channel of the first memory 202 to read the data from the first memory using the bus, and after the data read is completed, the first memory 202 may send a data read end response to the controller 205. Further, the controller 205 enables a write channel of the second memory 203 to write the read data into the second memory using the bus, and after the data write is completed, the second memory 203 may transmit a data write end response to the controller 205. Further, after the controller 205 completes the above migration of data, the processor 206 may also release the bus control authority of the controller 205.

For example, assuming that the first memory 202 is an NVRAM and the second memory 203 is a NAND flash memory, the flow chart of the controller 204 migrating data from the NVRAM to the NAND flash memory may be as shown in fig. 3. In fig. 3, SC _ REQ indicates an operation request, SC _ RESP indicates a response granting the operation request, BH _ REQ indicates a bus control request, BH _ RESP indicates a response granting the bus control request, R _ EN indicates enabling a read channel, W _ EN indicates enabling a write channel, and each memory has corresponding R _ EN and W _ EN. 5a indicates an operation of enabling the read channel R _ EN of the first memory 202 in the above-described step 5, and 5b indicates an operation of enabling the write channel W _ EN of the second memory 203 in the above-described step 5. Fig. 3 illustrates an example in which the bus 207 includes the data bus and the address bus shown in fig. 3, and one of the NVRAM and the NAND flash memory R _ EN and W _ EN, respectively.

It should be noted that the specific process of the controller 205 migrating data from the second storage 203 to the first storage 202 is similar to the specific process of the controller 205 migrating data from the first storage 202 to the second storage 203, and specific reference may be made to the above description. In addition, a specific process of the controller 204 migrating data between at least two of the first memory 202, the second memory 203 and the third memory 204 is also similar to the above-mentioned specific process of migrating data between the first memory 202 and the second memory 203, and specifically, reference may be made to the above description, and details of the embodiment of the present application are not repeated herein. It is understood that at least two memories may be simultaneously transmitted in two directions or transmitted only in one direction, and the embodiment is not limited thereto.

In practical applications, as an alternative embodiment, the first storage 202 and the second storage 203 may use the same type of storage medium, and the controller 205 may also migrate data between two storage media of the same type in the above manner. Generally speaking, the first memory 202 and the second memory 203 use different types of storage media, which is a more common option. When the first memory 202 and the second memory 203 use the same type of storage medium, the two memories are the same memory, and thus, a storage device including the two memories belongs to a non-hybrid memory, but can still achieve similar functions. When data is migrated between the two memories, it is still not necessary to transfer the data to the outside of the storage device, and efficiency can be improved.

Further, the apparatus further comprises: an interface 208 coupled to the controller 205 for coupling the first memory 202, the second memory 203 and the second memory 204 to a processing device located outside the enclosure 201 of the storage apparatus. Among other things, the interface 208 may include: at least two interfaces. Optionally, any of the at least two interfaces is: a Peripheral Component Interconnect express (PCIe) interface, a double data rate synchronous dynamic random access memory DDR SDRAM interface, or a Universal Flash Storage (UFS) interface.

In one possible implementation, referring to fig. 4, interface 208 includes a UFS interface for coupling both first memory 202 and third memory 204 to a processing device located outside package 201 of the storage apparatus, and a DDR SDRAM interface for coupling second memory 203 to a processing device located outside package 201 of the storage apparatus, for example, the processing device may be SoC101 shown in fig. 1 or a circuit board including SoC101, or the like. That is, the controller 205 may transfer data of the first memory 202 or data of the third memory 204 with the processing device through the DDR SDRAM interface, and transfer data of the second memory 203 with the processing device through the UFS interface, and the data may include read data and written data. In another possible implementation, referring to fig. 5, the interface 208 includes a PCIe interface, a UFS interface, and a DDR SDRAM interface; wherein the PCIe interface is configured to couple the first memory 202 to a processing device outside the package 201, that is, the controller 205 may transmit data of the first memory 202 with the processing device through the PCIe interface; the UFS interface is used to couple the second memory 203 to a processing device outside the package 201, i.e., the controller 205 may transfer data of the second memory 203 with the processing device through the UFS interface; the DDR SDRAM interface is used to couple the third memory 204 to a processing device outside the package 201, i.e., the controller 205 may transfer data of the third memory 204 with the processing device through the DDR SDRAM interface.

It should be noted that, only the interface 208 including a PCIe interface, a UFS interface, and/or a DDR SDRAM interface is taken as an example for description, in practical applications, the interface 208 may further include an Embedded multimedia controller (eMMC) interface, and the like, which may be used to couple an eMMC memory located in the hybrid memory to the processing device, and this is not specifically limited in this embodiment of the application. The types of interfaces mentioned in this embodiment are also extensible and are not necessarily limited to the types listed in this embodiment.

In the storage apparatus provided in the embodiment of the present application, the controller 205 is capable of migrating data between at least two of the first storage 202, the second storage 203, and the third storage 204 packaged in the same package, thereby achieving efficient data migration between different storage media. For example, the controller 205 is a DMA device for implementing the data migration in place of the DMA device in the SoC 101. The DMA device built in the storage device makes the data not necessary to be transferred to the outside of the storage device when the data is migrated, thereby improving the efficiency. Meanwhile, when the storage device is applied to the electronic equipment comprising the processing equipment, the whole data migration process does not need the participation of the processing equipment, so that the power consumption of the electronic equipment during data migration is reduced, and the performance of the electronic equipment is improved.

In another embodiment of the present application, there is also provided a storage apparatus, as shown in fig. 6, including: package 301, first memory 302, second memory 303, third memory 304, first controller 305 coupled to first memory 302, second controller 306 coupled to second memory 303, third controller 307 coupled to third memory 304, processor 308, and bus 309. Wherein a first memory 302, a second memory 303, a third memory 304, a first controller 305, a second controller 306, a third controller 307, and a processor 308 are coupled to a bus 309.

In the present embodiment, the package 301 is used to package a first memory 302, a second memory 303, a third memory 304, a first controller 305, a second controller 306, a third controller 307, a processor 308, and a bus 309. Wherein the first memory 302, the second memory 303 and the third memory 304 may be different types of memories; in one possible implementation, the first memory 302 may be NVRAM, the second memory 303 may be NAND flash memory, and the third memory 304 is DDR SDRAM, but is not limited thereto, e.g., the storage device may include more other types of memory.

Further, the storage device further includes: a first interface 310 coupled to the first controller 305 for coupling the first memory 302 to a processing device located outside the enclosure 301 of the storage apparatus; and a second interface 311 coupled to the second controller 306 for coupling the second memory 303 to a processing device located outside the enclosure 301 of the storage apparatus; and a third interface 312 coupled to the third controller 307 for coupling the third memory 304 to a processing device located outside the enclosure 301 of the storage apparatus. The first interface 310 may include a PCIe interface, that is, the first controller 305 may transmit data of the first memory 302 with the processing device through the PCIe interface; the second interface 311 may comprise a UFS interface, i.e. the second controller 306 may transfer data of the second memory 303 with the processing device via the UFS interface; the third interface 312 may comprise a DDR SDRAM interface, i.e. the third controller 307 may transfer data of the third memory 304 with the processing device via the DDR SDRAM interface. It should be noted that, only the PCIe interface, the UFS interface, and/or the DDR SDRAM interface are taken as examples for description, in practical applications, the first interface, the second interface, and the third interface may further include other interfaces, and the like, which is not specifically limited in this embodiment of the application.

Embodiments of the present application further provide an electronic device, which may include the storage device and the processing device as described in the foregoing embodiments, where the storage device may be as described in fig. 2, fig. 4, fig. 5, or fig. 6. Wherein, the processing device may be a system on chip SoC 101. Specifically, a schematic structural diagram of the electronic device may be as shown in fig. 1.

The storage device of the embodiment is used as a hybrid memory, comprises different types of built-in memories or storage media, and internally realizes data transfer between the different memories. For example, the different memories may include NVRAM, NAND flash memory, and DDR SDRAM. The NVRAM is generally small in storage capacity, while the NAND flash memory is larger in capacity, and the NVRAM can serve as a data cache of the NAND flash memory to achieve good performance. In the hybrid memory structure of the embodiment, for example, in the memory device shown in fig. 2, the first memory 202, the second memory 203, the third memory 204, the controller 205, the processor 206 and the bus 207 may be located in one chip particle to form a whole. Alternatively, these components may be located in different multiple chip particles, but packaged in a single package, still achieving the advantages of device miniaturization. For example, the first memory 202, the second memory 203, and the third memory 204 may be located on different chip particles because they are different types of memories. In addition, the controller 205, processor 206 and bus 207 may be located on another separate chip particle to implement the control functions. The controller 205 may be a DMA device that is built into the enclosure of the storage device and becomes part of the storage device for the data migration. Data migration need not be through an external device, e.g., DMA device participation in SoC 101.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

A storage device, the device comprising: a package, a first memory, a second memory, a third memory, and a controller;

the controller, coupled to the first memory, the second memory, and the third memory, to migrate data between at least two of the first memory, the second memory, and the third memory;

the first memory, the second memory, and the third memory are different types of memory;

the package is to package the first memory, the second memory, the third memory, and the controller.
The storage device of claim 1, wherein the first memory is a non-volatile random access memory (NVRAM) and the second memory is a NAND flash memory.
The memory device of claim 2, wherein the third memory is a double data rate synchronous dynamic random access memory (DDR SDRAM).
A storage device according to any one of claims 1-3, wherein the device further comprises: a bus and a processor, the controller, the first memory, the second memory, and the third memory coupled to the bus, the package further for packaging the bus and the processor;

the controller is further configured to acquire a bus control authority from the processor, and migrate data between the at least two memories by using the bus;

and the processor is used for granting the bus control authority to the controller.
The storage device of claim 4, wherein the controller is further configured to receive an operation request for migrating data from at least one of the at least two memories before migrating the data between the at least two memories.
The storage device of claim 5, wherein the controller is further configured to send a response to the at least one memory granting the operation request.
The storage device according to any one of claims 4 to 6, wherein the processor is further configured to release the bus control authority of the controller after the controller completes the migration data.
The storage device of any one of claims 1-7, wherein the device further comprises: an interface coupled to the controller to couple the first memory, the second memory, and the third memory to a processing device located outside of the enclosure.
The storage device of claim 8, wherein the interface comprises at least two interfaces.
The storage device of claim 9, wherein any of the at least two interfaces is: peripheral component interconnect standard PCIe interface, double data rate synchronous dynamic random access memory DDR SDRAM interface or universal flash memory UFS interface.
An electronic device, characterized in that it comprises a storage means according to any one of claims 8-10, and said processing device.
The electronic device of claim 11, wherein the processing device is a system on a chip (SoC).