CN111510284B - Real-time bit synchronization correction method for quantum key generation system - Google Patents
Real-time bit synchronization correction method for quantum key generation system Download PDFInfo
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Abstract
The method utilizes a plurality of local delay values to measure and obtain the optimal delay value of a detector, thereby realizing the real-time bit synchronization correction. Reading a real-time counting value and a real-time delay value of a detector, and acquiring a delay efficiency relation, a maximum counting value in unit time and a corresponding optimal delay value; judging whether to start a real-time bit synchronization process; calculating the synchronous delay search range of each detector and the delay value to be searched; fourthly, the delay control unit adjusts the delay value of each detector; counting by a detector; sixthly, the bit synchronization processing unit judges whether the search of the bit synchronization delay search range is finished or not, and returns to the fourth step if the search is not finished; and the position synchronization processing unit obtains the optimal delay values detected by the detectors according to the counting and sends the optimal delay values to the delay control unit, and the delay control unit controls the delay setting of the detectors according to the optimal delay values to realize real-time position synchronization correction.
Description
Technical Field
The application relates to the field of quantum communication, in particular to a real-time bit synchronization correction method for a quantum key generation system.
Background
Since the twenty-first century, with the overall popularization of the internet, the global informatization level is continuously improved, the attention of governments, national defense, enterprises and individuals to information security is increasingly enhanced, and the demand for information security is increasing day by day. Meanwhile, the information security faces more and more serious threats, and particularly in the Shor algorithm based on the quantum computer proposed in 1994, the basis of the classical cryptography protocol based on the computational complexity is subversively destroyed.
In recent years, Quantum Key Distribution (QKD) technology has attracted much attention because its unconditional security is guaranteed by the fundamental principles of Quantum mechanics. Many international research institutes have conducted intensive research on theory and application, and some companies have also successively introduced commercial quantum key distribution products.
In a quantum key distribution system, a transmitting end encodes a quantum signal (photon) and then transmits the encoded quantum signal to a receiving end through a quantum channel. Commonly used quantum channels include optical fibers and free space (i.e., the atmosphere). The receiving end needs to confirm the arrival time of the photon in order to use the detector to detect at the right moment, which is the bit synchronization process. After the bit synchronization process is completed, the quantum key distribution system can perform a subsequent negotiation process to generate a security key.
The inventor finds in the course of research of the present application that the optimum instant for detection by the detector varies over time. This is because the transmission time of photons in the quantum channel is usually affected by the environment, and especially when the ambient temperature changes, the length and refractive index of the quantum channel also change. When the photon transmission time changes, the optimal time for the detector to detect changes. The detection at the 'optimal detection moment' before the change can reduce the effective detection efficiency of the detector, the detection count is reduced, and the generation rate of the safe password of the quantum key distribution system is also obviously reduced or even can not normally operate.
The quantum channel based on optical fiber is taken as an example and explained as follows: with the change of the environmental temperature, the length and the refractive index of the optical fiber are changed, and the change amount Δ t of the transmission time of the photon is calculated as follows:
in the formula, neffIs a refractive index, LeffFor the fiber length, Δ Temp is the temperature change, α is the linear expansion coefficient, and ξ is the refractive index temperature coefficient.
For fused silica fiber, the coefficient of linear expansion α is 5.5 × 10-7V. deg. C, temperature coefficient of refractive index xi ═ neff×0.68× 10-5/° c, then calculated according to the above equation: photon per kilometer of fiber at temperature change per degree centigradeThe variation in transmission time is about 30 ps. Then the variation of photon transmission time can reach 30000ps at most for a quantum key distribution system with the quantum channel length of 100km running in the beijing area. (according to the forecast result of the weather of the China weather bureau 2018, 10 months and 18 days: cloudy, 13-23 ℃ and 3-4 grades of east wind.)
In order to ensure stable operation of the quantum key generation system, the optimal time for the detector to detect needs to be adjusted according to changes of the external environment during the working process of the quantum key generation system, which is called a bit synchronization correction process. A common bit synchronization correction scheme is an interrupted bit synchronization correction scheme. Besides, the influence of the external environment on the quantum key generation system can be reduced through a wavelength optimization scheme.
The existing solution of interrupt-type bit synchronization correction is that when the count of a detector is obviously reduced (for example, the current count of the detector is less than 50% of the maximum count of the detector), the overall signal-to-noise ratio of the system is obviously reduced, the bit error rate is obviously improved, at this time, the quantum key generation system cannot normally work, the key generation process of the quantum key generation system needs to be stopped, the bit synchronization process is started, and the key generation process of the quantum key generation system is restarted after the bit synchronization process is completed.
Another modification scheme for optimizing the wavelength of the synchronous light is to implement synchronization between quantum key generation systems by using a synchronous light mode, and to reduce the influence of the environment on the photon transmission time, the wavelength difference between the synchronous light wavelength and the quantum signal light wavelength is selected to be as small as possible.
However, during the research process of the present application, the inventors found that the interrupted feedback scheme is inefficient, and will reduce the effective operation time of the quantum key generation system. Particularly, with the acceleration of the change of the external environment temperature and the increase of the length of the quantum channel, the change rate of the photon transmission time is increased, the starting frequency of the interrupted feedback scheme is increased, and the stable operation of the quantum key generation system is seriously influenced.
The solution of optimizing the wavelength of the synchronous light is only to reduce the influence of environmental changes on the optimal detection time of the detector, but when the environmental changes are further aggravated or the length of the quantum channel is further increased, the problem that the optimal time for the detector to detect changes with the influence of the environmental temperature still exists. Meanwhile, the scheme is limited by the existing wavelength division multiplexing technology, when the wavelength difference between the synchronous light and the quantum signal light is small, the influence of the synchronous light on the quantum signal light is not negligible, and the introduced noise reduces the performance of the quantum key generation system.
Disclosure of Invention
The application provides a real-time bit synchronization method for a quantum key generation system, which aims to solve the problem that in the prior art, the detection count of a receiving end of the quantum key generation system is reduced due to the change of an external environment, so that the generation rate of a security key is reduced. The method obtains the monitoring detection count in real time, and when the detection count is reduced due to the change of the photon transmission time, the method starts a real-time bit synchronization process to obtain the optimal detection delay value without interrupting the safety key generation process of the quantum key generation system.
The method sets a proper detector counting minimum threshold relative to the maximum counting of the detector, and judges whether the counting of the detector exceeds the threshold in real time according to the minimum threshold so as to judge whether the optimal delay value detected by the detector changes.
The lowest count threshold, which is typically set, is closer to the maximum count, and the change in the value of the detector's optimal delay value is relatively small when the event occurs that the current detector count value exceeds the set lowest threshold, meaning that a search can be made within a relatively small range around the current delay value to find the optimal detection instant (i.e., without having to search through the entire pulse range). Within a small range near the current delay value, the count value of the detector is not obviously reduced, and although the working performance of the quantum key generation system is slightly reduced, the security key can be normally generated without interrupting the key generation process.
The work flow of the whole method is shown in figure 1, and the method comprises the following steps:
firstly, a bit synchronization processing unit continuously reads a real-time counting value of a detector and a real-time delay value of the corresponding detector, and obtains a delay efficiency relation of the detector, a maximum counting value in unit time and an optimal delay value corresponding to the maximum counting value, wherein the delay efficiency relation of the detector is the relation between the counting value and the delay value of the detector;
secondly, according to the parameters obtained in the first step, the bit synchronization processing unit judges whether a real-time bit synchronization process is started or not, if the judgment result is that the real-time bit synchronization process is started, the step returns to the first step, and if the judgment result is that the real-time bit synchronization process is started, the next step is executed;
thirdly, a bit synchronization processing unit calculates a bit synchronization delay search range of each detector and a delay value to be searched, wherein the bit synchronization delay search range of each detector is a preset peak time interval, and the delay value to be searched is obtained according to the preset peak time interval and a preset delay step;
fourthly, the delay control unit adjusts the delay value of each detector to be one of the delay values obtained in the third step;
fifthly, counting and accumulating by the detector according to the delay value adjusted in the fourth step;
sixthly, judging whether the search of the bit synchronization delay search range is finished or not by the bit synchronization processing unit, and if the detector finishes scanning all the delay values obtained in the third step, determining the delay value corresponding to the maximum unit time count value as the optimal delay value; or the detector scans continuous n delay values in all the delay values obtained in the third step, and the delay values corresponding to the maximum unit time count value in the unit time count values of the detectors corresponding to the rest delay values except two delay values at two ends are the optimal delay values, wherein n is an integer greater than or equal to 3; the next step is carried out when the search of the bit synchronization delay search range is completed and the optimal delay value is obtained, and the fourth step is carried out when the search of the bit synchronization delay search range is not completed and the optimal delay value is obtained;
and seventhly, the bit synchronization processing unit obtains the optimal delay values of the detectors according to the counting values and sends the obtained optimal delay values to the delay control unit, and the delay control unit controls the delay of the detectors to be set as the optimal delay values so as to realize the required bit synchronization correction.
Preferably, said unit of time in the first step, including,
the current wheel position synchronously corrects the fixed time set during or before starting.
Preferably, the delay efficiency relationship in the first step is a pre-calibrated discrete point-to-point relationship, or a pre-calibrated functional relationship obtained according to a discrete point-to-point relationship, or a discrete point-to-point relationship obtained in real time or in a machine learning manner or a functional relationship obtained according to a discrete point-to-point relationship in actual use.
Preferably, the real-time counting value of the detector in the first step includes a real-time detection counting value or a counting value obtained from a real-time detection counting value in a unit time.
Preferably, the maximum count value of the detector in unit time obtained in the first step is obtained by comparing the current real-time count value of the detector with the currently recorded maximum count value of the detector in unit time;
if the current real-time count value of the detector is greater than the currently recorded maximum count value of the detector in unit time, updating the currently recorded maximum count value of the detector in unit time into the current real-time count value of the detector in unit time; if the real-time count value of the current detector in unit time is less than or equal to the maximum count value of the current recorded detector in unit time, keeping the maximum count value of the current recorded detector in unit time unchanged;
or if the real-time unit time counting value of the current detector is greater than or equal to the maximum unit time counting value of the current recorded detector, updating the maximum unit time counting value of the current recorded detector into the real-time unit time counting value of the current detector; and if the real-time unit time count value of the current detector is smaller than the maximum unit time count value of the current recorded detector, keeping the maximum unit time count value of the current recorded detector unchanged.
Preferably, the step of judging whether to start the real-time bit synchronization process according to the parameters obtained in the first step includes judging whether a real-time unit time count value of the current detector is lower than a set threshold value; if the real-time unit time count value of the current detector is lower than the set threshold, the judgment result is yes, otherwise, the judgment result is no; wherein the threshold value is set to be less than the maximum count value per unit time of the detector.
Preferably, the bit synchronization delay search range in the third step is determined according to a delay difference between two delay values corresponding to the normalized detection efficiency value in the delay efficiency relationship of the detector after the count value of the current detector in real time in unit time is normalized to the maximum value of the count value of the detector in unit time.
Preferably, each time the delay value of the adjustment probe of the fourth step is entered, the delay value of the adjustment probe is different from the previous delay value in one of the third steps.
Preferably, the count accumulation is a count accumulation in the unit time or a count accumulation in an arbitrary time length.
Preferably, each detector completes scanning of all delay values obtained in the third step, obtains a unit time detection count value of all delay values of each detector according to the obtained count value, finds an optimal delay value and a channel number of each detector according to the unit time count value, and then calculates and/or searches a delay efficiency relationship according to relative delay among the detectors and a delay initial value of each detector to obtain an optimal delay value of each detector;
or, each detector completes scanning of continuous n delay values in all delay values obtained in the third step, except two delay values at two ends, any unit time count value in unit time count values of detectors corresponding to the rest delay values is used as the maximum value of the n unit time count values, n unit time count values corresponding to the detectors are obtained, the detectors find the optimal delay value and channel number of the detectors according to the unit time count values, and then the optimal delay value of each detector is obtained by calculating and/or searching a delay efficiency relation according to the relative delay among the detectors and the initial delay value of each detector, wherein n is an integer greater than or equal to 3.
Preferably, after the seventh step is finished, the method returns to the first step, and a new round of bit synchronization operation is restarted.
The scheme has the following advantages:
1. the invention can count and monitor the detector in real time. When the detection count is reduced due to the change of the photon transmission time, the method starts a real-time bit synchronization process to acquire the optimal detection delay value without interrupting the security key generation process of the quantum key generation system.
2. The counting accumulation time of the detector is not fixed, the self-adaptive adjustment of the quantum channel is realized according to the counting of the detector, and when the counting value of the detector in unit time is higher, the counting accumulation time of the detector is correspondingly shortened, which is beneficial to improving the efficiency of a real-time bit synchronization scheme.
The method monitors the counting of the detector in real time and then carries out statistics. And judging whether bit synchronization is needed according to the change of the counting of the detector. When the detection count is reduced due to the change of the photon transmission time, the method starts a real-time bit synchronization process to acquire the optimal detection delay value without interrupting the security key generation process of the quantum key generation system.
According to the scheme provided by the application, when the counting of the detector is reduced (for example, the counting of the current detector is less than 95% of the maximum counting of the detector), the key generation process of the quantum key generation system is not required to be stopped, and feedback is carried out in real time, so that the effective working time of the quantum key distribution system is prolonged, and the safe key generation rate of the quantum key distribution system is improved.
Meanwhile, the scheme also reduces the influence of the external environment on the quantum key distribution system through the feedback mode, and improves the robustness of the quantum key distribution system.
Drawings
In order to more clearly explain the technical solution of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious to those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a flow diagram of a method for real-time bit synchronization correction for a quantum key generation system according to the present application;
FIG. 2 is a schematic diagram of the relationship between the delay efficiency of the detector;
FIG. 3 is an equal delay interval division of the detector delay search range, PariFor the detector factory setting, ti,e<PariA schematic view of the case of (1);
FIG. 4 is an equal delay interval division of the detector delay search range, PariFor the detector factory setting, ti,e>PariA schematic view of the case of (1);
FIG. 5 is an equal delay interval division of the detector delay search range, PariIs a schematic diagram under the condition of an initial set value of a bit synchronization process;
fig. 6 is a schematic diagram of arbitrary interval division of the detector delay search range.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, the present application is described in further detail with reference to the accompanying drawings and the detailed description.
The method utilizes a plurality of detectors to simultaneously measure local delay values, and integrates a plurality of local delay value measurement results to obtain an optimal delay value, thereby achieving the purpose of reducing the bit synchronization establishing time.
The method mainly comprises the following steps:
firstly, a bit synchronization processing unit continuously reads a real-time counting value of a detector and a real-time delay value of the corresponding detector, and obtains a delay efficiency relation of the detector, a maximum counting value in unit time and an optimal delay value corresponding to the maximum counting value;
secondly, according to the parameters obtained in the first step, the bit synchronization processing unit judges whether a real-time bit synchronization process is started or not, if the judgment result is that the real-time bit synchronization process is started, the step returns to the first step, and if the judgment result is that the real-time bit synchronization process is started, the next step is executed;
thirdly, the bit synchronization processing unit calculates the bit synchronization delay search range of each detector and the delay value required to be searched;
fourthly, the delay control unit adjusts the delay value of each detector to be one of the delay values obtained in the third step;
fifthly, counting and accumulating by the detector according to the delay value adjusted in the fourth step;
sixthly, the bit synchronization processing unit judges whether the search of the bit synchronization delay search range is finished or not, if the search is finished, the next step is carried out, and if the search is not finished, the fourth step is returned;
and seventhly, the bit synchronization processing unit obtains the optimal delay values of the detectors according to the counting, and sends the obtained optimal delay values to the delay control unit, and the delay control unit controls the delay setting of the detectors according to the optimal delay values to realize the required bit synchronization correction.
In particular, in the process, the first and second steps can be carried out in parallel or in an alternating order.
The detector counts and counts in real time, and the change of the detector count value is judged, when the detection count value is reduced due to the change of the photon transmission time, the method starts a real-time bit synchronization process and then obtains the optimal detection delay value without interrupting the safety key generation process of the quantum key generation system.
In the method, the counting accumulation time of the detector is not fixed, the self-adaptive adjustment of the quantum channel is realized according to the counting of the detector, and when the counting value of the detector in unit time is higher, the counting accumulation time of the detector is correspondingly shortened, so that the efficiency of a real-time bit synchronization scheme is improved.
The method monitors the counting value of the detector in real time and then carries out statistics. And judging whether bit synchronization is needed according to the change of the counting of the detector. When the detection count is reduced due to the change of the photon transmission time, the method starts a real-time bit synchronization process to acquire the optimal detection delay value without interrupting the security key generation process of the quantum key generation system.
According to the scheme provided by the application, when the counting value of the detector is reduced (for example, the counting value of the current detector is less than 95% of the maximum counting value of the detector), the key generation process of the quantum key generation system is not required to be stopped, and feedback is carried out in real time, so that the effective working time of the quantum key distribution system is prolonged, and the safe key generation rate of the quantum key distribution system is improved.
Meanwhile, the scheme also reduces the influence of the external environment on the quantum key distribution system through the feedback mode, and improves the robustness of the quantum key distribution system.
[ example 1 ]
Detector count integration time TiIs a counter value current _ det _ cnt of a detector unit time according to a current unit timeiThe specific method is as follows:
when current _ det _ cnt is current _ det _ cntiLess than Ni,1One/second, detector count effective accumulation time SiIs set as Si,1；
Current _ det _ cnti is greater than Ni,2One/second, detector count effective accumulation time TiIs set as Si,2；
current_det_cntiNot less than Ni,1One/second, and current _ det _ cntiNot more than Ni,2One/second, detector count effective accumulation time SiSetting as;
n is abovei,0、Ni,1、Ni,2、Si,1、Si,2Can set proper values according to self requirements。
Bit-synchronous delay search Range of ith detectoriIs set according to the response characteristic of the detector. Generally, the detection efficiency of a certain detector is related to its detection time as shown in FIG. 2, wherein the vertical axis data has been normalized to the maximum count det _ cnt of the detectormaxThen the bit synchronization delay search Range of the ith detectoriThe calculation method of (c) is as follows:
Rangei＝ΔTi×γi
in the formula,. DELTA.TiThe length of time, γ, between two instants corresponding to the lowest threshold value set for the ith detector in fig. 2iA certain value set artificially.
Normally, the detector should operate at the peak in fig. 2, i.e. the delay value of the detector is the peak time. Setting the time length from the peak to the threshold point on the left side of the peak as Rangei,1The time length to the threshold point on the right side of the peak is set to Rangei,2
Let PariDelay steps, t, set for the real-time bit synchronization process of the ith detectorc,iAnd setting the current initial delay value of the ith detector for the delay unit. The detector being at each tc,iCount accumulation is performed in the vicinity. Typically, the probe after manufacture, PariRemain unchanged. Is provided with
When Pari>ti,eWhen the value is more than or equal to 0, the delay value number n which needs to be searched in the bit synchronization delay search range of the detectoriComprises the following steps:
wherein,
represents a rounding of value
Is the largest positive integer of (a).
As shown in FIG. 3, t may be adjustedi,eTime period and grouping to any j-th after divisione(je∈(0,1,2,…,ni-1)) section, i.e. the j-th section after the divisione(je∈(0,1,2,…,ni-1)) segment delay range extension ti,eThe delay value T of the ith detector for searchingi,jComprises the following steps:
when j iseWhen the content is equal to 0, the content,
② when Pari<ti,eIn this case, the number of delay values to be searched is ni+1。
As shown in fig. 4, t isi,eA separate time period is set as
The delay value Ti, j of the ith detector that needs to search is:
when j iseWhen the content is equal to 0, the content,
in particular, when
When, Ti,j＝ti,j。
In particular, by adjusting γiLet t bei,e＝0。
In particular, the bit-synchronous delay search Range of the ith detectoriAnd the number n of delay values to be searchediThe calibration can be obtained after the detector is manufactured, and real-time calculation is not needed.
104, the delay control unit adjusts the delay value of the ith detector to be Ti,j。
And step 106, judging whether the search of the bit synchronization delay search range is finished. There are two situations at this time:
whether the detector scans all the delay values obtained in the step 103 is judged to be finished if the detector scans all the delay values obtained in the step 103.
And secondly, whether the detector finishes scanning of continuous k (k is more than or equal to 3) delay values, the unit time count value of one corresponding detector except two points at two ends in the k delay values is the maximum value, and if so, the detector is judged to be finished.
If not, updating the subscript j, and returning to the step 104; if yes, the next step is carried out.
Finding out the maximum value of the count in all the counts of each detector, wherein the delay value corresponding to the maximum value is the optimal delay value of the corresponding detector;
when the count of each detector corresponding to a certain delay value except two end point delay values is the maximum value of k counts in the unit time count value corresponding to any continuous k (k is more than or equal to 3) delay values of each detector, the delay value corresponding to the maximum value is the optimal delay value of the corresponding detector;
the delay control unit sets the delay of the detector to T according to the optimal detection delay valuei,maxThereby achieving the desired real-time bit synchronization.
[ example 2 ]
Step 201 synchronizes step 101.
Step 202 synchronizes step 102.
In step 203, the bit synchronization processing unit calculates the bit synchronization delay search range of each detector and the delay value of the required search.
Bit-synchronous delay search Range of ith detectoriIs set according to the response characteristic of the detector. Generally, the detection efficiency of a certain detector is related to its detection time as shown in FIG. 2, wherein the vertical axis data has been normalized to the maximum count det _ cnt of the detectormaxThen the bit synchronization delay search Range of the ith detectoriThe calculation method of (c) is as follows:
Rangei＝ΔTi×γi
in the formula,. DELTA.TiThe delay difference, gamma, between the two delay values corresponding to the lowest threshold value set for the ith detector in fig. 2iA certain value set artificially.
Normally, the detector should operate at the peak in fig. 2, i.e. the delay value of the detector is the peak time. Setting the delay difference value from the delay value corresponding to the peak value to the delay value corresponding to the threshold value on the left side of the peak value as Rangei,1The delay difference value of the delay value corresponding to the threshold point on the right side of the peak value is Rangei,2。
Setting the number of delay values to be searched in the bit synchronization delay search range of the detector as ni，PariAnd (3) the delay step set for the real-time bit synchronization process of the ith detector is as follows:
after the above formula, PariAnd remains unchanged during the present rotation synchronization process, as shown in fig. 3.
Let tc,iAnd setting the current initial delay value of the ith detector for the delay unit. The detector being at each tc,iCount accumulation is performed in the vicinity. Order to
ti,j＝tc,i-Rangei,1+j×Pari,(j＝0,1,2,…,ni-1)
In particular, when
When, Ti,j＝ti,j。
In particular, the bit-synchronous delay search Range of the ith detectoriAnd the number n of delay values to be searchediThe calibration can be obtained after the detector is manufactured, and real-time calculation is not needed.
Step 204 synchronizes step 104.
Step 205 synchronizes step 105.
Step 206 synchronizes step 106.
Step 207 synchronizes step 107.
[ example 3 ]
Step 301 synchronizes step 101.
Step 302 synchronizes step 102.
Step 303, calculating the bit synchronization delay search range of each detector and the delay value required to search.
Bit-synchronous delay search Range of ith detectoriIs set according to the response characteristic of the detector. Generally, the detection efficiency of a certain detector is related to its detection time as shown in FIG. 2, wherein the vertical axis data has been normalized to the maximum count det _ cnt of the detectormaxThen the bit synchronization delay search Range of the ith detectoriThe calculation method of (c) is as follows:
Rangei＝ΔTi×γi
in the formula,. DELTA.TiThe delay difference, gamma, between the two delay values corresponding to the lowest threshold value set for the ith detector in fig. 2iA certain value set artificially.
Normally, the detector should operate at the peak in fig. 2, i.e. the delay value of the detector is the peak time. Setting the delay difference value from the delay value corresponding to the peak value to the delay value corresponding to the threshold value on the left side of the peak value as Rangei,1The delay difference value of the delay value corresponding to the threshold point on the right side of the peak value is Rangei,2。
Let tc,iThe current delay initial value of the ith detector set for the delay unit, and the delay value of the real-time bit synchronization process of the ith detector is set as follows: will RangeiIs arbitrarily divided into successive niSegment, each segment delay range is marked as delta ti,j(j＝0,1,2,…,ni-1), as shown in fig. 4, when the probe is activatedEach delay step Par ofi,jThe value may be any value or may be a fixed value. Each detector at each Δ ti,jThe start delay values are accumulated as counts as shown in fig. 6.
Order to
In particular, when
When, Ti,j＝ti,j。
Step 304 synchronizes step 104.
Step 305 synchronizes step 105.
Step 306 synchronizes step 106.
Step 307 synchronizes step 107.
The above embodiments provide several cases that the delay search range is uniformly divided according to the delay step of the detector leaving the factory, the delay search range is uniformly divided according to the delay step required by implementation, and the delay search range is arbitrarily and non-uniformly divided. However, the delay search range involved may be a combination of uniform division and any non-uniform division, and various combinations of the division manner of the delay range and the division of the delay range fall within the protection scope of the present application.
[ example 4 ]
Step 401 synchronizes step 101.
Step 402 synchronizes step 102.
In step 403, the bit synchronization delay search range and the delay value of the required search of each detector are calculated.
Bit-synchronous delay search Range of ith detectoriIs set according to the response characteristic of the detector. Generally, the relationship between the detection efficiency of a certain detector and its detection time is shown in FIG. 2, whereinThe vertical axis data has been normalized to the maximum count det _ cnt of the detectormaxThen the bit synchronization delay search Range of the ith detectoriThe calculation method of (c) is as follows:
Rangei＝ΔTi×γi
in the formula,. DELTA.TiThe delay difference, gamma, between the two delay values corresponding to the lowest threshold value set for the ith detector in fig. 2iA certain value set artificially.
Normally, the detector should operate at the peak in fig. 2, i.e. the delay value of the detector is the peak time. Setting the delay difference value from the delay value corresponding to the peak value to the delay value corresponding to the threshold value on the left side of the peak value as Rangei,1The delay difference value of the delay value corresponding to the threshold point on the right side of the peak value is Rangei,2。
Let PariThe delay value number n of the i-th detector which needs to be searched in the bit synchronization delay search range is set for the delay stepping set in the real-time bit synchronization process of the detectoriComprises the following steps:
wherein,
represents a rounding of value
Is the largest positive integer of (a).
Let tc,iThe current delay value of the ith detector is set for the delay unit. The detector being at each tc,iCount accumulation is performed in the vicinity.
Is provided with
In particular, by adjusting γi、pariOne or more of the parameters are equal, such that ti,e＝0。
In particular, the bit-synchronous delay search Range of the ith detectoriAnd the number n of delay values to be searchediThe calibration can be obtained after the detector is manufactured, and real-time calculation is not needed.
Taking into account the time step required by the algorithm and ti,ePresence of (a):
when Pari>ti,eWhen t is more than or equal to 0, t can be adjustedi,eTime periods are grouped into any step size.
At this moment, the delay stepping Par in the schemei,jComprises the following steps:
when j ismWhen the content is equal to 0, the content,
② when Pari<ti,eThen t can be adjustedi,eA separate time period is set, and the number of delay values needed to search is ni+1。
At this moment, the delay stepping Par in the schemei,jComprises the following steps:
when j ismWhen the content is equal to 0, the content,
in particular, by adjusting γi、PariOne or more of the parameters are equal, such that ti,e＝0。
In particular, the bit synchronization of the ith detector corrects the delay search RangeiAnd the number n of delay values to be searchediThe calibration can be obtained after the detector is manufactured, and real-time calculation is not needed.
Subsequently, the scheme adopts a climbing algorithm to calculate and select a delay value:
first, the delay values of the 1 st search and the 2 nd search of the ith probe are set:
when t isc,i≥Pari,jTime of flight
When t isc,i<Pari,jTime of flight
Calculating the delay value of the subsequent j (j is more than or equal to 3) th search by adopting a climbing algorithm in a specific calculation mode
When cnt is measuredi，j-2>cnti，j-1And t isi，j-2<ti，j-1And t isi，j-2≥Pari，jWhen t isi,j＝ti,j-2-Pari,j；
When cnt is measuredi,j-2>cnti,j-1And t isi,j-2<ti,j-1And t isi,j-2<Pari,jWhen the temperature of the water is higher than the set temperature,
when cnt is measuredi,j-2>cnti,j-1And t isi,j-2>ti,j-1And is
When t isi,j＝ti,j-2+Pari,j；
When cnt is measuredi,j-2>cnti,j-1And t isi,j-2>ti,j-1And is
When t isi,j＝0；
When cnt is measuredi,j-2≤cnti,j-1And t isi,j-2<ti,j-1And is
When t isi,j＝ti,j-1+Pari,j；
When cnt is measuredi,j-2≤cnti,j-1And t isi,j-2<ti,j-1And is
When t isi,j＝0；
When cnt is measuredi,j-2≤cnti,j-1And t isi,j-2>ti,j-1And t isi,j-1≥Pari,jWhen t isi,j＝ti,j-1-Pari,j；
When cnt is measuredi,j-2≤cnti,j-1And t isi,j-2>ti,j-1And t isi,j-1<Pari,jWhen the temperature of the water is higher than the set temperature,
step 404, controlling the delay unit to adjust the delay value to ti,j。
Step 405, obtain the delay value t of the ith detectori,jCount cnt of lower detector per unit timei,j。
Step 406, determining whether the search of the bit synchronization correction delay search range is completed. There are two situations at this time:
whether the detector scans all the delay values obtained in the step 402 is judged to be finished if the detector scans all the delay values obtained in the step 402.
And secondly, whether the detector finishes scanning of continuous k (k is more than or equal to 3) delay values, the unit time count value of one corresponding detector except two points at two ends in the k delay values is the maximum value, and if so, the detector is judged to be finished.
Step 407, counting cnt per unit time according to each detectori,jFinding out the maximum count value of each detector unit time, and the delay value t corresponding to the maximum count value of the detector unit timei,maxI.e. the optimum detection delay value of the detector.
Finding out the maximum value of the count in all the counts of each detector, wherein the delay value corresponding to the maximum value is the optimal delay value of the corresponding detector;
when the count of each detector corresponding to a certain delay value except two end point delay values is the maximum value of k counts in the unit time count value corresponding to any continuous k (k is more than or equal to 3) delay values of each detector, the delay value corresponding to the maximum value is the optimal delay value of the corresponding detector;
the delay control unit sets the delay of the detector to t according to the optimal detection delay valuei,maxThereby achieving the desired real-time bit synchronization.
An example of an algorithm application is given in embodiment 4, in this embodiment, Par is performed for delay steppingi,jThe sizes of (A) and (B) are not limited, and may be the same or different. This embodiment does not prevent other algorithms from being applied to the scenario described in the present invention. Of course, in other algorithms, the delay difference between two adjacent delay values may be changed continuously according to the needs of different algorithms. The application of these algorithms to the described scenarios of the present invention also falls within the scope of the present invention.
The present application has been described in detail with reference to specific embodiments and illustrative examples, but the description is not intended to limit the application. Those skilled in the art will appreciate that various equivalent substitutions, modifications or improvements may be made to the presently disclosed embodiments and implementations thereof without departing from the spirit and scope of the present disclosure, and these fall within the scope of the present disclosure. The protection scope of this application is subject to the appended claims.
Claims (10)
1. A real-time bit synchronization correction method for a quantum key generation system, the method comprising,
firstly, a bit synchronization processing unit continuously reads a real-time counting value of a detector and a real-time delay value of the corresponding detector, and obtains a delay efficiency relation of the detector, a maximum counting value in unit time and an optimal delay value corresponding to the maximum counting value, wherein the delay efficiency relation of the detector is the relation between the counting value and the delay value of the detector;
secondly, according to the parameters obtained in the first step, the bit synchronization processing unit judges whether a real-time bit synchronization process is started or not, if the judgment result is that the real-time bit synchronization process is started, the step returns to the first step, and if the judgment result is that the real-time bit synchronization process is started, the next step is executed;
thirdly, a bit synchronization processing unit calculates a bit synchronization delay search range of each detector and a delay value to be searched, wherein the bit synchronization delay search range of each detector is a preset peak time interval, and the delay value to be searched is obtained according to the preset peak time interval and a preset delay step;
fourthly, the delay control unit adjusts the delay value of each detector to be one of the delay values obtained in the third step;
fifthly, counting and accumulating by the detector according to the delay value adjusted in the fourth step;
sixthly, judging whether the search of the bit synchronization delay search range is finished or not by the bit synchronization processing unit, and if the detector finishes scanning all the delay values obtained in the third step, determining the delay value corresponding to the maximum unit time count value as the optimal delay value; or the detector scans continuous n delay values in all the delay values obtained in the third step, and the delay values corresponding to the maximum unit time count value in the unit time count values of the detectors corresponding to the rest delay values except two delay values at two ends are the optimal delay values, wherein n is an integer greater than or equal to 3; the next step is carried out when the search of the bit synchronization delay search range is completed and the optimal delay value is obtained, and the fourth step is carried out when the search of the bit synchronization delay search range is not completed and the optimal delay value is obtained;
and seventhly, the bit synchronization processing unit obtains the optimal delay values of the detectors according to the counting values and sends the optimal delay values to the delay control unit, and the delay control unit controls the delay of the detectors to be set as the optimal delay values so as to realize the required bit synchronization correction.
2. The method of claim 1, wherein the unit time in the first step comprises,
the current wheel position synchronously corrects the fixed time set during or before starting.
3. The real-time bit synchronization modification method for a quantum key generation system according to claim 1,
the delay efficiency relationship in the first step is a pre-calibrated discrete point-to-point relationship, or a pre-calibrated functional relationship obtained according to a discrete point-to-point relationship, or a discrete point-to-point relationship obtained in real time or in a machine learning manner or a functional relationship obtained according to a discrete point-to-point relationship when in actual use.
4. The method of claim 1, wherein the real-time counting value of the detector in the first step comprises a real-time detection counting value or a counting value obtained from a real-time detection counting value in a unit time.
5. The real-time bit synchronization correction method for a quantum key generation system according to claim 1, wherein the obtaining of the maximum count value of the detector in the first step is obtained by comparing the current real-time count value of the detector with the currently recorded maximum count value of the detector in unit time;
if the current real-time count value of the detector is greater than the currently recorded maximum count value of the detector in unit time, updating the currently recorded maximum count value of the detector in unit time into the current real-time count value of the detector in unit time; if the real-time count value of the current detector in unit time is less than or equal to the maximum count value of the current recorded detector in unit time, keeping the maximum count value of the current recorded detector in unit time unchanged;
or if the real-time unit time counting value of the current detector is greater than or equal to the maximum unit time counting value of the current recorded detector, updating the maximum unit time counting value of the current recorded detector into the real-time unit time counting value of the current detector; and if the real-time unit time count value of the current detector is smaller than the maximum unit time count value of the current recorded detector, keeping the maximum unit time count value of the current recorded detector unchanged.
6. The method according to claim 1, wherein the determining whether to start the real-time bit synchronization process according to the parameters obtained in the first step includes determining whether a real-time unit time count value of a current detector is lower than a set threshold; if the real-time unit time count value of the current detector is lower than the set threshold, the judgment result is yes, otherwise, the judgment result is no; wherein the threshold value is set to be less than the maximum count value per unit time of the detector.
7. The real-time bit synchronization correction method for a quantum key generation system according to claim 1, wherein the bit synchronization delay search range of the third step is determined according to a delay difference between two delay values corresponding to the normalized detection efficiency value in the delay efficiency relationship of the detector after the current count value of the detector detected in real time is normalized to the maximum value of the count value of the detector per unit time.
8. A real-time bit synchronization correction method for a quantum key generation system as claimed in claim 1, wherein each time the delay value of the adjustment detector of the fourth step is entered, the delay value of the adjustment detector is different from the previous delay value in one of the third steps.
9. The method of real-time bit-sync modification for a quantum key generation system of claim 1,
each detector finishes scanning of all delay values obtained in the third step, obtains a unit time detection count value of all delay values of each detector according to the obtained count value, finds the optimal delay value and the channel number of each detector according to the unit time count value, and then calculates and/or searches a delay efficiency relation according to the relative delay among the detectors and the initial delay value of each detector to obtain the optimal delay value of each detector;
or, each detector completes scanning of continuous n delay values in all delay values obtained in the third step, except two delay values at two ends, any unit time count value in unit time count values of detectors corresponding to the rest delay values is used as the maximum value of the n unit time count values, n unit time count values corresponding to the detectors are obtained, the detectors find the optimal delay value and channel number of the detectors according to the unit time count values, and then the optimal delay value of each detector is obtained by calculating and/or searching a delay efficiency relation according to the relative delay among the detectors and the initial delay value of each detector, wherein n is an integer greater than or equal to 3.
10. The real-time bit synchronization modification method for a quantum key generation system according to claim 1,
and after the seventh step is finished, returning to the first step, and restarting a new round of bit synchronization operation.
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