CN111508942B - Signal processing circuit capable of avoiding performance degradation of collocated memory chip - Google Patents
Signal processing circuit capable of avoiding performance degradation of collocated memory chip Download PDFInfo
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- CN111508942B CN111508942B CN201910098338.8A CN201910098338A CN111508942B CN 111508942 B CN111508942 B CN 111508942B CN 201910098338 A CN201910098338 A CN 201910098338A CN 111508942 B CN111508942 B CN 111508942B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
Abstract
The present invention provides a signal processing circuit, which includes: the circuit board comprises a first surface layer, a second surface layer, a first reference layer and a second reference layer, wherein the first surface layer and the second surface layer are respectively positioned on the opposite sides of the circuit board, and the first reference layer and the second reference layer are positioned between the first surface layer and the second surface layer; the memory chip is positioned on the first surface layer; the controller chip is positioned on the second surface layer; a first group of signal lines arranged on the first surface layer and coupled to the memory chip, wherein the signal lines in the first group of signal lines do not cross each other; the second group of signal lines are arranged on the second surface layer and coupled to the controller chip, and the signal lines in the second group of signal lines cannot cross each other; the controller chip accesses the memory chip through the first set of signal lines, the second set of signal lines, and the plurality of vias located in the circuit board.
Description
Technical Field
The present invention relates to signal processing circuits, and more particularly, to a signal processing circuit capable of avoiding performance degradation of a memory chip in a collocated operation.
Background
Many signal processing circuits are mounted with high-speed memory chips of various specifications to operate. In many applications, the number of signal lines between the memory chip and the control chip in the signal processing circuit is very large, so the layout work of the signal lines becomes very complicated. It is known that the imperfect layout of signal lines may cause crosstalk interference between signal lines, and may increase the length of signal lines and the number of vias, thereby causing the delay amount or phase mismatch between the related signal lines.
To comply with the above situation, many memory chips degrade their operation and fail to achieve the theoretically optimal performance. As a result, the overall performance of the signal processing circuit is negatively affected.
Disclosure of Invention
In view of the above, how to avoid the performance degradation of the memory chip mounted on the signal processing circuit is a problem to be solved.
This specification provides an embodiment of a signal processing circuit, comprising: a circuit board, comprising a first surface layer, a second surface layer, a first reference layer, and a second reference layer, wherein the first surface layer and the second surface layer are respectively located at opposite sides of the circuit board, and the first reference layer and the second reference layer are located between the first surface layer and the second surface layer; a memory chip located on the first surface layer; a controller chip located on the second surface layer; a first group of signal lines, disposed on the first surface layer, coupled to the memory chip, and all of the signal lines of the first group of signal lines do not cross each other; and a second group of signal lines, disposed on the second surface layer, coupled to the controller chip, wherein all signal lines of the second group of signal lines do not cross each other; the controller chip is coupled to the memory chip through the first group of signal lines, the second group of signal lines and a plurality of guide holes penetrating through the circuit board; at least partial signal of the memory chip is designated to be axially symmetrical relative to a central axis of the memory chip; and at least partial signals of the controller chip are designated to be arranged in an axial symmetry manner relative to a central axis of the controller chip.
One of the advantages of the above embodiments is that all signal lines in the first group of signal lines do not cross each other, and all signal lines in the second group of signal lines do not cross each other, so that the possibility of crosstalk interference between the signal lines can be reduced.
Another advantage of the above embodiment is that the memory chip and the controller chip are respectively located on opposite sides of the circuit board, so that the number of vias through which at least most of the signal lines between the memory chip and the controller chip pass can be the same, thereby reducing or avoiding the situation of inconsistent delay or phase mismatch between the related signal lines.
Another advantage of the above embodiments is that the possibility of the memory chip degrading the operation of the memory chip due to the signals affected by crosstalk interference, inconsistent signal delay, and/or phase mismatch of the signals can be effectively reduced.
Other advantages of the present invention will be explained in more detail with reference to the following description and accompanying drawings.
Drawings
Fig. 1 is a simplified structural diagram of a signal processing circuit according to an embodiment of the present invention.
Fig. 2 is a simplified exploded cross-sectional view of the signal processing circuit of fig. 1 taken along the direction a-a'.
Fig. 3 is a simplified exploded view of the signal processing circuit of fig. 1.
Fig. 4 is a simplified structural diagram of a signal processing circuit according to another embodiment of the present invention.
Fig. 5 is a simplified cross-sectional exploded view of the signal processing circuit of fig. 4 along the direction B-B'.
Fig. 6 is a simplified exploded view of the signal processing circuit of fig. 4.
Description of the symbols
100 Signal processing circuit (signal processing circuit)
110 circuit board (printed circuit board, PCB)
112 first surface layer (first surface layer)
114 second surface layer (second surface layer)
116 first reference layer (first reference layer)
118 second reference layer (second reference layer)
120 memory chip (memory chip)
130 controller chip (controller chip)
222 solder ball (solder ball)
232 solder ball (solder ball)
240 first set of signal lines (first set of signal lines)
250 second set of signal lines (second set of signal lines)
260 guide hole (via)
280. 580 Attribute Pair (charateristic-swappoped region)
Detailed Description
Embodiments of the present invention will be described below with reference to the accompanying drawings. In the drawings, the same reference numbers indicate the same or similar elements or process flows.
Please refer to fig. 1 to fig. 3. Fig. 1 is a simplified structural diagram of a signal processing circuit 100 according to an embodiment of the present invention. Fig. 2 is an exploded cross-sectional view of the signal processing circuit 100 along the direction a-a'. Fig. 3 is a simplified exploded view of the signal processing circuit 100.
The signal processing circuit 100 includes a circuit board 110, a memory chip 120, and a controller chip 130. The circuit board 110 is a multilayer circuit board including at least a four-layer structure. In the embodiment, the circuit board 110 includes a first surface layer 112, a second surface layer 114, a first reference layer 116, and a second reference layer 118, wherein the first surface layer 112 and the second surface layer 114 are respectively located at opposite sides of the circuit board 110, and the first reference layer 116 and the second reference layer 118 are located between the first surface layer 112 and the second surface layer 114.
The memory chip 120 is located on the first surface layer 112 and configured to store data required for the operation of the signal processing circuit 100 or data generated by the controller chip 130. A controller chip 130 is located on the second skin 114 and is configured to access the memory chip 120 and control the operation of the signal processing circuit 100. In other words, the memory chip 120 and the controller chip 130 are respectively located on opposite sides of the circuit board 110.
In practice, the circuit board 110 may be implemented as a multilayer circuit board of various suitable materials. In addition, the memory chip 120 and the controller chip 130 can be packaged by various suitable packaging structures, such as Ball Grid Array (BGA) package, micro BGA (ball grid array) package, and so on.
The structure and signal line layout of the signal processing circuit 100 will be further described with reference to fig. 2 and 3.
As shown in fig. 2 and 3, the package of the memory chip 120 includes a plurality of solder balls 222, and the package of the controller chip 130 includes a plurality of solder balls 232. The solder balls 222 on the memory chip 120 are arranged in a manner corresponding to a signal assignment (signal assignment) of the memory chip 120. Similarly, the solder balls 232 on the controller chip 130 are arranged in a manner corresponding to the signal assignments of the controller chip 130.
In addition, the signal processing circuit 100 further includes a first set of signal lines 240 and a second set of signal lines 250. The first group of signal lines 240 is disposed on the first surface layer 112 and coupled to the memory chip 120. The second group of signal lines 250 is disposed on the second surface layer 114 and coupled to the controller chip 130. To simplify the complexity of the drawing, only one of the signal lines of the first group of signal lines 240 and one of the signal lines of the second group of signal lines 250 are shown in fig. 2 as an example.
The controller chip 130 may be coupled to the memory chip 120 through a first set of signal lines 240, a second set of signal lines 250, and a plurality of vias 260 extending through the circuit board 110 to access the memory chip 120.
In practical applications, other active components, passive components, related circuits and/or chips may be disposed on the circuit board 110 as required by the circuit design, but these components are not shown in fig. 1 to 3 for simplifying the drawing.
In the signal processing circuit 100, the controller chip 130 and the memory chip 120 may be arranged in a manner that the central axes are aligned with each other or arranged in a manner that the central axes are parallel to each other, so that signal lines connected between the controller chip 130 and the memory chip 120 do not need to cross each other, which helps to simplify the complexity of signal line layout. That is, in the chip arrangement, all the signal lines in the first group of signal lines 240 do not cross each other, and all the signal lines in the second group of signal lines 250 do not cross each other.
The arrangement of the controller chip 130 and the memory chip 120 is helpful to reduce or avoid the crossing of signal lines, thereby reducing the possibility of crosstalk interference between the signal lines.
Since the signal lines connected between the controller chip 130 and the memory chip 120 do not need to cross each other, the first group of signal lines 240 and the second group of signal lines 250 may be electrically connected to each other by using disposable vias. For example, as shown in fig. 2, any specific signal line 240 in the first group of signal lines 240 may be electrically connected to a corresponding signal line 250 in the second group of signal lines 250 through a plurality of vias 260 arranged vertically. The circuit board via hole mode is simple, and the number of the via holes through which all signal wires can pass is the same. For example, in the present embodiment, the number of vias coupled to each signal line in the first group of signal lines 240 and the number of vias coupled to each signal line in the second group of signal lines 250 are also 4.
The via hole arrangement mode can effectively control the length of the related signal lines so as to reduce or avoid the delay amount or phase inconsistency between the related signal lines.
In the embodiment of fig. 1-3, the first reference layer 116 is adjacent to the first skin layer 112, and the second reference layer 118 is adjacent to the second skin layer 114. As shown in fig. 2 and fig. 3, an attribute-reversed region 280 is intentionally disposed in a local region of the second reference layer 118, and the attribute-reversed region 280 covers a projection region of the second set of signal lines 250 on the second reference layer 118. In the signal processing circuit 100, the electrical properties of both the first reference layer 116 and the second reference layer 118 are opposite, but the properties on the second reference layer 118 are the same as the electrical properties of the first reference layer 116 for the exchange area 280.
For example, the first reference layer 116 may be set as a ground layer, the second reference layer 118 may be set as a power layer, and the property swap area 280 may be set as a ground area. As a result, the reference layer properties corresponding to the first group of signal lines 240 on the first surface layer 112, i.e., the properties of the projected area of the first group of signal lines 240 on the first reference layer 116 (in this case, the grounding properties), are the same as the reference layer properties corresponding to the second group of signal lines 250 on the second surface layer 114 (i.e., the properties of the attribute-to-area 280).
For another example, the first reference layer 116 may be set as a power plane, the second reference layer 118 may be set as a ground plane, and the property swap area 280 may be set as a power plane. In this way, the reference layer properties corresponding to the first set of signal lines 240 on the first surface layer 112, i.e., the properties of the projected area of the first set of signal lines 240 on the first reference layer 116 (in this case, the power source properties) are the same as the reference layer properties corresponding to the second set of signal lines 250 on the second surface layer 114 (i.e., the properties of the property-to-region 280).
In practice, an appropriate insulating material may be disposed around the property-exchanged region 280 to prevent the property-exchanged region 280 from directly contacting other regions of the second reference layer 118 to form a short circuit. The aforementioned manner of intentionally disposing the property-exchanging region 280 in the local region of the second reference layer 118 can prevent the signal quality and/or the signal accuracy between the memory chip 120 and the controller chip 130 from being adversely affected by the property variation of the reference layer on the signal line path.
As can be seen from the foregoing description, the placement and arrangement of the memory chip 120 and the controller chip 130 in the signal processing circuit 100, the signal line via pattern, and the property-exchanging region 280 in the local area of the second reference layer 118 can reduce or eliminate the chance of crosstalk interference on the signal, reduce or eliminate the mismatch between the signal delay and the signal phase, and avoid the degradation of the signal quality and/or accuracy due to the difference between the reference layer properties.
Thus, the possibility of the memory chip 120 degrading its operation due to the aforementioned problems can be effectively reduced or avoided. In other words, by the design of the circuit architecture, the chance of the memory chip 120 performing the theoretically optimal performance can be effectively improved, and the overall operation performance of the signal processing circuit 100 can be further improved.
Please note that the relative positions of the first reference layer 116 and the second reference layer 118 are only exemplary embodiments and are not intended to limit the practical implementation of the present invention. In practice, the positions of the first reference layer 116 and the second reference layer 118 may be interchanged.
For example, please refer to fig. 4 to 6. Fig. 4 is a simplified structural diagram of a signal processing circuit 100 according to another embodiment of the present invention. Fig. 5 is a simplified exploded cross-sectional view of the signal processing circuit 100 of fig. 4 along the direction B-B'. Fig. 6 is a simplified exploded schematic diagram of the signal processing circuit 100 of fig. 4.
In the embodiment of fig. 4-6, the first reference layer 116 is adjacent to the second skin layer 114, and the second reference layer 118 is adjacent to the first skin layer 112. As shown in fig. 5 and fig. 6, an attribute-to-area 580 is disposed in a local area of the second reference layer 118 of the present embodiment, and the attribute-to-area 580 covers a projection area of the first group of signal lines 240 on the second reference layer 118. The properties on the second reference layer 118 will be the same as the electrical properties of the first reference layer 116 for the exchange area 580.
For example, the first reference layer 116 may be set as a ground layer, the second reference layer 118 may be set as a power layer, and the property swap area 580 may be set as a ground area. As a result, the reference layer properties corresponding to the second group of signal lines 250 on the second surface layer 114, i.e., the properties of the projected area of the second group of signal lines 250 on the first reference layer 116 (in this case, the grounding properties), are the same as the reference layer properties corresponding to the first group of signal lines 240 on the first surface layer 112 (i.e., the properties of the property-to-region 580).
For another example, the first reference layer 116 may be set as a power plane, the second reference layer 118 may be set as a ground plane, and the property swap area 280 may be set as a power plane. In this way, the reference layer properties corresponding to the second group of signal lines 250 on the second surface layer 114, i.e., the properties of the projected areas of the second group of signal lines 250 on the first reference layer 116 (in this case, the power source properties) are the same as the reference layer properties corresponding to the first group of signal lines 240 on the first surface layer 112 (i.e., the properties of the property swap area 580).
Similarly, an appropriate insulating material may be disposed around attribute-swap region 580 to avoid short-circuiting attribute-swap region 580 directly contacting other regions of second reference layer 118. The aforementioned manner of intentionally disposing the property-swapping area 580 in the local area of the second reference layer 118 can prevent the signal quality and/or signal accuracy between the memory chip 120 and the controller chip 130 from being adversely affected by the property variation of the reference layer on the signal path.
The foregoing descriptions regarding the connection, implementation, operation, and related advantages of other elements in the embodiments of fig. 1-3 also apply to the embodiments of fig. 4-6. For the sake of brevity, the description is not repeated here.
In addition, in some embodiments, the via hole pattern of the signal line, which is not affected by the signal delay or the signal phase difference, may be changed to be different from that of other signal lines, so as to increase the flexibility of the signal line layout. In this case, the number of vias to which these signal lines are coupled may be different from that of other signal lines. Generally, under the aforementioned via layout principle, at least 50% of the signal lines in the first group of signal lines 240 are coupled to the same number of vias, and at least 50% of the signal lines in the second group of signal lines 250 are coupled to the same number of vias.
In practice, other ground layers, power layers, and/or signal layers may be disposed between the first reference layer 116 and the second reference layer 118 in the embodiments of fig. 1 to 6 as needed. In other words, the circuit board 110 may be implemented by a circuit board having more layers.
Certain terms are used throughout the description and claims to refer to particular elements, and those skilled in the art may refer to like elements by different names. The present specification and claims do not intend to distinguish between components that differ in name but not function. In the description and claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Also, the term "coupled" is intended to include any direct or indirect connection. Therefore, if a first element is coupled to a second element, the first element can be directly connected to the second element through an electrical connection or a signal connection such as wireless transmission or optical transmission, or indirectly connected to the second element through another element or a connection means.
The description of "and/or" as used in this specification is inclusive of any combination of one or more of the items listed. In addition, any singular term shall include the plural unless the specification specifically states otherwise.
The term "element" as used in the specification and claims encompasses the concept of a component, layer, or region.
The dimensions and relative sizes of some of the elements in the figures may be exaggerated or the shape of some of the elements simplified to more clearly illustrate the content of the embodiments. Accordingly, unless otherwise indicated by the applicant, the shapes, sizes, relative positions and the like of the elements in the drawings are merely for convenience of description, and should not be used to limit the claims of the present invention. Furthermore, the present invention may be embodied in many different forms and should not be construed as limited to the embodiment set forth herein.
For convenience in explanation, the description may use some statements related to relative positions in space to describe the function of a certain element or the relative spatial relationship of that element to other elements in the drawings. For example, "on …," "above …," "below …," "below …," "above …," "below …," "up," "down," and the like. It will be understood by those skilled in the art that these descriptions relating to the relative positions in space include not only the orientation of the described elements in the drawings, but also the various orientations of the described elements in use, operation, or assembly. For example, if the drawings are turned upside down, elements originally described as "at … above" would then become "at … below". Therefore, the description of "on …" used in the specification includes two different orientations of "under …" and "on …". Similarly, the term "upwardly" as used herein is to be interpreted to encompass both the different directional relationships "upwardly" and "downwardly".
In the specification and claims, if a first element is described as being on, over, connected, joined, coupled, or connected to a second element, it is intended that the first element can be directly on, connected, joined, coupled, or coupled to the second element, or that there are other elements between the first and second elements. In contrast, if a first element is described as being directly on, directly connected to, directly engaged with, directly coupled to, or directly connected to a second element, that means that there are no other elements present between the first and second elements.
The above are only preferred embodiments of the present invention, and all equivalent changes and modifications made by the claims of the present invention should be covered by the present invention.
Claims (4)
1. A signal processing circuit (100), comprising:
a circuit board (110) comprising a first surface layer (112), a second surface layer (114), a first reference layer (116), and a second reference layer (118), wherein the first surface layer (112) and the second surface layer (114) are respectively located on opposite sides of the circuit board (110), and the first reference layer (116) and the second reference layer (118) are located between the first surface layer (112) and the second surface layer (114);
a memory chip (120) on the first skin (112);
a controller chip (130) on the second surface layer (114);
a first set of signal lines (240) disposed on the first surface layer (112) and coupled to the memory chip (120), wherein all of the signal lines of the first set of signal lines (240) do not cross each other; and
a second set of signal lines (250) disposed on the second surface layer (114) and coupled to the controller chip (130), wherein all of the signal lines of the second set of signal lines (250) do not cross each other;
wherein the controller chip (130) is coupled to the memory chip (120) through the first set of signal lines (240), the second set of signal lines (250), and a plurality of vias (260) that extend through the circuit board (110); at least partial signals of the memory chip (120) are assigned to be arranged in axial symmetry with respect to a central axis of the memory chip (120); and at least a local signal of the controller chip (130) is assigned to be disposed in axial symmetry with respect to a central axis of the controller chip (130), wherein the first reference layer (116) is adjacent to the first surface layer (112), the second reference layer (118) is adjacent to the second surface layer (114), an attribute-reversed region (280) is disposed in a local region of the second reference layer (118), and the attribute-reversed region (280) covers a projection region of the second set of signal lines (250) on the second reference layer (118);
wherein the electrical properties of both the first reference layer (116) and the second reference layer (118) are opposite and the electrical property of the swap area (280) is the same as the electrical property of the first reference layer (116).
2. The signal processing circuit (100) of claim 1, wherein at least 50% of the signal lines in the first set of signal lines (240) are coupled to the same number of vias, and at least 50% of the signal lines in the second set of signal lines (250) are coupled to the same number of vias.
3. A signal processing circuit (100), comprising:
a circuit board (110) comprising a first surface layer (112), a second surface layer (114), a first reference layer (116), and a second reference layer (118), wherein the first surface layer (112) and the second surface layer (114) are respectively located on opposite sides of the circuit board (110), and the first reference layer (116) and the second reference layer (118) are located between the first surface layer (112) and the second surface layer (114);
a memory chip (120) on the first skin (112);
a controller chip (130) on the second surface layer (114);
a first set of signal lines (240) disposed on the first surface layer (112) and coupled to the memory chip (120), wherein all of the signal lines of the first set of signal lines (240) do not cross each other; and
a second set of signal lines (250) disposed on the second surface layer (114) and coupled to the controller chip (130), wherein all of the signal lines of the second set of signal lines (250) do not cross each other;
wherein the controller chip (130) is coupled to the memory chip (120) through the first set of signal lines (240), the second set of signal lines (250), and a plurality of vias (260) that extend through the circuit board (110); at least partial signals of the memory chip (120) are assigned to be arranged in axial symmetry with respect to a central axis of the memory chip (120); and at least a local signal of the controller chip (130) is assigned to be disposed in axial symmetry with respect to a central axis of the controller chip (130), wherein the first reference layer (116) is adjacent to the second surface layer (114), the second reference layer (118) is adjacent to the first surface layer (112), an attribute-swapping area (580) is disposed in a local area of the second reference layer (118), and the attribute-swapping area (580) covers a projection area of the first set of signal lines (240) on the second reference layer (118),
wherein electrical properties of both the first reference layer (116) and the second reference layer (118) are opposite and the property is the same for the swap area (580) as the electrical property of the first reference layer (116).
4. The signal processing circuit (100) of claim 3, wherein at least 50% of the signal lines in the first set of signal lines (240) are coupled to the same number of vias, and at least 50% of the signal lines in the second set of signal lines (250) are coupled to the same number of vias.
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| CN201910098338.8A CN111508942B (en) | 2019-01-31 | 2019-01-31 | Signal processing circuit capable of avoiding performance degradation of collocated memory chip |
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| CN201910098338.8A CN111508942B (en) | 2019-01-31 | 2019-01-31 | Signal processing circuit capable of avoiding performance degradation of collocated memory chip |
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| CN111508942A CN111508942A (en) | 2020-08-07 |
| CN111508942B true CN111508942B (en) | 2022-02-25 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5567654A (en) * | 1994-09-28 | 1996-10-22 | International Business Machines Corporation | Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging |
| US7023719B1 (en) * | 2003-10-23 | 2006-04-04 | Lsi Logic Corporation | Memory module having mirrored placement of DRAM integrated circuits upon a four-layer printed circuit board |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4569912B2 (en) * | 2000-03-10 | 2010-10-27 | エルピーダメモリ株式会社 | Memory system |
| JP4886308B2 (en) * | 2005-09-16 | 2012-02-29 | 株式会社東芝 | USB memory device |
| JP6200236B2 (en) * | 2013-08-09 | 2017-09-20 | ルネサスエレクトロニクス株式会社 | Electronic equipment |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5567654A (en) * | 1994-09-28 | 1996-10-22 | International Business Machines Corporation | Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging |
| US7023719B1 (en) * | 2003-10-23 | 2006-04-04 | Lsi Logic Corporation | Memory module having mirrored placement of DRAM integrated circuits upon a four-layer printed circuit board |
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