CN111506462A - Mainboard test method and mainboard test system - Google Patents
Mainboard test method and mainboard test system Download PDFInfo
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- CN111506462A CN111506462A CN201910097670.2A CN201910097670A CN111506462A CN 111506462 A CN111506462 A CN 111506462A CN 201910097670 A CN201910097670 A CN 201910097670A CN 111506462 A CN111506462 A CN 111506462A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2284—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by power-on test, e.g. power-on self test [POST]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2289—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by configuration test
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention provides a mainboard test method, which is executed by a mainboard test system electrically connected with a power supply to operate, the mainboard test system comprises a mainboard and an auxiliary unit, the mainboard comprises a central processing unit, a platform path controller, a first memory, a second memory and a first network interface port, when the platform path controller selects the first memory, the central processing unit executes a first system image file and then sends a notice to the first network interface port, the auxiliary unit controls the power supply not to output electric energy by the platform path controller, controls the platform path controller to select the second memory and controls the platform path controller to enable the power supply to output electric energy, so that the central processing unit executes a second system image file.
Description
Technical Field
The present invention relates to a test method and a test system with an internal control program, and more particularly, to a method and a system for testing a motherboard under microinstruction control or micro-program control.
Background
Referring to fig. 1, a conventional motherboard 11 is loaded with different settings according to different pin combinations (pins) of a jumper cap (jumper) 12 disposed on the motherboard during a power-on test, and generally, the jumper cap 12 is manually sleeved on the pins to be turned on.
However, it is limited that the motherboard can be tested by manually setting the jumper cap, which wastes a lot of human resources and is not good for economic benefit, and therefore, how to automatically test the motherboard is a future research direction.
Disclosure of Invention
The present invention is to provide a motherboard testing method, which can automatically switch and read the relevant system image files by the central processing unit via the platform path controller controlling the motherboard without manual control.
In order to solve the above technical problems, a motherboard testing method and a motherboard testing system are executed by a motherboard testing system for receiving operating power provided by a power supply and operating in one of a disabled state and an enabled state, wherein the motherboard testing system comprises a motherboard and an auxiliary unit.
The mainboard comprises a central processing unit, a platform path controller electrically connected with the central processing unit and the power supply, a first memory electrically connected with the platform path controller and storing a first system image file, and a second memory electrically connected with the platform path controller and storing a second system image file.
The auxiliary unit is electrically connected with the mainboard.
The method for testing the motherboard includes a step (B3), a step (B7), a step (B8), a step (B9), and a step (B10).
The step (B3) is that when the platform path controller selects the first memory according to the configuration of the auxiliary unit, the cpu reads and executes the first system image file through the platform path controller.
The step (B7) is that the auxiliary unit sends a shutdown signal to the power supply via the platform path controller according to a notification signal sent by the central processing unit, so that the power supply does not provide operation power to the motherboard, and the motherboard is operated in the disabled state.
The step (B8) sets the platform path controller for the auxiliary unit to switch to select the second memory.
The step (B9) is that the auxiliary unit sends a power-on signal to the power supply via the platform path controller according to the notification signal, and the power supply provides operation power to the motherboard to enable the motherboard to operate in the enabled state.
The step (B10) is that the cpu reads and executes the second system image file via the platform path controller.
The invention also provides a mainboard test system which can make the central processing unit automatically switch and read the relevant system image files by controlling the platform path controller of the mainboard without manual control.
The invention relates to a mainboard test system which is used for receiving electric energy provided by a power supply and operates in one of a forbidden energy state and an energy consistent state.
The mainboard comprises a central processing unit, a platform path controller, a first memory and a second memory.
The platform path controller is electrically connected with the central processing unit and the power supply.
The first memory is electrically connected with the platform path controller and stores a first system image file.
The second memory is electrically connected with the platform path controller and stores a second system image file.
The auxiliary unit is electrically connected with the platform path controller and used for controlling and setting the platform path controller to select one of the first memory and the second memory.
When the auxiliary unit sets the platform path controller to select the first memory, the CPU reads and executes the first system image file through the platform path controller, the auxiliary unit sends a shutdown signal to the power supply through the platform path controller according to a notification signal sent by the central processing unit, so that the power supply does not provide operation electric energy to the mainboard, and the mainboard is operated in the disabled state, the auxiliary unit controls and sets the platform path controller to switch to select the second memory according to the notification signal, the auxiliary unit controls the platform path controller to send a power-on signal to the power supply according to the notification signal, so that the power supply provides operating power to the motherboard, and the CPU reads and executes the second system image file through the platform path controller.
Compared with the prior art, the mainboard test method and the mainboard test system of the invention have the advantages that the auxiliary unit controls the power supply to provide/not provide the operation electric energy for the mainboard through the platform path controller according to the notification signal, so that the mainboard is switched between the disabled state and the enabled state, and during the mainboard switching period, the auxiliary unit controls and sets the platform path controller to switch the image file setting according to the notification signal so as to select different memories, so that the central processing unit reads and executes different system image files after the mainboard is switched to the enabled state and is started.
[ description of the drawings ]
Fig. 1 is a partial schematic view illustrating a conventional motherboard.
FIG. 2 is a diagram illustrating a first embodiment of a motherboard testing system according to the present invention.
Fig. 3 is a partial schematic view to assist in explaining the operation mechanisms of a first and a second relay module according to the embodiment.
Fig. 4 is a flowchart illustrating a method for testing a motherboard according to the embodiment.
Fig. 5 is a flowchart for assisting in explaining an operation test procedure of the motherboard testing method.
FIG. 6 is a diagram illustrating a second embodiment of a motherboard testing system according to the present invention.
Fig. 7 is a flowchart illustrating a method for testing a motherboard according to the embodiment.
Fig. 8 is a flowchart for assisting in explaining a step of executing a test program of the motherboard testing method.
[ detailed description ] embodiments
The first embodiment:
referring to fig. 2, a first embodiment of the motherboard testing system for receiving power provided by a power supply 1 and operating in one of a disabled state and an enabled state according to the present invention includes a motherboard 2, an auxiliary unit 3, and a testing server 4.
The motherboard 2 includes a central processing unit 21, a hard disk module 22, a platform path controller 23, a first memory 24, a second memory 25, a first network interface port 28, and a second network interface port 29.
The hard disk module 22 is connected to the central processing unit 21 through the platform path controller, and stores a test program for the central processing unit 21 to execute corresponding to a trigger signal.
The Platform path Controller 23 (PCH) is electrically connected to the cpu 21 and the power supply 1, and is configured to receive and transmit the trigger signal to the cpu 21.
It should be noted that when the power supply 1 receives an externally provided ac power source (e.g., commercial power), when the motherboard is powered on, the power supply 1 may provide the motherboard power-on operation power and the standby power at the same time, and when the motherboard is powered off, the power supply 1 may not provide the motherboard power-on operation power, but may still provide the standby power to the platform path controller 23 of the motherboard, so that the platform path controller 23 may detect a power-on control signal generated by a user pressing a power-on key in a system power-off state.
In addition, the cpu 21 and the platform path controller 23 are electrically connected to each other via a Direct Media Interface (DMI), i.e., a bus, and the cpu 21 reads and executes the test program stored in the hard disk module 22 according to the trigger signal received by the platform path controller 23.
Generally speaking, a motherboard is usually configured with two chips for establishing data transmission channels between a central processing unit and a Peripheral device, i.e., a south bridge and a north bridge, the south bridge is mainly responsible for low-speed data Bus transmission, such as Serial Advanced Technology Attachment (Serial Advanced Technology Attachment) Bus and local area network (L AN: L) and the north bridge is responsible for reading of a Peripheral component interconnect (PCI-E: Peripheral component interconnect) Bus and a Random Access Memory (RAM), but since the speed of the central processing unit is continuously increased, the bandwidth of the front-side Bus is not changed, (i.e., the connection between the central processing unit and the north bridge), and the platform path controller re-allocates various data Bus input/output functions, which integrates the Memory controller and the Peripheral component interconnect standard controller into a chip set (chipset) and replaces some original functions of the south bridge and connects other data Bus input/output devices, such as a Serial Bus interface (USB) and connects other data Bus devices, such as a Serial Bus, a USB (USB) and a USB interface.
The first memory 24 is electrically connected to the platform path controller 23 and stores a first system image file related to the test program.
The second memory 25 is electrically connected to the platform path controller 23 and stores a second system image file related to the test program.
The first and second memories 24 and 25 are Flash memories (NVM) of Non-Volatile memory type, and the first and second System image files are Basic Input/Output System (BIOS) image files.
The platform path controller 23 is electrically connected to the auxiliary unit 3 and is controlled by the setting of the auxiliary unit 3 to select one of the first and second memories 24 and 25.
The first network interface port 28 is electrically connected to the platform path controller 23 and is used for receiving the trigger signal transmitted from the outside.
The second network interface port 29 is electrically connected to the platform path controller 23 and receives a notification signal from the central processing unit 21 via the platform path controller 23.
The auxiliary unit 3 includes a tool network interface port 31, a microcontroller 32, a first relay module 33, and a second relay module 34.
The tool network interface port 31 is electrically connected to the second network interface port 29, and receives the notification signal transmitted from the central processing unit 21 and transmitted to the second network interface port 29 via the platform path controller 23.
The microcontroller 32 includes a logic operation unit 321 electrically connected to the tool network interface port 31 for receiving the notification signal sent by the central processing unit 21, and a memory 322 electrically connected to the logic operation unit 321 in a plug-in manner and storing a batch file related to the notification signal.
The first relay module 33 is electrically connected to the logic operation unit 321 and the platform path controller 23, and transmits an on/off analog signal to the platform path controller 23 when the batch file is executed according to the logic operation unit 321, and the platform path controller 23 controls the power supply 1 to provide/not provide the operation electric energy to the motherboard 2 according to the received on/off analog signal, so that the motherboard 2 operates in one of the enabled state and the disabled state. It should be noted that the first relay module 33 is directly electrically connected to a General Purpose Input/Output pin (GPIOpin) of the platform path controller 23 to transmit the power on/off analog signal to the platform path controller 23, and the platform path controller 23 controls the power supply 1 according to the power on/off analog signal, so that the power supply 1 provides or does not provide power to the motherboard 2.
In the present embodiment, the switching mechanism for the power supply 1 to control the supply/non-supply of the operating power is that the microcontroller 32 of the auxiliary unit 3 controls the first relay module 33 to switch from the high potential (pull high) to the low potential (pull low) and then switch back to the high potential (pull high) to simulate and replace the conventional action of generating the power-on control signal by pressing the power key by the user, referring to fig. 3, the detailed actuation mechanism of the first relay module 33 is further described in detail, the first relay module 33 has a signal input end 331, a control end 332, a first signal output end 333, and a second signal output end 334, and the mechanism for the first relay module 33 to simulate a pulse signal output is as follows: the signal input terminal 331 is grounded and is electrically connected to the second signal output terminal 334 in advance, the first signal output terminal 333 is electrically connected to a power switch control pin of the platform path controller 23 and is electrically connected to a resistor R1 for receiving a voltage source VCC, therefore, the voltage level of the first signal output terminal 333 is preset to be high, and the second signal output terminal 334 is floating, the control terminal 332 then controls the signal input terminal 331 to switch to be electrically connected to the general purpose input/output pin of the platform path controller 23, after a first pulse time (about 0.3-0.5 seconds) elapses, the low voltage is input to the stage path controller 23, and the first relay module 33 is switched back, i.e., the first signal output terminal 333 electrically connected to the high voltage is electrically disconnected from the signal input terminal 331 connected to the ground, so that a low voltage pulse is generated.
The second relay module 34 is electrically connected to the logic operation unit 321, and is electrically connected to two general purpose input/output pins of the platform path controller 23, so as to transmit a power-on setting to the platform path controller 23, where the power-on setting corresponds to the first and second system image files stored in the first and second memories 24 and 25, respectively, when the second relay module 34 executes the batch file according to the logic operation unit 321, the second relay module 34 is controlled to provide the power-on setting to the platform path controller 23, and the platform path controller 23 selects one of the first and second memories 24 and 25 as a target bios image file to be executed by the next power-on according to the power-on setting.
On the other hand, the platform path controller 23 can select the first and second mapping files of the first and second memories 24 and 25 according to the following three modes:
first, the two general purpose i/o pins of the platform path controller 23 respectively correspond to the first and second system image files stored in the first and second memories 24 and 25, respectively, and correspondingly switch the image file settings thereof to correspondingly select one of the first and second memories 24 and 25 according to the voltage level received by the general purpose i/o pins as the power-on setting, and further set and select the target bios image file to be executed by the next power-on, for example, when one of the general purpose i/o pins receives a high potential, the platform path controller 23 selects the first memory 24 to select and set the corresponding first system image file as the target bios image file to be executed by the next power-on.
Secondly, the platform path controller 23 switches its internal mapping file setting to correspondingly select one of the first and second memories 24 and 25 according to the voltage level received by a specific general-purpose input/output pin thereof as a power-on setting, so as to set and select the target basic input/output system mapping file to be executed in the next power-on, for example, when the voltage level received by the specific general-purpose input/output pin is a high level, the platform path controller 23 is electrically conducted with the first memory 24, so as to select and set the corresponding first system mapping file as the target basic input/output system mapping file to be executed in the next power-on, otherwise, the corresponding second system mapping file is selected and set.
It should be further noted that the implementation mode of the platform path controller 23 selecting one of the first and second memories 24 and 25 is as follows: the two sets of buses of the platform path controller 23 are respectively connected to the first and second memories 24 and 25, and the platform path controller 23 controls to switch the image file setting therein according to the power-on setting to select one of the first and second memories 24 and 25.
In another embodiment, the platform path controller 23 controls a switch module (not shown) electrically connected to the first and second memories 24 and 25 to be switched to electrically connect to one of the first and second memories 24 and 25 according to the power-on setting.
The test server 4 is electrically connected to the first network interface port 28 and sends an address to the first network interface port 28 by Dynamic Host Configuration Protocol (DHCP) and sends the trigger signal to the first network interface port 28 according to the address, furthermore, the test server 4 can search a computer device having a fixed address in its local network connection range by the DHCP, and the tool network interface port 31 of the auxiliary unit 3 has a fixed address, so that the test server 4 can search the fixed address by the DHCP and send the fixed address to the second network interface port 29 of the main board 2, so that the CPU 21 of the main board 2 can send the notification signal to the tool network interface port 31 of the auxiliary unit 3 by the fixed address through the platform path controller 23 and the second network interface port 29, in addition, the test server 4 can transmit the address assigned to the first network interface port 28 to the tool network interface port 31 of the auxiliary unit 3.
Referring to fig. 4, the method for testing a motherboard according to the embodiment includes a step (a) of sending a trigger command, and a step (B) of running a test program.
The step of sending the trigger signal is (A): the test server 4 sends the trigger signal to the first network interface port 28 according to the address assigned to the first network interface port 28, and transmits the trigger signal to the CPU 21 via the platform path controller 23.
The operation test procedure comprises the following steps: the cpu 21 executes the test program stored in the hard disk module 22 according to the trigger signal.
Referring to fig. 5, in detail, the operation test procedure step (B) further includes a primary system image test sub-step (B3), a notification sending sub-step (B4), a batch file reading sub-step (B5), a waiting sub-step (B6), a control shutdown sub-step (B7), a control switch sub-step (B8), a control startup sub-step (B9), and a backup system image test sub-step (B10).
The primary system image file testing sub-step (B3) is as follows: the cpu 21 executes a selected target bios image, for example, the second relay module 34 provides the preset Power-on setting to the platform path controller 23 according to the preset control of the logical operation unit 321, and the platform path controller 23 selects the first memory 24 as the target bios image to be executed during the next Power-on according to the preset Power-on setting, so that the cpu 21 executes the first system image stored in the first memory 24 to perform the system hardware configuration detection related to the first system image, i.e., execute the Power-on Self-test (POST) related to the hardware configuration.
The transmission notification substep (B4) is: when the CPU 21 executes the first system image file, it then sends the notification signal to the platform path controller 23, and transmits the notification signal to the second network interface port 29 via the platform path controller 23.
The read lot file sub-step (B5) is: the tool network interface port 31 receives the notification signal from the second network interface port 29, and the logic operation unit 321 reads and executes the batch file stored in the memory 322 according to the notification signal received by the tool network interface port 31.
The waiting substep (B6) is: the logic operation unit 321 waits for a predetermined time (e.g., any one of 1 to 60 seconds) by executing the batch file.
The control shutdown substep (B7) is: the logic operation unit 321 controls the first relay module 33 to generate an on/off analog signal to the platform path controller 23 according to the address of the motherboard 2 allocated by the test server 4, so as to switch the power supply 1 to the disabled state via the platform path controller 23.
It should be noted that in the sub-step of controlling power-off (B7), the first relay module 33 generates the power-on/off analog signal through its pin (pin) electrically connected to the platform path controller 23 to simulate a high/low peak pulse signal, and transmits the high/low peak pulse signal to the platform path controller 23 to control the power supply to turn off the power supply.
The control switching sub-step (B8) is as follows: the logic operation unit 321 controls the second relay module 34 to generate the power-on setting to the platform path controller 23, so as to switch the image file setting of the platform path controller 23 to select the second memory 25.
The control power-on sub-step (B9) is as follows: the logic operation unit 321 controls the first relay module 33 to generate another power-on analog signal to the platform path controller 23, so as to switch the power supply to the enabled state.
The backup system image file test sub-step (B10) is: when the power supply 1 is in the enabled state and outputs the operating power to the motherboard for the operation of the central processing unit 21, the central processing unit 21 then reads the second system image file stored in the second memory 25 according to the selected second memory 25 via the platform path controller 23 to execute the hardware configuration related to the second system image file.
The above process can be further integrated and divided into two ways:
firstly, the platform path controller 23 receives the trigger signal of the test server 4, further prompts the central processing unit 21 to execute the test program stored in the hard disk module 22, then executes the test program by the central processing unit 21, and transmits a batch file to the microcontroller 32 of the auxiliary unit 3, meanwhile, the central processing unit 21 loads the basic input/output system selected according to the power-on setting through the platform path controller 23, the microcontroller 32 receives, stores and executes the batch file, and after a preset time is timed (after the central processing unit 21 is waited to execute the basic input/output system and execute the power-on self-test program is completed), the microcontroller 32 controls the first relay module 33 to send out a power-on/off analog signal (high/low peak pulse signal) to make the platform path controller 23 perform the power-off program, the microcontroller 32 then switches to the second relay module, so that the platform path controller 23 selects another bios after the next boot. Then, the microcontroller 32 controls the first relay module 33 to send the power on/off analog signal again to enable the platform path controller 23 to notify the central processing unit 21 to start up, and the central processing unit 21 further loads and executes another bios selected by the platform path controller 23.
Secondly, the platform path controller 23 receives the trigger signal of the test server 4, so that the central processing unit 21 executes the test program stored in the hard disk module 22, and further the central processing unit 21 executes the target bios selected by the platform path controller 23. After the target bios is executed and the power-on self-test is completed, the cpu 21 executes the test program again and transmits a batch file to the microcontroller 32 of the auxiliary unit 3, so that the microcontroller 32 stores and executes the batch file, the microcontroller 32 controls the first relay module 33 to send an on/off/analog signal to the platform path controller 23 by executing the batch file, the platform path controller 23 performs a shutdown program according to the on/off analog signal, and then the microcontroller 32 controls the second relay module 34 to send a power-on setting to the platform path controller 23 and execute subsequent related programs.
It should be further explained that the first and second memories 24 and 25 respectively store the first system image file and the second system image file, and also store a first mark code and a second mark code, respectively, so that the cpu 21 of the motherboard 2 can distinguish which system image file is currently executed when executing the system image file, thereby avoiding the repeated execution and wasting of testing time.
In addition, the following detailed description is provided for the platform path controller 23 to select one of the first and second memories 24 and 25: when the Power-on is started, the platform path controller 23 selects a target bios according to a current bios image file selection-related General purpose input/output (GPIO) pin, the cpu 21 starts executing the target bios image file and performs a Power On Self Test (POST) procedure, then sends a notification of starting to perform Power on Self Test to the auxiliary unit 3 through the platform path controller 23, after the auxiliary unit 3 receives the notification of starting to perform Power on Self Test, the microcontroller 32 of the auxiliary unit 3 starts executing its batch file according to the notification, and after the microcontroller 32 waits for a preset time by executing the batch file, an on/off simulation signal simulating a low peak pulse (low pulse) signal is output to the platform path controller 23, the platform path controller 23 receives the on/off analog signal of the low peak pulse signal to perform the shutdown operation. The preset time is greater than or equal to the time required for completing the power-on self-test, then the platform path controller 23 sends out an on/off analog signal which is generated by pressing a physical key through the first relay module 33 after selecting the second relay module 34, and the platform path controller 23 executes the on/off according to the received on/off analog signal and the current system in the on or off state, so that the platform path controller 23 performs the second on of the system according to the received on/off analog signal, selects another basic input/output system according to the switched general input/output pin, and performs the subsequent related procedures.
In the first embodiment of the motherboard testing system of the present invention, the testing server sends the trigger signal to the first network interface port according to the address assigned to the first network interface port, and transmits the trigger signal to the CPU via the platform path controller, so that the CPU executes the testing program in the hard disk module according to the trigger signal, and after executing the first system image file according to the testing program content, then sends the notification signal to the second network interface port via the platform path controller, furthermore, the testing server searches a fixed address of the tool network interface portion by using a dynamic host configuration protocol, the second network interface port can transmit the notification signal to the tool network interface port according to the fixed address, and then transmits the notification signal to the logic operation unit via the tool network interface port, the logic operation unit executes the batch file stored in the memory according to the notification signal, and according to the address allocated to the first network interface port by the test server, the first relay module and the platform path controller control the power supply to operate in the disabled state without outputting the operation power, then the platform path controller selects the second memory by the setting of the second relay module and does not select the first memory, for example, the platform path controller, the central processor can be electrically connected with the second memory through the platform path controller according to the setting of the second relay module, but the internal circuit of the platform path controller disconnects the electrical connection between the central processor and the first memory, and then the logic operation unit controls the first relay module and the platform path controller according to the content of the batch file to switch the power supply to operate in the enabled state and output the power, the central processor executes the second system image file stored in the second memory through the platform path controller and the selected second memory, so that the setting selection state of the central processor and the first and second memories and the switch of the power supply for providing operation power are not required to be controlled through manual operation, and the requirement of saving manpower is met.
Second embodiment:
referring to fig. 6, a second embodiment of the motherboard testing system of the present invention is different from the first embodiment in that: the motherboard 2 includes a system memory 20 electrically connected to the cpu 21, and the system memory 20 stores a batch file having a trigger signal instead of the test server 4 of the first embodiment.
It should be noted that the tool network interface port 31 has a fixed address, and can use Dynamic Host Configuration Protocol (DHCP) to distribute an external address to the second network interface port 29, and further enable the logic operation unit 321 to control the motherboard to be controlled to switch between an enabled state and a disabled state through the first and second relay modules 33, 34 according to the external address.
Referring to fig. 7, the method for testing a motherboard according to the second embodiment includes a step (C) of triggering a test procedure, and a step (D) of executing the test procedure.
The step (C) of the trigger test procedure is different from the step (a) of the trigger signal sending of the first embodiment in that: the CPU 21 reads 20 the lot file with the trigger signal from the system memory.
The steps of executing the test program are as follows: the cpu 21 executes the test program stored in the hard disk module 22 according to the trigger signal.
Referring to fig. 8, the step (D) of executing the testing procedure further includes a primary system image testing sub-step (D3), a notification sending sub-step (D4), a batch file reading sub-step (D5), a waiting sub-step (D6), a control shutdown sub-step (D7), a control switch sub-step (D8), a control startup sub-step (D9), and a backup system image testing sub-step (D10).
The difference between each sub-step of the step (D) of executing the test program and each sub-step of the step (B) of operating the test program in the first embodiment is: the send notification sub-step (D4), the control power off sub-step (D7), the control switch sub-step (D8), and the control power on sub-step (D9), described in further detail below.
The sending notification substep (D4) is: when the CPU 21 executes the first system image file, it then sends a notification signal to the platform path controller 23, and transmits the notification signal to the second network interface port 29 via the platform path controller 23, and then the second network interface port 29 obtains the fixed address of the tool network interface port 31 through searching or user's designation, and transmits the notification signal to the tool network interface port 31 according to the fixed address.
The control shutdown substep (D7) is: the logic operation unit 321 controls the first relay module 33 to switch the power supply 1 to the disabled state for 0.3 seconds according to the external address issued by the tool network interface port 31.
The control switching sub-step (D8) is as follows: the logic operation unit 321 controls the second relay module 34 according to the external address distributed by the tool network interface port 31, so that the platform path controller 23 configures and selects the second memory 25.
The control power-on sub-step (D9) is as follows: the logic operation unit 321 controls the first relay module 33 to switch the power supply 1 to the enabled state after 0.3 seconds according to the external address issued by the tool network interface port 31.
It should be further explained that the first and second memories 24 and 25 respectively store the first system image file and the second system image file, and also store a first mark code and a second mark code, respectively, so that the cpu 21 of the motherboard 2 can distinguish which system image file is currently executed when executing the system image file, thereby avoiding the repeated execution and wasting of testing time.
In the second embodiment of the motherboard testing system of the present invention, the CPU of the motherboard executes the testing program in the hard disk module according to the batch file built in the system memory, and after executing the first system image file according to the content of the testing program, sends the notification signal to the first network interface port via the platform path controller, the first network interface port and the fixed address of the tool network interface port send the notification signal to the tool network interface port, and then the notification signal is sent to the logic operation unit via the tool network interface port, the logic operation unit executes the batch file stored in the memory according to the notification, and sets the address sent to the first network interface port according to the tool network interface port by the dynamic host setting protocol, and further controls the power supply to operate in the disabled state without outputting the operation power through the first relay module, then the second memory is selected by the platform path controller through the control and setting of the second central processor module, the first memory is not selected, then the first relay module is controlled by the logic operation unit according to the content of the batch file, the power supply is controlled by the platform path controller to switch and operate in the enabling state through the platform path controller to output electric energy, when the central processor is restarted, the second system image file stored in the second memory is executed through the platform path controller, therefore, the selection state of the central processor and the first and second memories and the switch of the power supply are not required to be controlled through manual operation, and the requirement of saving manpower is met.
In summary, the present invention provides a method for automatically controlling the power supply on/off by program triggering and setting the platform path controller to automatically switch and select one of the first and second memories, compared with the prior art that uses manual operation, the present invention stores the batch file related to the testing program of the motherboard based on the auxiliary unit itself, when the cpu of the motherboard executes the first system image file according to the testing program, the cpu then sends a notification to the auxiliary unit, the auxiliary unit controls the power supply on/off of the motherboard according to the notification, and controls the switching of the image file setting by the power-on setting, without manual operation and switching, thereby achieving the object of the present invention.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A mainboard test method is executed by a mainboard test system which is used for receiving operation electric energy provided by a power supply and operates in one of a forbidden energy state and an energy state, the mainboard test system comprises a mainboard and an auxiliary unit, the mainboard comprises a central processing unit, a platform path controller which is electrically connected with the central processing unit and the power supply, a first memory which is electrically connected with the platform path controller and stores a first system image file, and a second memory which is electrically connected with the platform path controller and stores a second system image file, the auxiliary unit is electrically connected with the platform path controller, and the mainboard test method is characterized by comprising the following steps:
(B3) when the platform path controller selects the first memory according to the setting of the auxiliary unit, the central processing unit reads and executes the first system image file through the platform path controller;
(B7) the auxiliary unit sends a shutdown signal to the power supply through the platform path controller according to a notification signal sent by the central processing unit, so that the power supply does not provide operation electric energy to the mainboard, and the mainboard is operated in the disabled state;
(B8) the auxiliary unit sets the platform path controller to switch to select the second memory;
(B9) the auxiliary unit sends a starting signal to the power supply through the platform path controller according to the notification signal, and the power supply provides operation electric energy to the mainboard to enable the mainboard to operate in the enabling state; and
(B10) the CPU reads and executes the second system image file through the platform path controller.
2. The motherboard testing method as recited in claim 1, wherein the motherboard testing system further comprises a testing server electrically connected to the motherboard, and the motherboard further comprises a first network interface port electrically connected to the testing server and the platform path controller, and a hard disk module electrically connected to the central processing unit and storing a testing program, wherein the motherboard testing method further comprises a step (a) in which the testing server sends a triggering signal related to the testing program to the first network interface port and transmits the triggering signal to the central processing unit via the platform path controller.
3. The method of claim 2, wherein the auxiliary unit stores a lot, the method further comprising a step (B4) and a step (B5), the step (B4) is that the CPU sends the notification signal to the auxiliary unit according to the test procedure, the step (B5) is that the auxiliary unit executes the lot according to the notification signal, the lot is associated with executing the steps (B7) to (B9).
4. The method for testing a motherboard according to claim 3, wherein the motherboard further comprises a second network interface port electrically connected to the platform path controller for receiving the notification signal from the CPU via the platform path controller, the auxiliary unit is electrically connected to the second network interface port, wherein in the step (B4), the CPU sends the notification signal to the second network interface port via the platform path controller, the batch file further relates to a step (B6), and the auxiliary unit waits a predetermined time before proceeding to the step (B7) when the auxiliary unit receives the notification signal via the second network interface port to execute the batch file.
5. A kind of motherboard test system, in order to receive the operation electric energy that a power supply provides and operate in one of a forbidden energy state and a enable state, characterized by that, the test system of the motherboard includes:
a mainboard, including a central processor, a platform path controller electrically connected with the central processor and the power supply, a first memory electrically connected with the platform path controller and storing a first system image file, and a second memory electrically connected with the platform path controller and storing a second system image file; and
an auxiliary unit electrically connected to the platform path controller,
when the auxiliary unit setting indicates the platform path controller to select the first memory, the CPU reads and executes the first system image file through the platform path controller, the auxiliary unit sends a shutdown signal to the power supply through the platform path controller according to a notification signal sent by the central processing unit, the power supply does not provide operation electric energy to the mainboard, so that the mainboard operates in the disabled state, the auxiliary unit controls and sets the platform path controller to switch and select the second memory according to the notification signal, the auxiliary unit sends a power-on signal to the power supply through the platform path controller according to the notification signal, the power supply provides operating power to the motherboard, the motherboard operates in the enabled state, the CPU reads and executes the second system image file through the platform path controller.
6. The motherboard testing system of claim 5, further comprising a testing server electrically connected to the motherboard, wherein the motherboard further comprises a first network interface port electrically connected to the testing server and the platform path controller, and a hard disk module electrically connected to the central processing unit and storing a testing program, the testing server sending a triggering signal related to the testing program to the first network interface port and transmitting the triggering signal to the central processing unit via the platform path controller.
7. The system as claimed in claim 6, wherein the auxiliary unit stores a batch file associated with the test program, the CPU reads and executes the first system image via the platform path controller, the CPU sends the notification signal to the auxiliary unit according to the test program, the auxiliary unit executes the batch file according to the notification signal, the batch file is associated with the auxiliary unit and sends the shutdown signal to the platform path controller according to the notification signal, the platform path controller controls the power supply not to provide the operating power to the main board to shut down the main board and controls the platform path controller to switch to electrically connect to the second memory, and then sends the startup signal to the platform path controller to control the power supply to provide the operating power to the main board, so as to start the motherboard.
8. The system of claim 7, wherein the auxiliary unit sends the shutdown analog signal to disable the power supply from supplying operating power to the motherboard and waits for a predetermined time.
9. The system as claimed in claim 8, wherein the testing server is configured to send an address to the first network interface port via the dynamic host configuration protocol, and send the trigger signal to the first network interface port according to the address, the first network interface port receives the address and the trigger signal, and the CPU receives the trigger signal via the platform path controller to read and execute the testing procedure.
10. The motherboard testing system as recited in claim 9, further comprising a second network interface port electrically connected to the platform path controller for receiving the notification signal from the CPU via the platform path controller, wherein the auxiliary unit comprises a tool network interface port electrically connected to the second network interface port and having an address, a microcontroller for storing the batch file, a first relay module electrically connected to the microcontroller and the platform path controller, and a second relay module electrically connected to the microcontroller, the CPU transmits the notification signal to the second network interface port via the platform path controller, the second network interface port transmits the notification signal to the tool network interface port according to the address, the microcontroller receives the notification signal via the tool network interface port to execute the batch file, and the first relay module sends one of the shutdown signal and the startup signal to the platform path controller to control the power supply, and the second relay module controls the setting.
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| CN1330302A (en) * | 2000-06-23 | 2002-01-09 | 睿阳科技股份有限公司 | UPS system able to automatically store computer data to hard disk in suspend state |
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