CN111474782A

CN111474782A - Display panel and electronic device

Info

Publication number: CN111474782A
Application number: CN202010356036.9A
Authority: CN
Inventors: 田甜; 彭邦银; 金一坤
Original assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2020-04-29
Filing date: 2020-04-29
Publication date: 2020-07-31
Anticipated expiration: 2040-04-29
Also published as: CN111474782B

Abstract

The application provides a display panel and an electronic device, the display panel comprises a plurality of scanning lines and a plurality of data lines which are positioned in a display area and are mutually vertical, GOA circuit and at least one balanced electrode group, the GOA circuit includes a plurality of cascaded GOA units, the GOA unit includes a plurality of effective GOA units and a plurality of redundant GOA units that arrange in proper order along the second direction, the first output signal line and the scanning line of effective GOA unit are connected, the second output signal line and the reset signal end of preceding stage GOA unit of redundant GOA unit are connected, be provided with a plurality of balanced electrodes in the balanced electrode group, a plurality of balanced electrodes are along arranging with second output signal line vertically direction interval, every balanced electrode corresponds a second output signal line regional setting, balanced electrode and second output signal line set up in different layers and mutual insulation, interconnect between two at least balanced electrodes in the balanced electrode group. The technical problem that the required design space of the second output signal line is large is relieved.

Description

Display panel and electronic device

Technical Field

The application relates to the technical field of display, in particular to a display panel and an electronic device.

Background

With the development of flat panel display technology, the resolution of 8K has become the development trend of panels, in the existing 8K display panel, the GOA unit includes an effective GOA unit and a redundant GOA unit, wherein there is metal led out from a data line above the output signal line of the effective GOA unit, there exists a capacitor between the two, in order to realize the uniform load of the effective GOA unit and the redundant GOA unit, so as to improve the display effect, a plurality of strip metals are usually also arranged above the output signal line of each redundant GOA unit, so that a capacitor is also formed between the output signal line and the strip metal, the strip metals are mutually spaced along the extending direction of the output signal line, and each strip metal is parallel to the output signal line. However, in order to prevent the strip metal from falling out of the output signal line of the redundant GOA unit in the manufacturing process, the width of the output signal line needs to be greater than that of the strip metal, and in order to ensure that the strip metal does not produce peeling in the use process of the display panel, the strip metal itself needs to have a certain width, which requires that the output signal line of the redundant GOA unit has a sufficient width, so that the space requirement is large, and the output signal line does not have enough space to be placed under the condition of compact space, i.e. the design has certain limitation, and cannot meet the requirement of 8K products.

Therefore, the conventional display panel has a technical problem that the design space required for the output signal lines of the redundant GOA units is large, and needs to be improved.

Disclosure of Invention

The embodiment of the application provides a display panel and electronic equipment, which are used for relieving the technical problem that the design space required by an output signal line of a redundant GOA unit in the existing display panel is large.

The application provides a display panel, including:

the scanning lines are positioned in the display area, extend along a first direction, and are arranged at intervals along a second direction, and the first direction is vertical to the second direction;

the data lines are positioned in the display area, are vertical to the scanning lines and are arranged at intervals along the first direction, and are arranged on different layers and are insulated from the scanning lines;

the GOA circuit comprises a plurality of cascaded GOA units, each GOA unit comprises a plurality of effective GOA units and a plurality of redundant GOA units, the effective GOA units and the redundant GOA units are sequentially arranged along the second direction, a first output signal line of each effective GOA unit is connected with the scanning line, and a second output signal line of each redundant GOA unit is connected with a reset signal end of a previous GOA unit;

the balance electrode group is internally provided with a plurality of balance electrodes which are arranged at intervals along the direction vertical to the second output signal line, each balance electrode is arranged corresponding to the area where one second output signal line is located, the balance electrodes and the second output signal lines are arranged on different layers and are mutually insulated, and at least two balance electrodes in the balance electrode group are mutually connected.

In the display panel of the present application, all the balance electrodes in the balance electrode group are connected to each other.

In the display panel of the present application, the balance electrodes connected to each other are all adjacent to each other in the balance electrode group.

In the display panel of the present application, the balance electrodes connected to each other in the balance electrode group are not completely adjacent.

In the display panel of the application, the balance electrodes which are mutually connected in the balance electrode group are connected through a connecting part, and the width of the connecting part is less than or equal to the length of the balance electrode.

In the display panel of the present application, the display panel includes at least two balanced electrode groups, and each balanced electrode group is arranged at intervals along an extending direction of the second output signal line.

In the display panel of the present application, the connection method of the balance electrodes between the balance electrode groups is the same.

In the display panel of the present application, the second output signal line is disposed on the first metal layer, and the balance electrode is disposed on the second metal layer or the source drain layer.

In the display panel of the present application, the balance electrode material is at least one of copper and aluminum.

The application also provides an electronic device, which comprises a display panel and a driving chip, wherein the display panel is any one of the display panels.

Has the advantages that: the application provides a display panel and an electronic device, wherein the display panel comprises a plurality of scanning lines, a plurality of data lines, a GOA circuit and at least one balance electrode group; the scanning lines are positioned in the display area, extend along a first direction, and are arranged at intervals along a second direction, and the first direction is vertical to the second direction; the data lines are positioned in the display area, are vertical to the scanning lines and are arranged at intervals along the first direction, and the data lines and the scanning lines are arranged on different layers and are insulated from each other; the GOA circuit comprises a plurality of cascaded GOA units, each GOA unit comprises a plurality of effective GOA units and a plurality of redundant GOA units, the effective GOA units and the redundant GOA units are sequentially arranged along the second direction, a first output signal line of each effective GOA unit is connected with the scanning line, and a second output signal line of each redundant GOA unit is connected with a reset signal end of a previous GOA unit; the balance electrode group is internally provided with a plurality of balance electrodes which are arranged at intervals along the direction vertical to the second output signal lines, each balance electrode is arranged corresponding to the area where one second output signal line is located, the balance electrodes and the second output signal lines are arranged on different layers and are insulated from each other, and at least two balance electrodes in the balance electrode group are connected with each other. This application is through setting up at least one balanced electrode group, balanced electrode forms the electric capacity with second output signal line among the balanced electrode group, make the load of redundant GOA unit and effective GOA unit the same, and connect at least two balanced electrodes, make interconnect's balanced electrode be difficult for dropping from second output signal line top, the width of corresponding second output signal line can reduce, has alleviated the great technical problem in the required design space of second output signal line.

Drawings

The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.

Fig. 1 is a schematic plan view of a display panel according to an embodiment of the present disclosure.

Fig. 2 is a schematic view of a first structure of a balance electrode set in a display panel according to an embodiment of the present disclosure.

Fig. 3 is a schematic diagram of a second structure of a balance electrode set in a display panel according to an embodiment of the present disclosure.

Fig. 4 is a schematic structural diagram of a third structure of a balance electrode set in a display panel according to an embodiment of the present disclosure.

Fig. 5 is a schematic diagram of a fourth structure of a balanced electrode set in a display panel according to an embodiment of the present disclosure.

Fig. 6 is a schematic diagram of a fifth structure of a balanced electrode set in a display panel according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.

As shown in fig. 1, the present application provides a display panel, which includes a plurality of scan lines, a plurality of data lines, a GOA circuit, and at least one balanced electrode set (not shown);

a plurality of scan lines are located in the display area 100, the scan lines extend along a first direction, the scan lines are spaced along a second direction, and the first direction is perpendicular to the second direction;

a plurality of data lines are positioned in the display area 100, the data lines are perpendicular to the scan lines, the data lines are arranged at intervals along a first direction, and the data lines and the scan lines are arranged on different layers and are insulated from each other;

the GOA circuit comprises a plurality of cascaded GOA units, each GOA unit comprises a plurality of effective GOA units and a plurality of redundant GOA units, the effective GOA units and the redundant GOA units are sequentially arranged along a second direction, a first output signal line 10 of each effective GOA unit is connected with a scanning line, and a second output signal line 20 of each redundant GOA unit is connected with a reset signal end of a previous GOA unit;

a plurality of balance electrodes are arranged in the balance electrode group, the balance electrodes are arranged at intervals along a direction perpendicular to the second output signal lines 20, each balance electrode is arranged corresponding to the region 200 where one second output signal line is located, the balance electrodes and the second output signal lines 20 are arranged on different layers and are insulated from each other, and at least two balance electrodes in the balance electrode group are connected with each other.

The display panel includes a display area 100 and a non-display area located around the display area 100, wherein the non-display area includes a signal line setting area and a Gate Driver on Array (GOA) circuit setting area. A plurality of sub-pixels (not shown) are disposed in the display area 100 in an array, each sub-pixel is driven by a pixel driving circuit in the display area 100, and a scanning signal and a data signal of a driving transistor in the pixel driving circuit are respectively provided by a scanning line and a data line.

In this application, the first direction is the horizontal direction, and the second direction is vertical direction, and each scanning line all extends along the horizontal direction promptly, and many scanning lines set up along vertical direction interval, and each data line all extends along vertical direction, and many data lines set up along the horizontal direction interval. Fig. 1 illustrates a display panel according to the present application, taking an 8K product as an example. The resolution of the display panel in the 8K product is 7680x4320, and therefore includes 7680 data lines and 4320 scan lines, and in fig. 1, the 1 st to 4320 th scan lines are sequentially denoted by G1 to G4320, and the 1 st to 7680 th data lines are sequentially denoted by D1 to D7680. In the display area 100, in the pixel driving circuits of the sub-pixels in the same row, the gates of the driving transistors are connected to the same gate line, and in the pixel driving circuits of the sub-pixels in the same column, the sources or drains of the driving transistors are connected to the same data line.

The signal line setting area is provided with a plurality of clock signal lines CK 1-CK 12, the GOA circuit setting area is provided with a GOA circuit, the clock signal lines provide clock signals for the GOA circuit, the GOA circuit outputs gate driving signals and provides the gate driving signals for the scanning lines.

The GOA circuit comprises a plurality of cascaded GOA units, and the GOA units sequentially comprise a plurality of effective GOA units and a plurality of redundant GOA units from top to bottom, wherein the effective GOA units are represented by 'GOA units', and the redundant GOA units are represented by 'Dummy GOA units'. In the 8K product, the number of valid GOA units is 4320, denoted in turn by GOA Unit 1 to GOA Unit 4320, and the number of redundant GOA units is 6, denoted in turn by Dummy GOA Unit 1 to Dummy GOA Unit 6.

The first driving signal lines of the effective GOA units are sequentially connected with the scanning lines and are in one-to-one correspondence, namely the number of the effective units is consistent with that of the scanning lines, and the second output signal lines of the redundant GOA units are not connected with the scanning lines but provide reset signals for the previous GOA units. In the display panel of the present application, every 12 effective GOA units are in one group, the clock signal input ends of 12 effective GOA units are sequentially connected to 12 clock signal lines and in one-to-one correspondence, and for the whole GOA circuit, every 6 GOA units are in one group, and a reset signal is sequentially provided for 6 GOA units in the previous group, so that, for the last 6 levels of effective GOA units, i.e., GOA units 4315 to 4320, it is necessary to set 6 redundant GOA units, i.e., Dummy GOA units 1 to Dummy GOA units 6, to reset them, and thus a preceding GOA Unit refers to one or more effective GOA units before the 6 redundant GOA units.

It should be noted that fig. 1 is only one example of a display panel, and the number and connection manner of the clock signal lines, the effective GOA units and the redundant GOA units are different according to the model, for example, the reset may be performed by not using 6 units as a group, but performing reset at two, three or other number of stages, and the number of the redundant GOA units is correspondingly reduced.

The display panel can be a liquid crystal display panel or an O L ED display panel, the display panel comprises a substrate and a driving circuit layer from bottom to top, the driving circuit layer comprises an active layer, a first grid insulation layer, a first metal layer, a second grid insulation layer, a second metal layer, an interlayer insulation layer and a source drain electrode layer which are arranged in a stacked mode, the first metal layer is patterned to form a grid electrode and a scanning line of each thin film transistor, the source drain electrode layer is patterned to form a source electrode, a drain electrode and a data line of each thin film transistor, in the display area 100, the scanning line and the data line are arranged on different layers and are insulated from each other, and the scanning line and the data line are perpendicular to each other, so that in an area where projections of the scanning line and the drain electrode on the substrate are overlapped, a capacitor can be formed before the scanning line and the data line are perpendicular to each other, and.

In order to keep the load on the second output signal line 20 of the redundant GOA unit consistent with the load on the first output signal line 10 of the effective GOA unit, so as to improve the display effect, a capacitor needs to be formed in the area 200 where the second output signal line 20 is located. In the display panel of the present application, at least one balance electrode group is provided, a plurality of balance electrodes are provided in each balance electrode group, the plurality of balance electrodes are arranged at intervals along a direction perpendicular to the second output signal lines 20, each balance electrode is provided corresponding to a region 200 where one second output signal line is located, the balance electrodes and the second output signal lines 20 are provided in different layers and are insulated from each other, that is, in the same balance electrode group, one balance electrode is provided corresponding to each second output signal line 20, and thus a capacitance is also formed between each balance electrode and its corresponding second output signal line 20. When the display panel works, the driving chip provides a driving signal for the balance electrodes in the balance electrode group, and the capacitance between the balance electrodes and the second output signal line 20 can be controlled by adjusting the material and the size of the balance electrodes and the size of the driving signal, so that the capacitance at the overlapped part of the data line and the scanning line is consistent, and further the consistency with the load on the first output signal line 10 is realized.

The number of the balance electrode groups is at least one, when only one balance electrode group is arranged, the capacitance between each second output signal line 20 and one balance electrode is equal to the capacitance between each first output signal line 10 and all data lines by adjusting the size of the driving signal, when a plurality of balance electrode groups are arranged, the capacitance between each second output signal line 20 and a plurality of balance electrodes is equal to the capacitance between each first output signal line 10 and all data lines by adjusting the size of the driving signal, so that the load on the second output signal line 20 is kept consistent with the load on the first output signal line 10.

The display panel comprises at least one balance electrode group, and at least two balance electrodes in the balance electrode group are mutually connected. The number of the balance electrode groups may be one or more. In balanced electrode group, the whole that interconnect's balanced electrode is constituteed, and the width is for single balanced electrode greatly increased among the prior art, consequently is difficult for producing the risk of peeling, and is difficult for dropping from second output signal line 20 top in the process, and the width of corresponding second output signal line can reduce, has alleviated the great technical problem of the required design space of second output signal line.

In one embodiment, the interconnected balance electrodes 30 in the balance electrode set are all adjacent.

Fig. 2 is a schematic view of a first structure of a balanced electrode set in a display panel according to an embodiment of the present disclosure. In this embodiment, the number of the balanced electrode group is one, and taking 6 redundant GOA units as an example, the display panel includes 6 second output signal lines 20, the balanced electrode group also includes 6 balanced electrodes 30, and at least two balanced electrodes 30 of the 6 balanced electrodes 30 are connected to each other, so that various connection manners are possible.

Taking fig. 2 as an example, the first balance electrode 30 and the second balance electrode 30 are adjacent to each other from top to bottom, and are connected to each other through a connection portion 40, the third to six balance electrodes 30 are connected to each other through three connection portions 40, and every two balance electrodes 30 are also adjacent to each other, and in addition, the number of the balance electrodes 30 connected to each other may be selected according to the requirement, for example, every two, every three or more adjacent balance electrodes 20 are connected as a group, and the number of the balance electrodes 30 in each group may also be different. In addition, the width D1 of the balance electrode 30 is greater than or equal to the width D2 of the second output signal line 20, because the first balance electrode 30 and the second balance electrode 30 are connected to each other through a connecting portion 40, and the overall width of the three components is greater than the width D2 of any one of the second output signal lines 20, therefore, the overall width of the three components can be greater than the minimum width value without producing peeling, and at this time, the width D2 of the second output signal line 20 can be smaller, so that the design can meet the narrower width of the second output signal line 20, and no excessive space is required to be left in the display panel for placing the second output signal line 20, thereby realizing the narrow-frame design of the display panel.

During the manufacturing, the first balance electrode 30, the second balance electrode 30 and the connecting portion 40 therebetween can be directly manufactured as a whole, that is, the material of the connecting portion 40 is the same as that of the balance electrode 30, and the manufacturing method is simple. In addition, each balance electrode 30 may be manufactured first, and then the connection portion 40 may be manufactured on the balance electrode 30, the connection portion 40 may cover a partial region of each balance electrode 30, and at this time, the material of the connection portion 40 may be the same as or different from that of the balance electrode 30, and this manufacturing method does not need to change the mask used for the existing balance electrode, and only needs to add one mask for manufacturing the connection portion 40, so that it is also simpler.

The second output signal line 20 and the balance electrode 30 are insulated from each other, and the balance electrode 30 is disposed on an upper film layer of the second output signal line 20. The second output signal line 20 is disposed on the first metal layer, the balance electrode 30 may be disposed on the source/drain layer, i.e., on the same layer as the data line, and the balance electrode 30 may also be disposed on the second metal layer, which is used to form a plate of the storage capacitor, so that the space is more abundant. The material of the balance electrode 30 may be the same as that of the second metal layer or the source/drain layer, and may be at least one of copper and aluminum, or other materials commonly used for the second metal layer or the source/drain layer.

Fig. 3 is a schematic diagram of a second structure of a balanced electrode set in a display panel according to an embodiment of the present disclosure. Different from fig. 2, all the balance electrodes 30 in the balance electrode group of the present embodiment are connected to each other, that is, each balance electrode group is made of a whole metal, at this time, the balance electrodes 30 do not risk peeling, and are less prone to drop, and the width of each second output signal line 20 can be made smaller, so that the required design space for the second output signal lines 20 is also smaller, and a narrow frame is easier to implement.

In the embodiment of fig. 2 and 3, the width of the connecting portion 40 is equal to the length of the balance electrodes 30, that is, the whole body formed by each balance electrode 30 and the connecting portion 40 is a whole metal, so that the formed pattern is simple in manufacturing, the requirement on process precision is low, and the production difficulty is reduced.

As shown in fig. 4, a third structural diagram of the balanced electrode group in the display panel according to the embodiment of the present disclosure is different from that in fig. 3 in that the width L2 of the connecting portion 40 in the embodiment is smaller than the length L1 of the balanced electrode 30, at this time, the connecting portion 40 also can prevent the balanced electrode 30 from falling off from above the second output signal line 20, and the connecting portion 40 uses less material, thereby saving cost.

In one embodiment, the balance electrodes of the balance electrode group are not completely adjacent to each other.

As shown in fig. 5, for a fourth structural schematic diagram of a balance electrode group in a display panel provided in the embodiment of the present application, in fig. 5, from top to bottom, the first, second, and fourth balance electrodes 40 are not completely adjacent, the three are connected to each other by two connecting portions 40, the third, fifth, and sixth balance electrodes 30 are not completely adjacent, the three are also connected to each other by two connecting portions 40, in addition, the number of the balance electrodes 30 connected to each other may be selected according to needs, for example, every two, every three, or more incompletely adjacent balance electrodes 20 are connected as a group, and the number of the balance electrodes 30 in each group may also be different.

The above embodiments are all described with the display panel including one balanced electrode group, and in one embodiment, the display panel includes at least two balanced electrode groups, each of which is arranged at intervals along the extending direction of the second output signal line 20, wherein at least one of the balanced electrode groups is a balanced electrode group.

Fig. 6 is a schematic diagram of a fifth structure of a balanced electrode set in a display panel according to an embodiment of the present application. The present embodiment includes 3 balanced electrode sets, and the 3 balanced electrode sets are arranged at intervals along the horizontal direction.

In one embodiment, the balance electrodes 30 are connected in the same manner between the balance electrode groups, all the balance electrodes 30 in each balance electrode group are connected together as shown in fig. 3 or 4, or are connected in groups of two, three or other numbers as shown in fig. 2, and the width L2 of the connecting portion 40 is also the same between the balance electrode groups, i.e., the shapes and positions of the components in each balance electrode group are the same, so that the process is simple in manufacturing.

In an embodiment, the connection modes of the balance electrodes 30 among the balance electrode groups are different, and when the pitches of the second output signal lines 20 are different at different places of the display panel, different connection modes are adopted in the balance electrode groups for different pitches, so that the design mode is flexible, and the connection modes of the balance electrodes 30 in the balance electrode groups can be reasonably designed according to the actual situation of the second output signal lines 20 in the display panel.

According to the embodiment, the capacitor is formed by the balance electrodes and the second output signal line in the balance electrode group by arranging the at least one balance electrode group, so that the loads of the redundant GOA unit and the effective GOA unit are the same, the at least two balance electrodes are connected, the balance electrodes connected with each other are not prone to falling off from the upper portion of the second output signal line, the width of the corresponding second output signal line can be reduced, and the technical problem that the required design space of the second output signal line is large is solved.

The electronic device can be an 8K product with the resolution of 7680X4320, wherein the display panel can be a liquid crystal display panel or an O L ED display panel, a timing controller is arranged in the driving chip, and clock signals in each clock signal line in the display panel are provided by the timing controller.

According to the above embodiment:

the application provides a display panel and an electronic device, wherein the display panel comprises a plurality of scanning lines, a plurality of data lines, a GOA circuit and at least one balance electrode group; the scanning lines are positioned in the display area, extend along a first direction, and are arranged at intervals along a second direction, and the first direction is vertical to the second direction; the data lines are arranged in the display area, are vertical to the scanning lines and are arranged at intervals along a first direction, and the data lines and the scanning lines are arranged on different layers and are insulated from each other; the GOA circuit comprises a plurality of cascaded GOA units, each GOA unit comprises a plurality of effective GOA units and a plurality of redundant GOA units, the effective GOA units and the redundant GOA units are sequentially arranged along a second direction, a first output signal line of each effective GOA unit is connected with a scanning line, and a second output signal line of each redundant GOA unit is connected with a reset signal end of a previous GOA unit; a plurality of balance electrodes are arranged in the balance electrode group, the balance electrodes are arranged at intervals along the direction vertical to the second output signal lines, each balance electrode is arranged corresponding to the area where one second output signal line is located, the balance electrodes and the second output signal lines are arranged on different layers and are mutually insulated, and at least two balance electrodes in the balance electrode group are mutually connected. This application is through setting up at least one balanced electrode group, balanced electrode forms the electric capacity with second output signal line among the balanced electrode group, make the load of redundant GOA unit and effective GOA unit the same, and connect at least two balanced electrodes, make interconnect's balanced electrode be difficult for dropping from second output signal line top, the width of corresponding second output signal line can reduce, has alleviated the great technical problem in the required design space of second output signal line.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The display panel and the electronic device provided by the embodiment of the present application are described in detail above, and a specific example is applied in the description to explain the principle and the implementation of the present application, and the description of the embodiment is only used to help understanding the technical solution and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A display panel, comprising:

2. The display panel of claim 1, wherein all of the balance electrodes in the balance electrode group are connected to each other.

3. The display panel of claim 1, wherein the balance electrode groups are such that the balance electrodes connected to each other are adjacent to each other.

4. The display panel of claim 1, wherein the balance electrode groups are such that the interconnected balance electrodes are not completely adjacent.

5. The display panel according to claim 1, wherein the balance electrodes connected to each other in the balance electrode group are connected to each other by a connection portion having a width smaller than or equal to a length of the balance electrode.

6. The display panel according to claim 1, wherein the display panel includes at least two balanced electrode groups, each of which is arranged at intervals along an extending direction of the second output signal line.

7. The display panel according to claim 6, wherein the balance electrodes are connected in the same manner between the balance electrode groups.

8. The display panel according to claim 1, wherein the second output signal line is provided in a first metal layer, and the balance electrode is provided in a second metal layer or a source drain layer.

9. The display panel of claim 1, wherein the balancing electrode material is at least one of copper and aluminum.

10. An electronic device comprising a display panel according to any one of claims 1 to 9 and a driver chip.