CN111463128A - Dry etching method and polycrystalline silicon thin film transistor - Google Patents

Dry etching method and polycrystalline silicon thin film transistor Download PDF

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CN111463128A
CN111463128A CN202010288223.8A CN202010288223A CN111463128A CN 111463128 A CN111463128 A CN 111463128A CN 202010288223 A CN202010288223 A CN 202010288223A CN 111463128 A CN111463128 A CN 111463128A
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dry etching
reaction chamber
oxygen
etching gas
introducing
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张涛
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TCL China Star Optoelectronics Technology Co Ltd
TCL Huaxing Photoelectric Technology Co Ltd
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TCL Huaxing Photoelectric Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1604—Amorphous materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

The application discloses a dry etching method and a polycrystalline silicon thin film transistor, wherein the method comprises the following steps: providing a substrate, preparing a semiconductor layer and a light resistor on the substrate, and exposing and developing the light resistor; placing the substrate, the semiconductor layer and the light resistance in a reaction chamber, introducing first etching gas into the reaction chamber, and performing first dry etching on the semiconductor layer; introducing oxygen into the reaction chamber; after reacting for a period of time, pumping away oxygen and the first etching gas; and introducing second etching gas into the reaction chamber, and performing second dry etching on the semiconductor layer to form an active layer. Because the activity of the oxygen is larger, oxygen is introduced in two adjacent etching steps, part of accumulated static electricity can be taken away, the environment in the reaction chamber is improved, and the electrostatic discharge phenomenon generated in the etching process is improved.

Description

Dry etching method and polycrystalline silicon thin film transistor
Technical Field
The present disclosure relates to semiconductor manufacturing processes, and particularly to a dry etching method and a polysilicon thin film transistor.
Background
At present, dry etching is widely applied to the preparation of low-temperature polycrystalline silicon thin film transistors, and in the process of etching gas in plasma etching, due to the non-uniformity of plasma distribution in a reaction cavity, a large amount of charges are accumulated in a local area of a substrate, so that electrostatic discharge is caused, the substrate is easy to break down due to high electrostatic discharge voltage, and the polycrystalline silicon thin film transistors are permanently damaged.
Therefore, in the existing substrate dry etching process, the problems of substrate static accumulation and easy generation of static discharge exist, and the problems need to be solved.
Disclosure of Invention
The embodiment of the application provides a dry etching method and a polycrystalline silicon thin film transistor, which can effectively relieve the electrostatic discharge phenomenon generated during the dry etching of the polycrystalline silicon thin film transistor.
The embodiment of the application provides a dry etching method, which comprises the following steps:
providing a substrate, preparing a semiconductor layer and a light resistance on the substrate, and exposing and developing the light resistance;
placing the substrate, the semiconductor layer and the light resistor in a reaction chamber, introducing a first etching gas into the reaction chamber, and performing first dry etching on the semiconductor layer;
introducing oxygen into the reaction chamber;
pumping away the oxygen and the first etching gas;
and introducing a second etching gas into the reaction chamber, and performing secondary dry etching on the semiconductor layer to form an active layer.
In some embodiments, the first etching gas is the same as the second etching gas.
In some embodiments, the first etching gas is different from the second etching gas.
In some embodiments, the first etching gas is a mixture of nitrogen trifluoride and oxygen.
In some embodiments, the step of introducing oxygen into the reaction chamber comprises: setting the source power and the bias voltage to be zero, and introducing oxygen into the reaction chamber within preset time according to preset pressure and preset flow rate.
In some embodiments, the predetermined pressure is 0 to 5 torr.
In some embodiments, the predetermined flow rate is 6000 to 10000 milliliters per minute.
In some embodiments, the preset time is 4 to 12 seconds.
In some embodiments, the dry etching method comprises at least two dry etching steps, and oxygen is introduced between any two adjacent dry etching steps.
The application also provides a polycrystalline silicon thin film transistor which is prepared by adopting any one of the methods.
The application discloses a dry etching device and a dry etching method thereof, wherein the dry etching method comprises the following steps: providing a substrate to prepare a semiconductor layer and a light resistance on the substrate, and carrying out dry etching steps at least twice on the semiconductor layer after exposing and developing the light resistance, wherein protective gas is introduced between any two adjacent dry etching steps, and the active gas is oxygen. Because the activity of oxygen is larger, part of accumulated static electricity can be taken away in the process of introducing, reacting and pumping away the oxygen, the environment in the reacting cavity is improved, and the static electricity discharge phenomenon generated in the etching process is further improved.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic flow chart of an etching method according to an embodiment of the present application.
Fig. 2 is a schematic structural diagram of an etching apparatus provided in an embodiment of the present application.
Fig. 3 is a schematic structural diagram of the first polysilicon thin film transistor prepared by the etching method of fig. 1.
Fig. 4 is a schematic structural diagram of a second polysilicon thin film transistor prepared by the etching method of fig. 1.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
Specifically, referring to fig. 1 to 4, an embodiment of the present invention provides a dry etching method.
As shown in fig. 1, the dry etching method comprises the following steps:
s1, providing a substrate, preparing a semiconductor layer and a photoresist on the substrate, exposing and developing the photoresist.
S2, placing the substrate, the semiconductor layer and the light resistance in a reaction chamber, and introducing first etching gas into the reaction chamber to perform first dry etching on the semiconductor layer.
And S3, introducing oxygen into the reaction chamber.
And S4, pumping away the oxygen and the first etching gas.
And S5, introducing a second etching gas into the reaction chamber, and performing second dry etching on the semiconductor layer to form an active layer.
In S1, a substrate, which may be a glass substrate, is provided. Firstly, preparing an amorphous silicon layer on a substrate, wherein the amorphous silicon layer is of a whole-surface structure. And carrying out annealing treatment on the amorphous silicon layer to form a polycrystalline silicon layer, wherein the polycrystalline silicon layer is a semiconductor layer. And covering a photoresist on the semiconductor layer, developing and exposing the photoresist to form a photoresist pattern, wherein one part of the semiconductor layer is covered by the photoresist hollowed-out layer, and the other part of the semiconductor layer is covered by the photoresist non-hollowed-out layer.
In S2, the substrate is placed in a reaction chamber, the reaction chamber is in a sealed vacuum environment, a vacuum gauge detects the environment of the reaction chamber, and a gas valve is activated to start introducing the first etching gas. Setting the source power and the bias voltage of the etching device to be zero, and introducing first etching gas into the reaction chamber within preset time according to preset pressure and preset flow rate. The upper electrode and the lower electrode of the reaction cavity are electrified to ionize the first etching gas to form plasma gas, the plasma gas comprises halogen elements such as chlorine and fluorine, and the halogen elements are easy to react with a silicon-containing compound, so that dry etching is realized by the reaction of the halogen elements and the silicon elements. And for the reaction chamber, the upper electrode and the lower electrode are electrified with voltage, and the voltage of the upper electrode contact is between six kilovolts and twenty thousand volts. And for the reaction chamber, voltages are applied to the upper electrode and the lower electrode, the voltage of the upper electrode contact is between six kilovolts and twenty thousand volts, and the voltage of the lower electrode contact is between 0 and five kilovolts. In step S2, the first etching gas removes the raised portions of the amorphous silicon layer not covered by the photoresist after ionization.
In some embodiments, the first etching gas comprises a mixture of nitrogen fluoride and oxygen in a ratio of seven to three.
In some embodiments, the first etching gas comprises a mixture of sulfur hexafluoride and oxygen.
In some embodiments, the first etching gas comprises a mixture of chlorine and oxygen.
In some embodiments, the first etching gas comprises a mixture of carbon tetrafluoride and oxygen.
In some embodiments, the first etching gas may be introduced into the reaction chamber before being introduced, or may be exhausted by using an inert gas, such as helium.
In S3, after the first etching is completed, oxygen is introduced, and the oxygen carries away a part of the first etching gas that has not been completed. Meanwhile, the oxygen is ionized in the reaction cavity to form ozone and oxygen ions with higher activity. Ozone, oxygen ions and residual electrons and ions in the chamber react, and generated compounds are discharged.
In some embodiments, the step of introducing oxygen into the reaction chamber comprises: setting the source power and the bias voltage to be zero, and introducing oxygen into the reaction chamber within a preset time according to a preset pressure and a preset flow rate, wherein the preset pressure is 0 to 5 torr, the preset flow rate is 6000 to 10000 milliliters per minute, and the preset time is 4 to 12 seconds.
In S4, the exhaust device performs slow exhaust, closes the shut-off valve to protect the turbomolecular pump, the pressure is below 50 torr, the pressure gauge is closed, a delay time is set, and the high pressure vacuum pressure gauge starts measuring pressure. And when the pressure reaches below 0 torr, sequentially opening the stop valves to prepare for introducing second etching gas.
And in S5, introducing a second etching gas, electrifying the upper electrode and the lower electrode of the reaction cavity to ionize the second etching gas to form plasma gas, wherein the plasma gas comprises halogen elements such as chlorine, fluorine and the like. And setting the source power and the bias voltage of the etching device to be zero, and introducing second etching gas into the reaction chamber within preset time according to preset pressure and preset flow rate. The electrode is energized to a voltage between 5 kilovolts and 20 kilovolts. And completely removing the part of the polycrystalline silicon layer which is not covered by the photoresist pattern by using the second etching gas so as to form a polycrystalline silicon pattern and form an active layer of the thin film transistor.
In some embodiments, the second etching gas may be the same as or different from the first etching gas, and the second etching gas includes one of chlorine, nitrogen trifluoride and sulfur hexafluoride.
In S5, the polysilicon layer is etched to form a plurality of polysilicon patterns, in some embodiments, the dry etching is performed more than twice, and oxygen is introduced between any two adjacent dry etches.
The application discloses a dry etching method and a polycrystalline silicon thin film transistor, wherein the method comprises the following steps: providing a substrate, preparing a semiconductor layer and a light resistor on the substrate, and exposing and developing the light resistor; placing the substrate, the semiconductor layer and the light resistance in a reaction chamber, introducing first etching gas into the reaction chamber, and performing first dry etching on the semiconductor layer; introducing oxygen into the reaction chamber; after reacting for a period of time, pumping away oxygen and the first etching gas; and introducing second etching gas into the reaction chamber, and performing second dry etching on the semiconductor layer to form an active layer. Because the activity of the oxygen is larger, oxygen is introduced in two adjacent etching steps, part of accumulated static electricity can be taken away, the environment in the reaction chamber is improved, and the electrostatic discharge phenomenon generated in the etching process is improved.
As shown in FIG. 2, the present invention provides a dry etching apparatus using any one of the dry etching methods described above. The dry etching device is used for carrying out a dry etching process on a film layer structure of the polycrystalline silicon thin film transistor.
In the embodiment of the present application, the dry etching apparatus includes a reaction chamber 10, at least one exhaust assembly 20, and at least one load cell assembly 30. The reaction cavity 10 is used for etching the polycrystalline silicon thin film transistor to be etched; the exhaust assembly 20 is connected to the reaction chamber 10 for exhausting gas and providing a vacuum environment; the pressure measuring assembly 30 is installed on the reaction chamber 10, and is used for monitoring the pressure in the reaction chamber 10 in real time, so as to judge whether the process conditions in the reaction chamber 10 reach the standard in real time.
The reaction chamber 10 includes a chamber body 11, an upper electrode 12, and a lower electrode 13. The substrate to be etched is placed in the cavity 11 at the position to be etched. The cavity 11 is connected with an upper electrode 12 and a lower electrode 13, and the upper electrode and the lower electrode are respectively connected with voltage and used for ionizing etching gas. In some embodiments, the voltage of the upper electrode 12 is between five thousand and twenty thousand volts for ionizing the etching gas, and the voltage of the lower electrode 13 is between zero and five thousand volts for adsorbing the gas.
The load cell assembly 30 includes a vacuum gauge 31 connected to the reaction chamber 10 through a conduit, and a gas valve 32 disposed on the conduit for controlling opening and closing of a pipe between the vacuum gauge 31 and the reaction chamber 10. When the gas valve 32 controls the pipeline to be conducted, the vacuum gauge 31 is communicated with the reaction cavity 10, so that the pressure in the reaction cavity 10 can be monitored in real time.
In some embodiments, the pressure measuring assembly 30 is provided with two pressure measuring assemblies 30, and the detection ranges of the vacuums 31 of the two pressure measuring assemblies 30 are different, wherein one of the vacuums 31 is a high-pressure vacuum manometer, the detection range of the high-pressure vacuum manometer is 0-0.1 torr, the other one of the vacuums 31 is a common manometer, and the detection range of the manometer is 0-2 torr. The reaction can be better controlled depending on the range of the manometer measurement.
In some embodiments, the gas valve 32 is used to control the connection and disconnection of the pipeline between the vacuum gauge 31 and the reaction chamber 10, and is opened only in a low pressure state to connect the pipeline between the vacuum gauge 31 and the reaction chamber 10; when the pressure in the reaction chamber 10 increases, for example, when the pressure in the reaction chamber 10 reaches the atmospheric pressure, the gas valve 32 will be closed to cut off the pipeline between the vacuum gauge 31 and the reaction chamber 10, and the vacuum gauge 31 is effectively protected. In the present invention, the type and structure of the gas valve 32 are not specifically limited, and will not be described herein.
In one embodiment of the present invention, the reaction chamber 10 further has a plurality of exhaust holes (not shown), and each exhaust assembly 20 is connected to the reaction chamber 10 through one exhaust hole. Each of the exhaust assemblies 20 includes at least one vacuum pump 21 connected to a corresponding exhaust port via a pipe (not shown) for pumping the process products in the reaction chamber 10 out of the reaction chamber 10.
In an embodiment of the present invention, each of the exhaust assemblies 20 further includes at least one valve 22, and each of the valves 22 is disposed on a pipeline between a vacuum pump 21 and the reaction chamber 10 for controlling the connection and disconnection of a channel between the vacuum pump 21 and the reaction chamber 10. It is understood that the valve 22 may be any one of a pneumatic valve, an electric valve, or a mechanical valve, and is not particularly limited in the present invention.
The working flow of the dry etching device is as follows:
s201: after the reaction chamber 10 is sealed, the exhaust assembly 20 exhausts the reaction chamber to a vacuum state.
S202: after the vacuum gauge 31 detects that the reaction chamber 10 reaches a vacuum condition, opening the gas valve 32, and introducing a first etching gas into the reaction chamber 10, wherein the step of introducing the first etching gas into the reaction chamber comprises: setting the source power and the bias voltage to be zero, and introducing oxygen into the reaction chamber within preset time according to preset pressure and preset flow rate.
S203: the upper electrode 12 and the lower electrode 13 in the reaction chamber 10 are electrified, so that the first etching gas in the chamber 10 forms a plasma state, and the first etching gas in the plasma state is one or more of ions, active atomic groups or molecular free radicals. And the ionized first etching gas carries out ion bombardment and chemical reaction on the semiconductor layer to realize dry etching process operation.
S204: after the first dry etching process is completed, introducing oxygen into the reaction chamber, wherein the step of introducing oxygen into the reaction chamber 10 comprises: setting the source power and the bias voltage to be zero, and introducing oxygen into the reaction chamber within preset time according to preset pressure and preset flow rate.
S205: after the oxygen is introduced for a predetermined time, the exhaust assembly 20 exhausts the first etching gas and the oxygen from the chamber 12. The exhaust assembly opens the exhaust valve 21, and the vacuum pump 22 is started to evacuate the reaction chamber to a vacuum state.
S206, after the vacuum gauge 31 detects that the reaction chamber 10 reaches a vacuum condition, opening the gas valve 32, and introducing a second etching gas into the reaction chamber 10, wherein the step of introducing the second etching gas into the reaction chamber comprises the following steps: setting the source power and the bias voltage to be zero, and introducing oxygen into the reaction chamber within preset time according to preset pressure and preset flow rate.
S207: and after the second etching is finished, exhausting the gas of the assembly to discharge the reaction cavity into a vacuum state to finish the etching.
In some embodiments, the polysilicon thin film transistor needs to be subjected to at least two dry etching steps, and oxygen is introduced in each adjacent dry etching step.
As shown in fig. 3, fig. 3 is a schematic structural diagram of the first polysilicon thin film transistor prepared by the etching method. The first polycrystalline silicon thin film transistor is a thin film transistor with a top gate structure. The first polysilicon thin film transistor comprises a glass substrate 110, a buffer layer 120, an active layer 130, a first gate insulating layer 140, a first gate layer 150, a second gate insulating layer 160, a second gate layer 170, an interlayer insulating layer 180 and a source drain layer 190 which are sequentially stacked from bottom to top, wherein the active layer 130 comprises a source doped region and a drain doped region, and the source drain layer 180 comprises a source electrode 191 electrically connected with the source doped region and a drain electrode 192 electrically connected with the drain doped region.
In some embodiments, after the first polysilicon thin film transistor adopts the dry etching method shown in fig. 1, the active layer 130 is doped to form a drain doped region and a source doped region, and then a gate insulating layer and a gate are formed on the basis of the doped region and the gate, and then a gate pattern is obtained by photolithography to form a first gate insulating layer 140, a first gate layer 150, a second gate insulating layer 160, and a second gate layer 170, and then a dielectric layer is formed, the dielectric layer penetrates through the active layer 130 to form a through hole, and the source and drain layers are patterned at a high temperature in the through hole to form a source 191 and a drain 192, thereby obtaining the first thin film transistor.
As shown in fig. 4, fig. 4 is a schematic structural view of a second polysilicon thin film transistor prepared by the etching method. The second polycrystalline silicon thin film transistor is a polycrystalline silicon thin film transistor with a bottom gate structure. The second polysilicon thin film transistor comprises a glass substrate 210, a gate electrode layer 220, a gate insulating layer 230, an active layer 240, a source drain electrode layer 250, a passivation layer 260 and a pixel electrode layer 270 which are sequentially stacked from bottom to top. Before the second polysilicon thin film transistor 200 is dry etched, a gate layer is prepared.
The etching steps of the second polysilicon thin film transistor 200 are as follows:
s401: providing a substrate, and forming a metal film on the substrate, wherein the metal film is sequentially formed with a gate pattern.
S402: and sequentially depositing a gate insulating layer and a semiconductor layer on the gate pattern.
In some embodiments, the gate insulating layer is made of silicon nitride, and the semiconductor is made of amorphous silicon, wherein the amorphous silicon is a full-surface structure covering the gate insulating layer.
S403: and annealing the amorphous silicon to form polycrystalline silicon, wherein the surface of the polycrystalline silicon is provided with a plurality of protrusions.
S404: the surface of the polycrystalline silicon is covered with a photoresist pattern, one part of the polycrystalline silicon is covered by the non-hollow-out area of the photoresist, and the other part of the polycrystalline silicon is exposed by the hollow-out area of the photoresist.
S405: and introducing a first etching gas to remove the protrusions which are not covered by the photoresist.
S406: and introducing oxygen, and removing the oxygen and the first etching gas.
S407: and introducing a second etching gas, and completely removing the part which is not covered by the photoresist pattern to form a polysilicon pattern to prepare the active layer.
S408: and through holes are formed in the gate insulating layer, and the through holes respectively form a source electrode connection pattern and a drain electrode pattern with the active layer. And filling the source electrode pattern and the drain electrode pattern on the surface of the active layer to form a source electrode doped region and a drain electrode doped region.
S409: and a source electrode and a drain electrode are formed on the surface of the active layer.
S410: and depositing a passivation layer on the source electrode and the drain electrode, and depositing a pixel electrode on the passivation layer to form the polycrystalline silicon thin film transistor.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The above detailed description is provided for a dry etching method and a polysilicon thin film transistor provided in the embodiments of the present application, and the principle and the implementation of the present application are explained in the present application by applying specific examples, and the description of the above embodiments is only used to help understanding the technical scheme and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims (10)

1. A dry etching method, comprising:
providing a substrate, preparing a semiconductor layer and a light resistance on the substrate, and exposing and developing the light resistance;
placing the substrate, the semiconductor layer and the light resistor in a reaction chamber, introducing a first etching gas into the reaction chamber, and performing first dry etching on the semiconductor layer;
introducing oxygen into the reaction chamber;
pumping away the oxygen and the first etching gas;
and introducing a second etching gas into the reaction chamber, and performing secondary dry etching on the semiconductor layer to form an active layer.
2. The dry etching method of claim 1, wherein the first etching gas is the same as the second etching gas.
3. The dry etching method of claim 1, wherein the first etching gas is different from the second etching gas.
4. The dry etching method according to claim 1, wherein the first etching gas is a mixed gas of nitrogen trifluoride and oxygen.
5. The dry etching method of claim 1, wherein the step of introducing oxygen into the reaction chamber comprises: setting the source power and the bias voltage to be zero, and introducing oxygen into the reaction chamber within preset time according to preset pressure and preset flow rate.
6. The dry etching method according to claim 5, wherein the predetermined pressure is 0 to 5 torr.
7. The dry etching method according to claim 5, wherein the predetermined flow rate is 6000 to 10000 ml standard per minute.
8. The dry etching method according to claim 5, wherein the predetermined time is 4 to 12 seconds.
9. The dry etching method according to claim 1, wherein the dry etching method comprises at least two dry etching steps, and oxygen is introduced between any two adjacent dry etching steps.
10. A polycrystalline silicon thin film transistor, wherein the polycrystalline silicon thin film transistor is manufactured by a method comprising any one of claims 1 to 9.
CN202010288223.8A 2020-04-14 2020-04-14 Dry etching method and polycrystalline silicon thin film transistor Pending CN111463128A (en)

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