CN111446856B - Power topology circuit, control method and control device - Google Patents
Power topology circuit, control method and control device Download PDFInfo
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- CN111446856B CN111446856B CN202010320498.5A CN202010320498A CN111446856B CN 111446856 B CN111446856 B CN 111446856B CN 202010320498 A CN202010320498 A CN 202010320498A CN 111446856 B CN111446856 B CN 111446856B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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Abstract
The invention is applicable to the technical field of power topology circuits, and provides a power topology circuit, a control method and a control device, wherein the power topology circuit comprises: the direct current power supply, the boost inductor, the driving unit, the clamping unit, the output bus filtering unit and the bus output end; the positive pole of DC power supply is connected with one end of the boost inductor, and DC power supply's negative pole is connected with the negative pole of drive unit, output bus filter unit and busbar output respectively, and the boost inductor other end is connected with drive unit, and clamping unit is connected with drive unit and filter unit respectively, and output bus filter unit still is connected with the positive pole and the negative pole of busbar output respectively, and output bus filter unit is provided with a busbar central node and the first output bus filter capacitor that one end and busbar central node are connected, and clamping unit is provided with a clamping capacitor. The power topology circuit is simple to control and low in cost.
Description
Technical Field
The invention belongs to the technical field of power topology circuits, and particularly relates to a power topology circuit, a control method and a control device.
Background
Boost is the most basic DC/DC topology among power electronics topologies, and is applied to a wide variety of power electronics devices. The photovoltaic inverter comprises a DC/DC part and a DC/AC part, the DC/DC part can not only stabilize the input voltage of the DC/AC side, but also enable the battery board to output (MPPT, maximum power point tracking) at the maximum power, thereby improving the generating capacity of the photovoltaic inverter, and the DC/DC has a vital effect on the performance and the efficiency of the photovoltaic inverter.
The Boost circuit has simple topology and simple control, is widely used on the DC/DC side of the photovoltaic inverter, and can meet the voltage withstand requirement for a low-voltage system, but for higher input voltage, the two-level Boost is difficult to meet the voltage withstand requirement because most of power tubes commonly used in the market are low-voltage devices, the price of the high-voltage devices is several times that of the low-voltage devices.
The three-level boost circuit now includes: the system comprises a symmetrical Boost three-level voltage boosting circuit and a flying capacitor three-level voltage boosting circuit.
Wherein, symmetrical Boost three-level Boost circuit: the topology and the driving time sequence of the symmetrical BOOST circuit are shown in fig. 1 and 2, since the diode D1 and the diode D2 exist between the bus output and the DC source DC, the switching transistors Q1 and Q2 cannot ensure the simultaneous on and off, and when the midpoint voltages of the capacitor C1 and the capacitor C2 deviate, the driving time sequence of the switching transistor Q1 and the switching transistor Q2 needs to be adjusted to stabilize the midpoint voltages of the capacitor C1 and the capacitor C2, so that serious common mode signals exist between the output voltage and the ground, and common mode interference is formed between the ground, so that high leakage current is caused, and normal operation of the system is affected. The symmetrical Boost three-level Boost voltage requires two inductors and two independent driving circuits, which also increase the system cost.
Wherein, flying capacitor three-level boost circuit: the topology and the driving time sequence of the flying capacitor three-level booster circuit are shown in fig. 3 and 4, although the flying capacitor three-level does not have the common mode interference problem, the flying capacitor three-level needs to precharge a capacitor C3 of the flying capacitor, the precharge circuit is complex in design, the voltage on the capacitor C3 is controlled at any moment in steady-state operation, the control is complicated, the capacitance value of the capacitor C3 is large, the cost is high, and the flying capacitor three-level is difficult to be widely applied to engineering until now.
Disclosure of Invention
The embodiment of the invention provides a power topology circuit, which aims to solve the problems of complicated control and high cost of the power topology circuit in the prior art.
The embodiment of the invention provides a power topology circuit, which comprises: the direct current power supply, the boost inductor, the driving unit, the clamping unit, the output bus filtering unit and the bus output end; the positive electrode of the direct current power supply is connected with one end of the boost inductor, the negative electrode of the direct current power supply is respectively connected with the negative electrodes of the driving unit, the output bus filtering unit and the bus output end, the other end of the boost inductor is connected with the driving unit, the clamping unit is respectively connected with the driving unit and the filtering unit, the output bus filtering unit is also respectively connected with the positive electrode and the negative electrode of the bus output end, the output bus filtering unit is provided with a bus center node and a first output bus filtering capacitor, one end of the first output bus filtering capacitor is connected with the bus center node, and the clamping unit is provided with a clamping capacitor;
The driving unit comprises a first power switch tube, a second power switch tube, a third power switch tube and a fourth power switch tube, wherein the first power switch tube is respectively connected with the output bus filtering unit, the positive electrode of the bus output end, one end of the clamping capacitor and the second power switch tube, the second power switch tube is also respectively connected with one end of the clamping capacitor, the boost inductor and the third power switch tube, the third power switch tube is also respectively connected with the other end of the clamping capacitor and the fourth power switch tube, and the fourth power switch tube is also respectively connected with the negative electrode of the direct current power supply, the other end of the first output bus filtering capacitor and the negative electrode of the bus output end;
the first power switch tube, the second power switch tube, the third power switch tube and the fourth power switch tube respectively meet the preset first driving time sequence, the preset second driving time sequence, the preset third driving time sequence and the preset fourth driving time sequence.
Still further, the clamping unit comprises a first clamping diode and a second clamping diode, wherein the negative electrode of the first clamping diode is respectively connected with one end of the clamping capacitor, the first power switch tube and the second power switch tube, the positive electrode of the first clamping diode is respectively connected with the bus center node and the negative electrode of the second clamping diode, and the positive electrode of the second clamping diode is respectively connected with the other end of the clamping capacitor, the third power switch tube and the fourth power switch tube.
Still further, the output bus filter unit further includes a second output bus filter capacitor, one end of the second output bus filter capacitor is connected with the first power switch tube and the positive electrode of the bus output end respectively, and the other end of the second output bus filter capacitor is connected with one end of the first output bus filter capacitor, the bus center node and the connection point between the first clamping diode and the second clamping diode respectively.
Still further, the first power switch tube, the second power switch tube, the third power switch tube and the fourth power switch tube are respectively corresponding to a first triode, a second triode, a third triode and a fourth triode, the collector of the first triode is connected to a connecting line between the first output bus filter capacitor and the positive pole of the bus output end, the emitter of the first triode is connected to the collector of the second triode, one end of the clamping capacitor and the connecting line between the negative poles of the first clamping diode, the emitter of the second triode is connected to the connecting line between the boost inductor and the collector of the third triode, the emitter of the third triode is connected to a connecting line between the other end of the clamping capacitor, the positive pole of the second clamping diode and the collector of the fourth power switch tube, and the emitter of the fourth triode is connected to a connecting line between the negative pole of the direct current power supply, the other end of the second output bus filter capacitor and the negative pole of the bus output end.
Still further, the driving unit further comprises a first diode, a second diode, a third diode and a fourth diode, wherein the positive electrode of the first diode is connected with the emitter of the first triode, the negative electrode of the first diode is connected with the collector of the first triode, the positive electrode of the second diode is connected with the emitter of the second triode, the second diode is connected with the collector of the second triode, the positive electrode of the third diode is connected with the emitter of the third triode, the negative electrode of the third diode is connected with the collector of the third triode, the positive electrode of the fourth diode is connected with the emitter of the fourth triode, and the negative electrode of the fourth diode is connected with the collector of the fourth triode.
The embodiment of the invention also provides a control method of the power topology circuit, which is used for controlling the power topology circuit provided by the embodiment, and comprises the following steps:
respectively acquiring a first driving time sequence, a second driving time sequence, a third driving time sequence and a fourth driving time sequence which correspond to a first power switch tube, a second power switch tube, a third power switch tube and a fourth power switch tube in the driving unit;
And outputting a first driving signal, a second driving signal, a third driving signal and a fourth driving signal based on the first driving time sequence, the second driving time sequence, the third driving time sequence and the fourth driving time sequence so as to drive the first power switch tube, the second power switch tube, the third power switch tube and the fourth power switch tube to be turned on or off, so that the discharge charge quantity of the clamping capacitor to the bus output end in each period is equal to the charge quantity of the first output bus filter capacitor in each period, and the potential of a bus central node is kept unchanged so as to control the bus output end to output stable voltage.
Furthermore, the first driving signal and the second driving signal are both high level on the whole control time axis, so that the first power switch tube and the second power switch tube are in a normally-on state;
in the initial state of each period, the third driving signal and the fourth driving signal are both low level, so that the third power switch tube is in a closed state;
in a first time period in each period, the third driving signal is at a high level, the fourth driving signal is at a low level, so that the third power switch tube is in an on state, and the fourth power switch tube is in an off state;
In a second time period in each period, the third driving signal and the fourth driving signal are both high level, so that the third power switching tube and the fourth power switching tube are both in an on state;
in a third time period in each period, the third driving signal is at a high level, the fourth driving signal is at a low level, so that the third power switch tube is in an on state, and the fourth power switch tube is in an off state;
in a fourth period of time in each cycle, the third driving signal and the fourth driving signal are at a low level, so that the third power switch tube and the fourth power switch tube are in a closed state until the next cycle arrives.
The embodiment of the invention also provides a control device of the power topology circuit, which is used for controlling the power topology circuit provided by the embodiment, and the control device of the power topology circuit comprises:
the acquisition unit is used for respectively acquiring a first driving time sequence, a second driving time sequence, a third driving time sequence and a fourth driving time sequence which correspond to the first power switch tube, the second power switch tube, the third power switch tube and the fourth power switch tube in the driving unit;
And the switching tube driving unit is used for outputting a first driving signal, a second driving signal, a third driving signal and a fourth driving signal based on the first driving time sequence, the second driving time sequence, the third driving time sequence and the fourth driving time sequence so as to drive the first power switching tube, the second power switching tube, the third power switching tube and the fourth power switching tube to be turned on or off, so that the discharge charge quantity of the clamping capacitor to the bus output end in each period is equal to the charge quantity of the first output bus filter capacitor in each period, and the potential of a bus center node is kept unchanged so as to control the bus output end to output stable voltage.
Furthermore, the first driving signal and the second driving signal are both high level on the whole control time axis, so that the first power switch tube and the second power switch tube are in a normally-on state;
in the initial state of each period, the third driving signal and the fourth driving signal are both low level, so that the third power switch tube is in a closed state;
in a first time period in each period, the third driving signal is at a high level, the fourth driving signal is at a low level, so that the third power switch tube is in an on state, and the fourth power switch tube is in an off state;
In a second time period in each period, the third driving signal and the fourth driving signal are both high level, so that the third power switching tube and the fourth power switching tube are both in an on state;
in a third time period in each period, the third driving signal is at a high level, the fourth driving signal is at a low level, so that the third power switch tube is in an on state, and the fourth power switch tube is in an off state;
in a fourth period of time in each cycle, the third driving signal and the fourth driving signal are at a low level, so that the third power switch tube and the fourth power switch tube are in a closed state until the next cycle arrives.
The invention has the beneficial effects that: and controlling the on or off of a first power switch tube, a second power switch tube, a third power switch tube and a fourth power switch tube in a driving unit through a preset first driving time sequence, a preset second driving time sequence, a preset third driving time sequence and a preset fourth driving time sequence, so that the discharge charge quantity of the clamping capacitor to the bus output end in each period is equal to the charge quantity of the first output bus filter capacitor in each period, and the potential of a bus central node is kept unchanged to control the bus output end to output stable voltage. The voltage that can be stable will step up the inductance output like this is transmitted to the generating line output for power topology circuit can provide stable voltage, and this power topology circuit has following advantage simultaneously:
1. The first power switch tube and the second power switch tube are in a normally-on state due to the first driving time sequence and the second driving time sequence, the third power switch tube and the fourth power switch tube only need to meet the third driving time sequence and the fourth driving time sequence, and the driving of the third power switch tube and the fourth power switch tube does not need independent control, so that the control of the first power switch tube, the second power switch tube, the third power switch tube and the fourth power switch tube is simple.
2. In the power topology circuit, the direct current power supply and the bus output end are of a common negative electrode, so that the power topology circuit has no problem of interference of an engineering mode.
3. In the power topology circuit, only one boost inductor is needed, so the cost in the power topology circuit is low.
Drawings
FIG. 1 is a circuit diagram of a symmetrical Boost three-level Boost circuit provided in the prior art;
FIG. 2 is a timing diagram of a symmetrical Boost three-level Boost circuit according to the prior art;
FIG. 3 is a circuit diagram of a flying capacitor three-level boost circuit provided in the prior art;
FIG. 4 is a timing diagram of a prior art drive scheme for a flying capacitor three level boost circuit;
FIG. 5 is a circuit diagram of a power topology circuit provided by an embodiment of the present invention;
FIG. 6 is a driving timing diagram of a power topology according to an embodiment of the present invention;
fig. 7 is a flowchart of a control method of a power topology circuit according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a control device of a power topology circuit according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The power topology circuit of the present invention includes: the power supply comprises a direct current power supply DC, a boost inductor L, a power switch tube Q1, a power switch tube Q2, a power switch tube Q3, a power switch tube Q4, a capacitor Cx, an output bus filter capacitor C2 and a bus output end. The positive pole of DC power supply DC is connected with one end of boost inductance L, and the negative pole of DC power supply DC and one end of emitter and output bus filter capacitor C2 of power switch tube Q4. The other end of the boost inductor L is connected to the emitter of the power switching transistor Q2 and the negative electrode of the collector of the power switching transistor Q3. The emitter of the power switch tube Q3 is connected with the collector of the power switch tube Q4, one end of the capacitor Cx is connected, the collector of the power switch tube Q2 is connected with the emitter of the power switch tube Q1, the other end of the capacitor Cx is connected, the collector of the power switch tube Q1 is connected with the positive electrode of the bus output end, and the other end of the output bus filter capacitor C2 is connected with the bus output end. The invention discloses a boost circuit topology realized by controlling the logic of a switching tube, which has the following advantages: 1. because the power switch tube Q1 and the power switch tube Q2 are normally on, the power switch tube Q3 and the power switch tube Q4 only need to meet corresponding driving time sequences, so that the control is simple; 2. because the input DC and bus output are common-negative, there is no common-mode interference problem; 3. in the power topology circuit, only one boost inductor is needed, so the cost in the power topology circuit is low.
Example 1
As shown in fig. 5, fig. 5 is a circuit diagram of a power topology circuit according to an embodiment of the present invention; the power topology circuit includes: a direct current power supply DC, a boost inductor L, a driving unit 4, a clamping unit 3, an output bus filtering unit 2 and a bus output end 1; the positive pole of DC power supply DC is connected with boost inductor L one end, DC power supply DC's negative pole is connected with the negative pole of drive unit 4, output bus filter unit 2 and busbar output 1 respectively, boost inductor L other end is connected with drive unit 4, clamping unit 3 is connected with drive unit 4 and filter unit respectively, output bus filter unit 2 still is connected with the positive pole and the negative pole of busbar output 1 respectively, output bus filter unit 2 is provided with a busbar central node O2 and one end is connected with first output bus filter capacitor C1 of busbar central node O2, clamping unit 3 is provided with a clamp capacitance Cx.
The driving unit 4 comprises a first power switch tube Q1, a second power switch tube Q2, a third power switch tube Q3 and a fourth power switch tube Q4, wherein the first power switch tube Q1 is respectively connected with the output bus filtering unit 2, the positive electrode of the bus output end 1, one end of a clamping capacitor Cx and the second power switch tube Q2, the second power switch tube Q2 is respectively connected with one end of the clamping capacitor Cx, a boosting inductor L and the third power switch tube Q3, the third power switch tube Q3 is respectively connected with the other end of the clamping capacitor Cx and the fourth power switch tube Q4, and the fourth power switch tube Q4 is respectively connected with the negative electrode of the direct current power supply DC, the other end of the first output bus filtering capacitor C1 and the negative electrode of the bus output end 1;
The first power switch tube Q1, the second power switch tube Q2, the third power switch tube Q3 and the fourth power switch tube Q4 respectively meet the preset first driving time sequence, second driving time sequence, third driving time sequence and fourth driving time sequence.
Specifically, as shown in fig. 6, the first driving timing drives the first power switch Q1 to make the gate voltage of the first power switch Q1 be at a high level on the whole control time axis, that is, the first power switch Q1 is in a normally-on state on the whole control time axis. The second driving time sequence drives the second power switch tube Q2 to enable the gate voltage of the second power switch tube Q2 to be in a high level on the whole control time axis, namely the second power switch tube Q2 is in a normally-on state on the whole control time axis. The first driving timing and the second driving timing are the same, so that the on or off states of the first power switch Q1 and the second power switch Q2 are the same. In this way, when the first power switching transistor Q1 and the second power switching transistor Q2 are normally on the entire control time axis, the third power switching transistor Q3 and the fourth power switching transistor Q4 may be turned on or off by the third driving timing sequence and the fourth driving timing sequence.
The third driving timing periodically drives the third power switch Q3 to make the initial state of the gate voltage thereof in each period on the whole control time axis be a low level, that is, the initial state in each period is the off state of the third power switch Q3. The gate voltage of the third power switching transistor Q3 is at a high level in the first period t1 after the initial state, that is, the third power switching transistor Q3 is in an on state in the first period t1 in each period. The gate voltage of the third power switching transistor Q3 is maintained at a high level for the second period. The gate voltage of the third power switching transistor Q3 continues to be maintained at a high level for a third period t2 in each cycle. In a fourth period of time in each cycle, the gate voltage of the third power switching transistor Q3 is switched to a low level until the next cycle comes.
The fourth driving timing periodically drives the fourth power switch Q4 to make the initial state of the gate voltage thereof in each period on the entire control time axis be a low level, that is, the initial state of the fourth power switch Q4 in each period is an off state. The gate voltage of the fourth power switching transistor Q4 continues to be maintained at a low level for a first period t1 after the initial state, and the gate voltage of the fourth power switching transistor Q4 is converted to a high level for a second period in each period. In the third period t2 in each cycle, the gate voltage of the fourth power switching transistor Q4 is converted to a low level. The gate voltage of the fourth power switch Q4 continues to remain low for the fourth period of time in each cycle until the next cycle.
The first, second, third and fourth periods t1, t2 and t2 of the third driving timing are synchronized with the times of the first, second, third and fourth periods t1, t2 and t2 of the fourth driving timing. And the first period t1 may be denoted by t1, for which the first period t1 may be denoted as the first period t1, and the third period t2 may be denoted as t2, for which the second period may be denoted as the second period t2.
In an embodiment of the present invention, the clamping unit 3 includes a clamping unit 3 including a first clamping diode D5 and a second clamping diode D6, wherein a negative electrode of the first clamping diode D5 is connected to one end of the clamping capacitor Cx, the first power switching tube Q1 and the second power switching tube Q2, an positive electrode of the first clamping diode D5 is connected to the bus central node O2 and a negative electrode of the second clamping diode D6, and a positive electrode of the second clamping diode D6 is connected to the other end of the clamping capacitor Cx, the third power switching tube Q3 and the fourth power switching tube Q4.
Specifically, during the second period of time in each cycle, that is, when the third power switching transistor Q3 is turned on and the fourth power switching transistor Q4 is turned on, the clamp capacitance Cx is charged through the first clamp diode D5.
The first output bus filter capacitor C1 is charged through the second clamp diode D6 in the first period t1 and the third period t2 in each cycle. If the average value of the charging current to the first output bus filter capacitor C1 in the first period t1 and the third period t2 is Ic1 in each period, the charging charge amount to the first output bus filter capacitor C1 in each period is Δqc1=i1 (t1+t2).
In an embodiment of the present invention, the output bus filter unit 2 further includes a second output bus filter capacitor C2, one end of the second output bus filter capacitor C2 is connected to the first power switch Q1 and the positive electrode of the bus output terminal 1, and the other end of the second output bus filter capacitor C2 is connected to one end of the first output bus filter capacitor C1, the bus center node O2, and the connection point between the first clamping diode D5 and the second clamping diode D6, respectively. In this way, the second output bus filter capacitor C2 can filter the bus output terminal 1, so that the bus output terminal 1 can provide a more stable voltage. The voltage output by the bus bar output terminal 1 may be high voltage.
The working principle of the power topology circuit is as follows:
on the whole control time axis, the first power switch tube Q1 and the second power switch tube Q2 are all normally on, the initial state in each period, and the gate drive voltages of the third power switch tube Q3 and the fourth power switch tube Q4 are low level; in a first time period t1 in each period, the gate driving voltage of the third power switch tube Q3 is high level, and the gate driving voltage of the fourth power switch tube Q4 is low level; after the first time period t1, that is, in the second time period in each period, the gate driving voltages of the third power switch tube Q3 and the fourth power switch tube Q4 are both high levels; in the third period t2 of each cycle, the gate driving voltage of the third power switch Q3 is at a high level, and the gate driving voltage of the fourth power switch Q4 is at a low level. In the fourth period of time in each cycle, the gate driving voltages of the third power switch Q3 and the fourth power switch Q4 are both low level until the next cycle comes.
For example, assuming that the total bus voltage is Vout and remains unchanged, the potential of the bus center node O2 always rises in the previous x period of operation of the power topology circuit, and assuming that the potential of the bus center node O2 rises to 1/2vout+a, the potential of the bus center node O2 no longer changes and is always 1/2vout+a; the voltage across the clamp capacitance Cx is 1/2Vout-a, the capacitance value of the clamp capacitance Cx is d, and the voltage across the clamp capacitance Cx is 1/2Vout+a.
From this, it can be seen that, first, in the first period t1 in each cycle, the third power switching transistor Q3 is turned on, the fourth power switching transistor Q4 is turned off, the charge of the clamp capacitor Cx remains unchanged, neither charging nor discharging is performed, and the voltage across the clamp capacitor Cx is 1/2Vout-a.
2. In the second period of time in each cycle, the third power switch Q3 is turned on, the fourth power switch Q4 is turned on, the clamping capacitor Cx is charged by the second clamping diode D6, the charging charge quantity is Δ Qcx =d×2a, and the voltage across the clamping capacitor Cx is changed from 1/2Vout-a to 1/2vout+a.
3. In a third period t2 in each period, the third power switch tube Q3 is turned on, the fourth power switch tube Q4 is turned off, the clamping capacitor Cx discharges to the total bus through the first power switch tube Q1, the discharge charge quantity is Δ Qcx =d2a, and the voltage across the clamping capacitor Cx is changed from 1/2vout+a to 1/2vout-a.
4. In a fourth period of time in each cycle, the third power switching transistor Q3 is turned off, the fourth power switching transistor Q4 is turned off, and the charge of the clamp capacitance Cx remains unchanged.
If the average value of the charging current to the first output bus filter capacitor C1 in the first period t1 and the third period t2 is Ic1 in each period, the charging charge amount to the first output bus filter capacitor C1 in each period is Δqc1=i1× (t1+t2), the charge amount of the clamp capacitor Cx discharged to the total bus in each period is Δ Qcx =d2a, if the potential of the bus center node O2 remains unchanged, Δqc1= Δ Qcx, at this time a= (Ic 1×t1+t2))/(2*d), and the bus center node O2 remains unchanged. Where a is a parameter variable, and the value of a is related to the current Ic1 of the first output bus filter capacitor C1, the time length t1 of the first time period t1, the time length t2 of the third time period t2, and the capacitance d of the clamp capacitor Cx. The value of a can be set according to the size of the bus bar output terminal 1.
In the embodiment of the invention, the first power switch tube Q1, the second power switch tube Q2, the third power switch tube Q3 and the fourth power switch tube Q4 in the driving unit 4 are controlled to be turned on or off through the preset first driving time sequence, the preset second driving time sequence, the preset third driving time sequence and the preset fourth driving time sequence, so that the discharge charge quantity of the clamping capacitor Cx to the bus output terminal 1 in each period is equal to the charge quantity of the first output bus filter capacitor C1 in each period, and the potential of the bus central node O2 is kept unchanged, thereby controlling the bus output terminal 1 to output stable voltage. The voltage that can be stable in this way will step up inductance L output is transmitted to busbar output 1 for power topology circuit can provide stable voltage, and this power topology circuit has following advantage simultaneously:
1. The first power switch tube Q1 and the second power switch tube Q2 are in a normal on state by the first driving time sequence and the second driving time sequence, the third power switch tube Q3 and the fourth power switch tube Q4 only need to meet the third driving time sequence and the fourth driving time sequence, and the driving of the third power switch tube Q4 and the fourth power switch tube Q4 do not need independent control, so that the control of the first power switch tube Q1, the second power switch tube Q2, the third power switch tube Q3 and the fourth power switch tube Q4 is simple.
2. In the power topology circuit, the direct current power supply DC and the bus output end 1 are of common negative electrode, so that the power topology circuit has no problem of interference of an engineering mode.
3. In the power topology circuit, only one boost inductor L is needed, so the cost in the power topology circuit is low.
Example two
As shown in fig. 5, the first power switch Q1, the second power switch Q2, the third power switch Q3 and the fourth power switch Q4 are respectively corresponding to a first triode, a second triode, a third triode and a fourth triode, the collector of the first triode is connected to a connection line between the first output bus filter capacitor C1 and the positive electrode of the bus output terminal 1, the emitter of the first triode is connected to a connection line between the collector of the second triode, one end of the clamping capacitor Cx and the negative electrode of the first clamping diode D5, the emitter of the second triode is connected to a connection line between the boost inductor L and the collector of the third triode, the emitter of the third triode is connected to a connection line between the other end of the clamping capacitor Cx, the positive electrode of the second clamping diode D6 and the collector of the fourth power switch Q4, and the emitter of the fourth triode is connected to a connection line between the negative electrode of the direct current power supply DC, the other end of the second output filter capacitor C2 and the negative electrode of the bus output terminal 1.
Of course, the first power switch tube Q1, the second power switch tube Q2, the third power switch tube Q3 and the fourth power switch tube Q4 are respectively corresponding to a first MOS tube, a second MOS tube, a third MOS tube and a fourth MOS tube. Alternatively, the first power switching tube Q1, the second power switching tube Q2, the third power switching tube Q3, and the fourth power switching tube Q4 may be respectively corresponding to other components having a switching function.
It should be noted that the first transistor, the second transistor, the third transistor and the fourth transistor also respectively satisfy the preset first driving timing, the preset second driving timing, the preset third driving timing and the preset fourth driving timing shown in fig. 6. Of course, when the first power switch tube Q1, the second power switch tube Q2, the third power switch tube Q3 and the fourth power switch tube Q4 are respectively corresponding to the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube, the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube also respectively correspond to the preset first driving time sequence, the preset second driving time sequence, the preset third driving time sequence and the preset fourth driving time sequence shown in fig. 6.
In an embodiment of the present invention, the driving unit 4 further includes a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4, wherein the anode of the first diode D1 is connected to the emitter of the first triode, the cathode of the first diode D1 is connected to the collector of the first triode, the anode of the second diode D2 is connected to the emitter of the second triode, the second diode D2 is connected to the collector of the second triode, the anode of the third diode D3 is connected to the emitter of the third triode, the cathode of the third diode D3 is connected to the collector of the third triode, the anode of the fourth diode D4 is connected to the emitter of the fourth triode, and the cathode of the fourth diode D4 is connected to the collector of the fourth triode.
Specifically, the first diode D1, the second diode D2, the third diode D3, and the fourth diode D4 all play a role in protection. The first diode D1 and the second diode D2 can protect the first power switch Q1 and the second power switch Q2 when the first power switch Q1 and the second power switch are reversely connected or short-circuited. The third diode D3 and the fourth diode D4 can protect the third power switching transistor Q3 and the fourth power switching transistor Q4 when the bus is short-circuited or the DC power supply DC is connected reversely. Therefore, the hardware cost of the first power switch tube Q1, the second power switch tube Q2, the third power switch tube Q3 and the fourth power switch tube Q4 in the power topology circuit can be reduced, and meanwhile, the power topology circuit is safer to work.
In the embodiment of the invention, the first power switch tube Q1, the second power switch tube Q2, the third power switch tube Q3 and the fourth power switch tube Q4 are respectively corresponding to a first triode, a second triode, a third triode and a fourth triode, the triodes are common switch components or voltage control components, the technology of the triodes is relatively mature, the cost of the components is not required to be too much, the control and the connection of the triodes are relatively simple, the cost of the first power switch tube Q1, the second power switch tube Q2, the third power switch tube Q3 and the fourth power switch tube Q4 is low, the connection and the control process of a circuit are simplified, and the circuit cost of the power topology circuit is low, and the circuit structure and the control process are simple. And each triode corresponding to the first power switch tube Q1, the second power switch tube Q2, the third power switch tube Q3 and the fourth power switch tube Q4 is provided with a corresponding diode, so that the effect of protecting the triode is achieved, and the safety of the power topology circuit is improved.
Example III
As shown in fig. 7, fig. 7 is a flowchart of a control method of a power topology circuit according to an embodiment of the present invention, for controlling the power topology circuit according to any one of the first to second embodiments, the control method of the power topology circuit includes the following steps:
step 101, a first driving time sequence, a second driving time sequence, a third driving time sequence and a fourth driving time sequence corresponding to a first power switch tube, a second power switch tube, a third power switch tube and a fourth power switch tube in a driving unit are respectively obtained.
Step 102, outputting a first driving signal, a second driving signal, a third driving signal and a fourth driving signal based on the first driving timing sequence, the second driving timing sequence, the third driving timing sequence and the fourth driving timing sequence to drive the first power switch tube, the second power switch tube, the third power switch tube and the fourth power switch tube to be turned on or off, so that the discharge charge quantity of the clamping capacitor to the bus output end in each period is equal to the charge quantity of the first output bus filter capacitor in each period, and the potential of the bus central node is kept unchanged to control the bus output end to output stable voltage.
As an embodiment of the present invention, the first driving signal and the second driving signal are both high level on the whole control time axis, so that the first power switch Q1 and the second power switch Q2 are in a normally-on state;
in the initial state in each period, the third driving signal and the fourth driving signal are both low level, so that the third power switch tube Q3 is in a closed state;
in a first time period t1 in each period, the third driving signal is at a high level, the fourth driving signal is at a low level, so that the third power switch tube Q3 is in an on state, and the fourth power switch tube Q4 is in an off state;
in the second time period in each period, the third driving signal and the fourth driving signal are both high level, so that the third power switch tube Q3 and the fourth power switch tube Q4 are both in an on state;
in a third time period t2 in each period, the third driving signal is at a high level, the fourth driving signal is at a low level, so that the third power switch tube Q3 is in an on state, and the fourth power switch tube Q4 is in an off state;
in the fourth period of time in each cycle, the third driving signal and the fourth driving signal are at low level, so that the third power switch Q3 and the fourth power switch Q4 are in the off state until the next cycle comes.
The control principle of the power topology circuit is as follows:
based on the first driving signal, the second driving signal, the third driving signal, and the fourth driving signal at the first driving timing, the second driving timing, the third driving timing, and the fourth driving timing, the first power switch Q1, the second power switch Q2, the third power switch Q3, and the fourth power switch Q4 are driven to be turned on or off, so that the discharge charge amount of the clamping capacitor Cx in each period to the bus output terminal 1 is equal to the charge amount of the first output bus filter capacitor C1 in each period, and the potential of the bus center node O2 is kept unchanged, so as to control the bus output terminal 1 to output a stable voltage. This enables stable transmission of the voltage output by the boost inductor L to the bus bar output terminal 1, so that the power topology circuit can provide a stable voltage.
Specifically, the working principle of the power topology circuit is as follows: on the whole control time axis, the first power switch tube Q1 and the second power switch tube Q2 are all normally on, the initial state in each period, and the gate drive voltages of the third power switch tube Q3 and the fourth power switch tube Q4 are low level; in a first time period t1 in each period, the gate driving voltage of the third power switch tube Q3 is high level, and the gate driving voltage of the fourth power switch tube Q4 is low level; after the first time period t1, that is, in the second time period in each period, the gate driving voltages of the third power switch tube Q3 and the fourth power switch tube Q4 are both high levels; in the third period t2 of each cycle, the gate driving voltage of the third power switch Q3 is at a high level, and the gate driving voltage of the fourth power switch Q4 is at a low level. In the fourth period of time in each cycle, the gate driving voltages of the third power switch Q3 and the fourth power switch Q4 are both low level until the next cycle comes.
For example, assuming that the total bus voltage is Vout and remains unchanged, the potential of the bus center node O2 always rises in the previous x period of operation of the power topology circuit, and assuming that the potential of the bus center node O2 rises to 1/2vout+a, the potential of the bus center node O2 no longer changes and is always 1/2vout+a; the voltage across the clamp capacitance Cx is 1/2Vout-a, the capacitance value of the clamp capacitance Cx is d, and the voltage across the clamp capacitance Cx is 1/2Vout+a.
From this, it can be seen that, first, in the first period t1 in each cycle, the third power switching transistor Q3 is turned on, the fourth power switching transistor Q4 is turned off, the charge of the clamp capacitor Cx remains unchanged, neither charging nor discharging is performed, and the voltage across the clamp capacitor Cx is 1/2Vout-a.
2. In the second period of time in each cycle, the third power switch Q3 is turned on, the fourth power switch Q4 is turned on, the clamping capacitor Cx is charged by the second clamping diode D6, the charging charge quantity is Δ Qcx =d×2a, and the voltage across the clamping capacitor Cx is changed from 1/2Vout-a to 1/2vout+a.
3. In a third period t2 in each period, the third power switch tube Q3 is turned on, the fourth power switch tube Q4 is turned off, the clamping capacitor Cx discharges to the total bus through the first power switch tube Q1, the discharge charge quantity is Δ Qcx =d2a, and the voltage across the clamping capacitor Cx is changed from 1/2vout+a to 1/2vout-a.
4. In a fourth period of time in each cycle, the third power switching transistor Q3 is turned off, the fourth power switching transistor Q4 is turned off, and the charge of the clamp capacitance Cx remains unchanged.
If the average value of the charging current to the first output bus filter capacitor C1 in the first period t1 and the third period t2 is Ic1 in each period, the charging charge amount to the first output bus filter capacitor C1 in each period is Δqc1=i1× (t1+t2), the charge amount of the clamp capacitor Cx discharged to the total bus in each period is Δ Qcx =d2a, if the potential of the bus center node O2 remains unchanged, Δqc1= Δ Qcx, at this time a= (Ic 1×t1+t2))/(2*d), and the bus center node O2 remains unchanged. Where a is a parameter variable, and the value of a is related to the current Ic1 of the first output bus filter capacitor C1, the time length t1 of the first time period t1, the time length t2 of the third time period t2, and the capacitance d of the clamp capacitor Cx. The value of a can be set according to the size of the bus bar output terminal 1.
In the embodiment of the invention, a first driving time sequence, a second driving time sequence, a third driving time sequence and a fourth driving time sequence corresponding to a first power switch tube Q1, a second power switch tube Q2, a third power switch tube Q3 and a fourth power switch tube Q4 in a driving unit 4 are respectively obtained; based on the first driving time sequence, the second driving time sequence, the third driving time sequence and the fourth driving time sequence, the first driving signal, the second driving signal, the third driving signal and the fourth driving signal are output so as to drive the first power switch tube Q1, the second power switch tube Q2, the third power switch tube Q3 and the fourth power switch tube Q4 to be turned on or off, so that the discharge charge quantity of the clamping capacitor Cx in each period to the bus output end 1 is equal to the charge quantity of the first output bus filter capacitor C1 in each period, and the potential of the bus center node O2 is kept unchanged so as to control the bus output end 1 to output stable voltage. This enables stable transmission of the voltage output by the boost inductor L to the bus bar output terminal 1, so that the power topology circuit can provide a stable voltage.
Example IV
As shown in fig. 8, fig. 8 is a schematic structural diagram of a control device for a power topology circuit according to an embodiment of the present invention, where the control device 200 for a power topology circuit is used for controlling the power topology circuit according to the first to second embodiments, and the control device 200 for a power topology circuit can use the method steps in the third embodiment, and the control device 200 for a power topology circuit includes:
an obtaining unit 201, configured to obtain a first driving timing sequence, a second driving timing sequence, a third driving timing sequence, and a fourth driving timing sequence corresponding to the first power switch Q1, the second power switch Q2, the third power switch Q3, and the fourth power switch Q4 in the driving unit 4, respectively;
the switching tube driving unit 202 is configured to output a first driving signal, a second driving signal, a third driving signal, and a fourth driving signal based on the first driving timing, the second driving timing, the third driving timing, and the fourth driving timing, so as to drive the first power switching tube Q1, the second power switching tube Q2, the third power switching tube Q3, and the fourth power switching tube Q4 to be turned on or off, so that a discharge charge amount of the clamp capacitor Cx to the bus bar output terminal 1 in each period is equal to a charge amount of the first output bus bar filter capacitor C1 in each period, and a potential of the bus bar center node O2 is kept unchanged, so as to control the bus bar output terminal 1 to output a stable voltage.
In an embodiment of the present invention, the first driving signal and the second driving signal are both high level on the whole control time axis, so that the first power switch tube Q1 and the second power switch tube Q2 are in a normally-on state; .
In the initial state in each period, the third driving signal and the fourth driving signal are both at low level, so that the third power switch Q3 is in the off state.
In the first period t1 in each period, the third driving signal is at a high level, the fourth driving signal is at a low level, so that the third power switch Q3 is in an on state, and the fourth power switch Q4 is in an off state.
In the second time period in each period, the third driving signal and the fourth driving signal are both high level, so that the third power switch tube Q3 and the fourth power switch tube Q4 are both in an on state;
in the third period t2 in each period, the third driving signal is at a high level, the fourth driving signal is at a low level, so that the third power switch Q3 is in an on state, and the fourth power switch Q4 is in an off state.
In the fourth period of time in each cycle, the third driving signal and the fourth driving signal are at low level, so that the third power switch Q3 and the fourth power switch Q4 are in the off state until the next cycle comes.
The working principle of the control device 200 of the power topology circuit is as follows:
based on the first driving signal, the second driving signal, the third driving signal, and the fourth driving signal at the first driving timing, the second driving timing, the third driving timing, and the fourth driving timing, the first power switch Q1, the second power switch Q2, the third power switch Q3, and the fourth power switch Q4 are driven to be turned on or off, so that the discharge charge amount of the clamping capacitor Cx in each period to the bus output terminal 1 is equal to the charge amount of the first output bus filter capacitor C1 in each period, and the potential of the bus center node O2 is kept unchanged, so as to control the bus output terminal 1 to output a stable voltage. This enables stable transmission of the voltage output by the boost inductor L to the bus bar output terminal 1, so that the power topology circuit can provide a stable voltage.
Specifically, the working principle of the power topology circuit is as follows: on the whole control time axis, the first power switch tube Q1 and the second power switch tube Q2 are all normally on, the initial state in each period, and the gate drive voltages of the third power switch tube Q3 and the fourth power switch tube Q4 are low level; in a first time period t1 in each period, the gate driving voltage of the third power switch tube Q3 is high level, and the gate driving voltage of the fourth power switch tube Q4 is low level; after the first time period t1, that is, in the second time period in each period, the gate driving voltages of the third power switch tube Q3 and the fourth power switch tube Q4 are both high levels; in the third period t2 of each cycle, the gate driving voltage of the third power switch Q3 is at a high level, and the gate driving voltage of the fourth power switch Q4 is at a low level. In the fourth period of time in each cycle, the gate driving voltages of the third power switch Q3 and the fourth power switch Q4 are both low level until the next cycle comes.
For example, assuming that the total bus voltage is Vout and remains unchanged, the potential of the bus center node O2 always rises in the previous x period of operation of the power topology circuit, and assuming that the potential of the bus center node O2 rises to 1/2vout+a, the potential of the bus center node O2 no longer changes and is always 1/2vout+a; the voltage across the clamp capacitance Cx is 1/2Vout-a, the capacitance value of the clamp capacitance Cx is d, and the voltage across the clamp capacitance Cx is 1/2Vout+a.
From this, it can be seen that, first, in the first period t1 in each cycle, the third power switching transistor Q3 is turned on, the fourth power switching transistor Q4 is turned off, the charge of the clamp capacitor Cx remains unchanged, neither charging nor discharging is performed, and the voltage across the clamp capacitor Cx is 1/2Vout-a.
2. In the second period of time in each cycle, the third power switch Q3 is turned on, the fourth power switch Q4 is turned on, the clamping capacitor Cx is charged by the second clamping diode D6, the charging charge quantity is Δ Qcx =d×2a, and the voltage across the clamping capacitor Cx is changed from 1/2Vout-a to 1/2vout+a.
3. In a third period t2 in each period, the third power switch tube Q3 is turned on, the fourth power switch tube Q4 is turned off, the clamping capacitor Cx discharges to the total bus through the first power switch tube Q1, the discharge charge quantity is Δ Qcx =d2a, and the voltage across the clamping capacitor Cx is changed from 1/2vout+a to 1/2vout-a.
4. In a fourth period of time in each cycle, the third power switching transistor Q3 is turned off, the fourth power switching transistor Q4 is turned off, and the charge of the clamp capacitance Cx remains unchanged.
If the average value of the charging current to the first output bus filter capacitor C1 in the first period t1 and the third period t2 is Ic1 in each period, the charging charge amount to the first output bus filter capacitor C1 in each period is Δqc1=i1× (t1+t2), the charge amount of the clamp capacitor Cx discharged to the total bus in each period is Δ Qcx =d2a, if the potential of the bus center node O2 remains unchanged, Δqc1= Δ Qcx, at this time a= (Ic 1×t1+t2))/(2*d), and the bus center node O2 remains unchanged. Where a is a parameter variable, and the value of a is related to the current Ic1 of the first output bus filter capacitor C1, the time length t1 of the first time period t1, the time length t2 of the third time period t2, and the capacitance d of the clamp capacitor Cx. The value of a can be set according to the size of the bus bar output terminal 1.
In the embodiment of the invention, a first driving time sequence, a second driving time sequence, a third driving time sequence and a fourth driving time sequence corresponding to a first power switch tube Q1, a second power switch tube Q2, a third power switch tube Q3 and a fourth power switch tube Q4 in a driving unit 4 are respectively obtained; based on the first driving time sequence, the second driving time sequence, the third driving time sequence and the fourth driving time sequence, the first driving signal, the second driving signal, the third driving signal and the fourth driving signal are output so as to drive the first power switch tube Q1, the second power switch tube Q2, the third power switch tube Q3 and the fourth power switch tube Q4 to be turned on or off, so that the discharge charge quantity of the clamping capacitor Cx in each period to the bus output end 1 is equal to the charge quantity of the first output bus filter capacitor C1 in each period, and the potential of the bus center node O2 is kept unchanged so as to control the bus output end 1 to output stable voltage. This enables stable transmission of the voltage output by the boost inductor L to the bus bar output terminal 1, so that the power topology circuit can provide a stable voltage.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (7)
1. A power topology, the power topology comprising: the direct current power supply, the boost inductor, the driving unit, the clamping unit, the output bus filtering unit and the bus output end; the positive electrode of the direct current power supply is connected with one end of the boost inductor, the negative electrode of the direct current power supply is respectively connected with the driving unit, the output bus filtering unit and the negative electrode of the bus output end, the other end of the boost inductor is connected with the driving unit, the clamping unit is respectively connected with the driving unit and the output bus filtering unit, the output bus filtering unit is also respectively connected with the positive electrode and the negative electrode of the bus output end, the output bus filtering unit is provided with a bus center node and a first output bus filtering capacitor, one end of the first output bus filtering capacitor is connected with the bus center node, and the clamping unit is provided with a clamping capacitor;
the driving unit comprises a first power switch tube, a second power switch tube, a third power switch tube and a fourth power switch tube, wherein the collector electrode of the first power switch tube is connected with the output bus filtering unit and the positive electrode of the bus output end, and the emitter electrode of the first power switch tube is connected with one end of the clamping capacitor and the collector electrode of the second power switch tube; the collector of the second power switch tube is connected with one end of the clamping capacitor, and the emitter of the second power switch tube is connected with one end of the boost inductor and the collector of the third power switch tube; the emitter of the third power switch tube is connected with the other end of the clamping capacitor and the collector of the fourth power switch tube, and the emitter of the fourth power switch tube is connected with the negative electrode of the direct current power supply, the other end of the first output bus filter capacitor and the negative electrode of the bus output end;
The first power switch tube, the second power switch tube, the third power switch tube and the fourth power switch tube respectively meet a preset first driving time sequence, a preset second driving time sequence, a preset third driving time sequence and a preset fourth driving time sequence; respectively acquiring a first driving time sequence, a second driving time sequence, a third driving time sequence and a fourth driving time sequence which correspond to a first power switch tube, a second power switch tube, a third power switch tube and a fourth power switch tube in the driving unit;
outputting a first driving signal, a second driving signal, a third driving signal and a fourth driving signal based on the first driving time sequence, the second driving time sequence, the third driving time sequence and the fourth driving time sequence so as to drive the first power switch tube, the second power switch tube, the third power switch tube and the fourth power switch tube to be turned on or off, so that the discharge charge quantity of the clamping capacitor to the bus output end in each period is equal to the charge quantity of the first output bus filter capacitor in each period, and the potential of a bus central node is kept unchanged so as to control the bus output end to output stable voltage; the first driving signal and the second driving signal are high level on the whole control time axis, so that the first power switch tube and the second power switch tube are in a normally-on state;
In the initial state of each period, the third driving signal and the fourth driving signal are both in a low level, so that the third power switching tube and the fourth power switching tube are both in a closed state;
in a first time period in each period, the third driving signal is at a high level, the fourth driving signal is at a low level, so that the third power switch tube is in an on state, and the fourth power switch tube is in an off state;
in a second time period in each period, the third driving signal and the fourth driving signal are both high level, so that the third power switching tube and the fourth power switching tube are both in an on state;
in a third time period in each period, the third driving signal is at a high level, the fourth driving signal is at a low level, so that the third power switch tube is in an on state, and the fourth power switch tube is in an off state;
in a fourth period of time in each cycle, the third driving signal and the fourth driving signal are at a low level, so that the third power switch tube and the fourth power switch tube are in a closed state until the next cycle arrives.
2. The power topology of claim 1, wherein the clamping unit comprises a first clamping diode and a second clamping diode, wherein a negative pole of the first clamping diode is connected with one end of the clamping capacitor, the first power switching tube and the second power switching tube respectively, a positive pole of the first clamping diode is connected with the bus center node and a negative pole of the second clamping diode respectively, and a positive pole of the second clamping diode is connected with the other end of the clamping capacitor, the third power switching tube and the fourth power switching tube respectively.
3. The power topology of claim 2, wherein said output bus filter unit further comprises a second output bus filter capacitor, one end of said second output bus filter capacitor is connected to said first power switch tube and an anode of said bus output terminal, respectively, and the other end of said second output bus filter capacitor is connected to one end of said first output bus filter capacitor, said bus center node, and a connection point between said first clamp diode and said second clamp diode, respectively.
4. The power topology circuit of claim 3, wherein the first power switch tube, the second power switch tube, the third power switch tube and the fourth power switch tube are respectively corresponding to a first triode, a second triode, a third triode and a fourth triode, a collector of the first triode is connected to a connecting line between the second output bus filter capacitor and an anode of the bus output end, an emitter of the first triode is connected to a connecting line between a collector of the second triode, one end of the clamping capacitor and a cathode of the first clamping diode, an emitter of the second triode is connected to a connecting line between the boost inductor and a collector of the third triode, an emitter of the third triode is connected to a connecting line between the other end of the clamping capacitor, an anode of the second clamping diode and a collector of the fourth power switch tube, and an emitter of the fourth triode is connected to a connecting line between a cathode of the direct current power supply, an other end of the first output bus filter capacitor and a cathode of the output end of the bus.
5. The power topology of claim 4, wherein said drive unit further comprises a first diode, a second diode, a third diode, and a fourth diode, wherein an anode of said first diode is connected to an emitter of said first transistor, a cathode of said first diode is connected to a collector of said first transistor, an anode of said second diode is connected to an emitter of said second transistor, an anode of said third diode is connected to an emitter of said third transistor, a cathode of said third diode is connected to a collector of said third transistor, an anode of said fourth diode is connected to an emitter of said fourth transistor, and a cathode of said fourth diode is connected to a collector of said fourth transistor.
6. A control device for a power topology circuit, characterized by being configured to control the power topology circuit according to any one of claims 1 to 5, the control device for a power topology circuit comprising:
the acquisition unit is used for respectively acquiring a first driving time sequence, a second driving time sequence, a third driving time sequence and a fourth driving time sequence which correspond to the first power switch tube, the second power switch tube, the third power switch tube and the fourth power switch tube in the driving unit;
And the switching tube driving unit is used for outputting a first driving signal, a second driving signal, a third driving signal and a fourth driving signal based on the first driving time sequence, the second driving time sequence, the third driving time sequence and the fourth driving time sequence so as to drive the first power switching tube, the second power switching tube, the third power switching tube and the fourth power switching tube to be turned on or off, so that the discharge charge quantity of the clamping capacitor to the bus output end in each period is equal to the charge quantity of the first output bus filter capacitor in each period, and the potential of a bus center node is kept unchanged so as to control the bus output end to output stable voltage.
7. The control device of the power topology circuit of claim 6, wherein the first driving signal and the second driving signal are both high level on the entire control time axis, so that the first power switching tube and the second power switching tube are in a normally-on state;
in the initial state of each period, the third driving signal and the fourth driving signal are both in a low level, so that the third power switching tube and the fourth power switching tube are both in a closed state;
In a first time period in each period, the third driving signal is at a high level, the fourth driving signal is at a low level, so that the third power switch tube is in an on state, and the fourth power switch tube is in an off state;
in a second time period in each period, the third driving signal and the fourth driving signal are both high level, so that the third power switching tube and the fourth power switching tube are both in an on state;
in a third time period in each period, the third driving signal is at a high level, the fourth driving signal is at a low level, so that the third power switch tube is in an on state, and the fourth power switch tube is in an off state;
in a fourth period of time in each cycle, the third driving signal and the fourth driving signal are at a low level, so that the third power switch tube and the fourth power switch tube are in a closed state until the next cycle arrives.
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| CN102158081A (en) * | 2011-04-07 | 2011-08-17 | 天津大学 | Three-level boosting DC converter and modulation method thereof |
| CN102510215A (en) * | 2011-11-17 | 2012-06-20 | 天津大学 | Three-level bidirectional direct-current converter and pulse width control method thereof |
| CN104052278A (en) * | 2013-03-15 | 2014-09-17 | 马克西姆综合产品公司 | Multi-level step-up converter topologies, control and soft start systems and methods |
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