CN111446286A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN111446286A
CN111446286A CN201910039185.XA CN201910039185A CN111446286A CN 111446286 A CN111446286 A CN 111446286A CN 201910039185 A CN201910039185 A CN 201910039185A CN 111446286 A CN111446286 A CN 111446286A
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fin
layer
forming
source
isolation
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CN111446286B (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, wherein a fin structure is arranged on the substrate, the fin structure comprises a bottom area and a top area positioned on the bottom area, and the top area comprises a plurality of layers of composite fin layers stacked along the normal direction of the surface of the substrate; forming a pseudo gate structure crossing the fin structure, wherein the pseudo gate structure covers part of the top surface and the side wall surface of the fin structure; forming source and drain openings in the bottom regions of the fin structures on two sides of the pseudo gate structure, wherein the source and drain openings are exposed out of the top surface of the bottom region of the fin structure; forming an isolation layer in the source drain opening, wherein the isolation layer covers part of the side wall of the top region of the fin structure; and forming a source-drain doping layer in the source-drain opening after the isolation layer is formed, wherein the source-drain doping layer covers the surface of the isolation layer and the surface of the side wall of the top region of the fin structure. The semiconductor structure formed by the method has better performance.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of integrated circuit manufacturing technology, the size of semiconductor devices in the integrated circuit is continuously reduced, so that the operation speed of the whole integrated circuit can be effectively increased. However, as the size of the device is further reduced, the control capability of the conventional planar MOS transistor for the channel current is weakened, and the Short Channel Effect (SCE) is becoming more serious. Fin field effect transistors (Fin FETs) are an emerging multi-gate device, and the gate of the Fin FET has good control capability on the channel and is widely used in the field of small size.
A semiconductor device having a gate-all-around Gate (GAA) structure is sought in the semiconductor industry because of its device performance and special performance of effectively controlling short channel effect.
However, the fully-wrapped-around gate device formed in the prior art has parasitic capacitance, leakage current is easy to occur, and the performance is still poor and needs to be further improved.
Disclosure of Invention
The invention provides a semiconductor device and a forming method thereof, which are used for improving the performance of the semiconductor device.
To solve the above technical problem, the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate is provided with a fin part structure, the fin part structure comprises a bottom area and a top area positioned on the bottom area, the top area comprises a plurality of layers of composite fin part layers stacked along the normal direction of the surface of the substrate, each composite fin part layer comprises a first fin part layer and a second fin part layer positioned on the surface of the first fin part layer, and the first fin part layer and the second fin part layer are made of different materials; forming a pseudo gate structure crossing the fin structure, wherein the pseudo gate structure covers part of the top surface and the side wall surface of the fin structure; forming source and drain openings in the bottom regions of the fin structures on two sides of the pseudo gate structure, wherein the source and drain openings are exposed out of the top surface of the bottom region of the fin structure; forming an isolation layer in the source drain opening, wherein the isolation layer covers part of the side wall of the top region of the fin structure; and forming a source-drain doping layer in the source-drain opening after the isolation layer is formed, wherein the source-drain doping layer covers the surface of the isolation layer and the surface of the side wall of the top region of the fin structure.
Optionally, the material of the isolation layer includes: silicon oxide, silicon nitride, silicon carbonitride, silicon carbide, aluminum oxide, hafnium oxide, silicon oxynitride, or silicon oxycarbide.
Optionally, the isolation layer is higher than or flush with a top surface of the first fin layer at the bottommost layer in the top region of the fin structure.
Optionally, the isolation layer is lower than or flush with a top surface of the second fin layer at a bottommost layer in the top region of the fin structure.
Optionally, the thickness of the isolation layer along the normal direction of the substrate surface is: 4 to 200 nanometers.
Optionally, the forming method of the isolation layer includes: forming an isolation material film on the top surface of the bottom region of the fin portion structure, the top surface and the side wall surface of the dummy gate structure and the side wall surface of the top region of the fin portion structure; after the isolation material film is formed, forming a sacrificial layer on the surface of the isolation material film, wherein the source drain opening is filled with the sacrificial layer, and the top surface of the sacrificial layer is flush with the top surface of the isolation material film; etching the isolation material film and the sacrificial layer covering the surface of the isolation material film until the isolation material film on the surface of the bottom area of the fin part structure is exposed to form the isolation layer; after the isolation layer is formed, the sacrificial layer is removed.
Optionally, the sacrificial layer is a bottom anti-reflective coating.
Optionally, a fin protection layer is disposed on the top of the fin structure.
Optionally, the isolation layer exposes sidewalls of the first fin layer in the at least one layer of top region; after the isolation layer is formed, before the source-drain doping layer is formed, the method further comprises the following steps: and removing part of the first fin portion layer exposed out of the side wall, and forming a first opening between the adjacent second fin portion layers.
Optionally, the method further includes: before forming a source-drain doped layer, an insulating layer is formed in the first opening, and the side wall of the insulating layer is flush with the side wall of the dummy gate structure.
Optionally, the material of the insulating layer includes silicon nitride or silicon oxynitride.
Optionally, the dimension of the insulating layer in the extending direction of the fin structure is: 2 to 5 nanometers.
Optionally, the method further includes: forming dielectric layers on the top surface of the isolation layer, the side wall and the top surface of the source drain doping layer and the side wall and the top surface of the dummy gate structure, wherein the top of the dielectric layer is exposed out of the top surface of the dummy gate structure; removing the pseudo gate structure, and forming a pseudo gate opening in the dielectric layer; after the pseudo gate opening is formed, removing the first fin portion layers, and forming a second opening between the adjacent second fin portion layers; and after removing the first fin portion layer, forming a grid electrode structure surrounding the second fin portion layer.
Accordingly, the present invention also provides a semiconductor structure comprising: the fin structure comprises a bottom area and a top area positioned on the bottom area, the top area comprises a plurality of layers of composite fin layers stacked along the normal direction of the surface of the substrate, each composite fin layer comprises a first fin layer and a second fin layer positioned on the surface of the first fin layer, and the first fin layer and the second fin layer are made of different materials; the dummy gate structure stretches across the fin structure, and covers the top surface and part of the side wall surface of the fin structure; the source and drain openings are positioned in the bottom regions of the fin structures on two sides of the pseudo gate structure and expose the top surfaces of the bottom regions of the fin structures; the isolation layer is positioned in the source drain opening and covers part of the side wall of the top area of the fin structure; and the source-drain doping layer is positioned in the source-drain opening and covers the surface of the isolation layer and the surface of the side wall of the top region of the fin structure.
Optionally, the material of the isolation layer includes: silicon oxide, silicon nitride, silicon carbonitride, silicon carbide, aluminum oxide, hafnium oxide, silicon oxynitride, or silicon oxycarbide.
Optionally, the isolation layer is higher than or flush with a top surface of the first fin layer at the bottommost layer in the top region of the fin structure.
Optionally, the isolation layer is lower than or flush with a top surface of the second fin layer at a bottommost layer in the top region of the fin structure.
Optionally, the thickness of the isolation layer along the normal direction of the substrate surface is: 4 to 200 nanometers.
Optionally, the method further includes: a first opening between adjacent second fin layers; and the side wall of the insulating layer is flush with the side wall of the dummy gate structure.
Optionally, the dimension of the insulating layer along the extending direction of the fin structure is 2 nm to 5 nm.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the forming method of the semiconductor structure provided by the technical scheme of the invention, an isolation layer is formed in the source drain opening, and the isolation layer covers part of the side wall of the top region of the fin structure; and forming a source-drain doping layer in the source-drain opening after the isolation layer is formed, wherein the source-drain doping layer covers the surface of the isolation layer and the surface of the side wall of the top region of the fin structure, so that the formed isolation layer is positioned between the source-drain doping layer and the bottom region of the fin structure. The isolation layer isolates the source-drain doping layer from the bottom region of the fin portion structure, so that parasitic devices are prevented from being formed in the subsequently formed grid structure, the source-drain doping layer and the bottom region of the fin portion structure, parasitic currents can be effectively prevented from being generated in the bottom region of the fin portion structure, and the formed semiconductor structure is good in performance.
Further, after the forming of the isolation layer and before the forming of the source drain doping layer, the method further includes: removing part of the first fin portion layers exposed out of the side walls, and forming first openings between the adjacent second fin portion layers; and forming an insulating layer in the first opening, wherein the side wall of the insulating layer is flush with the side wall of the dummy gate structure. The first fin portion layer is removed subsequently to form the gate structure, and the size of the insulating layer in the extending direction of the fin portion structure is larger, so that the distance between the subsequently formed gate structure and the source drain doping layer can be increased by the insulating layer, parasitic capacitance between the gate structure and the source drain doping layer is reduced, and performance of the semiconductor device is improved.
Drawings
FIG. 1 is a schematic diagram of a fully wrapped-around gate device;
fig. 2 to 12 are schematic structural diagrams of steps of a semiconductor structure forming process according to an embodiment of the invention.
Detailed Description
As described in the background, the performance of the semiconductor structure of the prior art fully-wrapped-around gate device is poor.
A fully wrapped around gate structure, referring to fig. 1, comprising: a substrate 100, wherein the substrate 100 has a fin structure (not shown in the figure), the fin structure includes a bottom region a and a top region B located on the bottom region a, the top region B includes a plurality of layers of composite fin layers 110 overlapped along a normal direction of a surface of the substrate 100, each composite fin layer 110 includes a first fin layer 111 and a second fin layer 112 located on a surface of the first fin layer 111, and materials of the first fin layer 111 and the second fin layer 112 are different; a dummy gate structure 120 spanning the fin structure, the dummy gate structure 120 covering a portion of a top surface and a portion of a sidewall surface of the fin structure; the source-drain openings (not shown in the figure) located in the top regions B of the fin structures on both sides of the dummy gate structure 120 are located in the source-drain doping layer 130 in the source-drain openings.
In the fully-surrounded gate device, the dummy gate structure 120 covers a part of the top surface and a part of the sidewall surface of the fin structure, and the dummy gate junction 120 and each layer of the first fin layer 111 exposed after the dummy gate structure 120 is removed are subsequently removed to form a gate structure. The gate structure of the partial structure surrounding each second fin layer 112 instead of the first fin layer 111, the bottom region a of the fin structure, and the source-drain doping layer 130 form a parasitic device, and then a parasitic current is generated in the bottom region a of the fin structure, so that the performance of the fully-surrounded gate structure is poor.
In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, which comprises the following steps: forming source and drain openings in the bottom regions of the fin structures on two sides of the pseudo gate structure, wherein the source and drain openings are exposed out of the top surface of the bottom region of the fin structure; forming an isolation layer in the source drain opening, wherein the isolation layer covers the side wall of the top region of the fin structure; and forming a source-drain doping layer in the source-drain opening after the isolation layer is formed, wherein the source-drain doping layer covers the surface of the isolation layer and the surface of the side wall of the top region of the fin structure. The semiconductor structure formed by the method has better performance.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 12 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 2, an initial substrate 200 is provided; multiple stacked fin material units (not shown) are formed on the surface of the initial substrate 200, each fin material unit includes a first fin material layer 201 and a second fin material layer 202 located on the surface of the first fin material layer 201, and the second fin material layer 202 is made of a different material from the first fin material layer 201.
In this embodiment, the material of the initial substrate 200 is silicon. The cost of silicon is low, which is beneficial to reducing the manufacturing cost of the semiconductor device.
In other embodiments, the material of the initial substrate comprises germanium or silicon germanium.
A portion of the initial substrate 200 is used for a subsequent formation of the substrate, and a portion of the initial substrate 200, the first fin material layer 201, and the second fin material layer 202 are used for a subsequent formation of the fin structure. Wherein, a part of the initial substrate 200 is used for forming a bottom region of the fin structure subsequently, the first fin material layer 201 is used for forming a first fin layer in the composite fin layer of the top region, and the second fin material layer 202 is used for forming a second fin layer in the composite fin layer of the top region.
The alternating stacking of the first fin material layer 201 and the second fin material layer 202 means that: because the first fin material layer 201 and the second fin material layer 202 are made of different materials, the first fin material layer 201 is used for forming a first fin layer in a subsequent step, and the second fin material layer 202 is used for forming a second fin layer in a subsequent step, the first fin layer is removed in the subsequent step, so that a suspended second fin layer is formed, and a gate structure surrounding the second fin is formed.
The first fin material layer 201 and the second fin material layer 202 are made of different materials, and the first fin material layer 201 and the second fin material layer 202 have different etching selection ratios, so that the second fin layer is less damaged when a part of the first fin layer is removed subsequently.
In this embodiment, the material of the initial substrate 200 and the material of the second fin material layer 202 are silicon, and the material of the first fin material layer 202 is silicon germanium.
In other embodiments, the material of the first fin material layer includes: silicon carbide, the material of the second fin material layer comprising: group III-V elements, InGaAs, or germanium.
The fin material unit has a fin protection layer (not shown) on a top surface thereof.
The fin portion protection layer is used for protecting the top of the fin portion structure when the fin portion structure is formed through subsequent etching, and the influence of an etching process is avoided, so that the performance of the semiconductor structure is improved.
Referring to fig. 3 and 4, fig. 4 is a cross-sectional view of fig. 3 along a cutting line C-C1, and fig. 3 is a cross-sectional view of fig. 4 along a cutting line D-D1, wherein the initial substrate 200, the first fin material layer 201 and the second fin material layer 202 are patterned to form a substrate 203 and a fin structure (not shown) on the surface of the substrate 203.
Fig. 3 corresponds to the cross-sectional direction of fig. 2.
In this embodiment, the fin structure includes a bottom region a and a top region B located on the bottom region a, the fin structure top region B includes a plurality of layers of composite fin layers 210 stacked along a surface normal direction of the substrate 203, and each of the composite fin layers 210 includes a first fin layer 211 and a second fin layer 212 located on a surface of the first fin layer 211.
The method for forming the substrate 203 and the fin structure comprises the following steps: forming a first mask layer (not shown) on top of the multi-layer stacked fin material units, the first mask layer exposing top surfaces of portions of the multi-layer stacked fin material units; and etching the fin material unit and part of the substrate 200 by taking the first mask layer as a mask to form a substrate 203 and a fin structure positioned on the surface of the substrate 203.
The material of the first mask layer comprises silicon nitride or titanium nitride. The first mask layer is used as a mask for forming the substrate 203 and the fin structure.
The process for etching the fin material unit and part of the substrate 200 by using the first mask layer as a mask comprises the following steps: one or two of the dry etching process and the wet etching process are combined.
Each composite fin portion layer 210 includes a first fin portion layer 211 formed by the first fin portion material layer 201 and a second fin portion layer 212 formed by the second fin portion material layer 202, and therefore, the materials of the first fin portion layer 211 and the second fin portion layer 212 are different, so that in the process of subsequently removing the first fin portion layer 211, the damage to the second fin portion layer 212 is small, and the performance of the semiconductor device is improved.
The surface of the substrate 203 further has an isolation structure 220, the top of the isolation structure 220 is lower than the top of the fin structure, and the isolation structure 220 covers the sidewalls of the bottom region a of all or part of the fin structure.
The material of the isolation structure 220 includes silicon oxide or silicon oxynitride.
The isolation structure 220 is used to achieve electrical isolation between semiconductor devices.
Referring to fig. 5, a dummy gate structure 230 is formed across the fin structure.
The dummy gate structure 230 includes a dummy gate dielectric layer 231 covering the top and sidewall surfaces of the top region B of the fin structure, a dummy gate layer 232 on the surface of the dummy gate dielectric layer 231, and a sidewall structure 233 on the sidewalls of the dummy gate dielectric layer 231 and the dummy gate layer 232.
The material of the dummy gate dielectric layer 231 comprises silicon oxide, and the material of the dummy gate layer 232 comprises silicon.
The sidewall structure 233 includes a first sidewall (not shown) on the sidewalls of the dummy gate dielectric layer 231 and the dummy gate layer 232 and a second sidewall (not shown) on the sidewall of the first sidewall. The first side wall is made of silicon nitride or silicon oxynitride, and the second side wall is made of silicon nitride or silicon oxynitride.
The sidewall structures 233 are used to define the positions of subsequent source and drain openings.
Referring to fig. 6, a source/drain opening 240 is formed in the top region B of the fin structure at two sides of the dummy gate structure 230 by using the dummy gate structure 230 as a mask.
The forming process of the source/drain opening 240 includes: one or two of the dry etching process and the wet etching process are combined.
Since the source/drain opening 240 is located in the top region B, the first fin layer 211 and the second fin layer 212 are exposed on the sidewall of the source/drain opening 240, which is beneficial to removing a portion of the first fin layer 211 subsequently, and forming a first opening between adjacent second fin layers 212.
The source and drain openings 240 are used for subsequently accommodating source and drain doped layers.
After the source and drain openings are formed, an isolation layer is formed in the source and drain openings, and the isolation layer covers part of the side wall of the top region of the fin structure, and a method for forming the isolation layer is described with reference to fig. 7 to 9.
Referring to fig. 7, after the source/drain openings 240 are formed, an isolation material film 251 is formed on the top surface of the bottom region a of the fin structure, the top surface and the sidewall surface of the dummy gate structure 230, and the sidewall surface of the top region B of the fin structure.
The material of the release material film 251 includes: silicon oxide, silicon nitride, silicon carbonitride, silicon carbide, aluminum oxide, hafnium oxide, silicon oxynitride, or silicon oxycarbide.
In this embodiment, the isolation material film is made of silicon oxide, and correspondingly, the isolation layer to be formed subsequently is made of silicon oxide.
The formation process of the isolation material film 251 includes: a chemical vapor deposition process or a physical vapor deposition process.
The isolation material film 251 is used for the subsequent formation of an isolation layer.
Referring to fig. 8, after the isolation material film 251 is formed, a sacrificial layer 252 is formed on the surface of the isolation material film 251, the source/drain openings 240 are filled with the sacrificial layer 252, and the top surface of the sacrificial layer 252 is flush with the top surface of the isolation material film 251.
In this embodiment, the sacrificial layer 252 is a bottom anti-reflective coating.
The forming process of the sacrificial layer comprises the following steps: and (4) spin coating.
The sacrificial layer 252 formed by the spin coating process has a smooth surface, which is beneficial to removing the sacrificial layer and part of the isolation material film by the subsequent etching process to form an isolation layer with a smooth surface.
Referring to fig. 9, the isolation material film 251 and the sacrificial layer 252 covering the surface of the isolation material film 251 are removed until the isolation material film 251 on the surface of the bottom region a of the fin structure is exposed, and the isolation layer 250 is formed.
The process of removing the isolation material film 251 and the sacrificial layer 252 covering the surface of the isolation material film 251 includes: one or two of the dry etching process and the wet etching process are combined.
In this embodiment, the etching process is a dry etching process. The parameters of the dry etching process comprise: the etching gas used includes: CH (CH)4And CHF3Said CH4The flow rate of (1) is 8 to 600 standard ml/min, the CHF3The flow rate is 30-500 standard ml/min, the radio frequency power is 100-1300 w, the time is 5-500 s, the direct current power supply is 80-500 v, and the pressure is 10-2000 mTorr.
The isolation layer 250 formed by the etching process has a flat plane, so that a good isolation effect is achieved between a source-drain doping layer and a bottom area A of the fin structure formed subsequently, parasitic capacitance can be avoided, and the performance of the semiconductor structure is improved.
The isolation layer 250 is higher than or flush with the top surface of the bottommost first fin layer 211 in the top region a of the fin structure.
The isolation layer 250 is lower than or flush with the top surface of the second bottom fin layer 212 in the top region a of the fin structure.
In the present embodiment, the isolation layer 250 is higher than the top surface of the first fin layer 211 at the bottom layer of the top region a of the fin structure, and lower than the top surface of the second fin layer 212 at the bottom layer of the top region a of the fin structure.
In other embodiments, the isolation layer is flush with a top surface of the first bottom fin layer in the top region of the fin structure.
In another embodiment, the isolation layer is flush with a top surface of a second bottommost fin layer in a top region of the fin structure.
The isolation layer 250 isolates the source-drain doping layer formed subsequently from the bottom area A of the fin structure, so that parasitic devices formed by the gate structure, the source-drain doping layer and the bottom area A of the fin structure formed subsequently are avoided, parasitic currents generated in the bottom area A of the fin structure can be effectively avoided, and the formed semiconductor structure has good performance.
The thickness of the isolation layer 250 along the normal direction of the substrate surface is: 4 to 200 nanometers.
The thickness is chosen in the sense that: if the thickness of the isolation layer 250 is greater than 200 nm, the space occupied by the thicker isolation layer 250 is larger, and the isolation layer covers not only the sidewall of the first fin layer 211 at the bottommost layer, but also the sidewall of the second fin layer 212 at the bottommost layer, so that the subsequent formation of a source-drain doping layer is influenced, and the performance of the formed semiconductor structure is still poorer; if the thickness of the isolation layer is less than 4 nanometers, the effect of the thinner isolation layer 250 in isolating the source-drain doping layer from the bottom area a of the fin structure is smaller, so that parasitic devices cannot be prevented from being formed in the subsequently formed gate structure, the source-drain doping layer and the bottom area a of the fin structure, parasitic current still can be generated in the bottom area a of the fin structure, and the performance of the formed semiconductor structure is poor.
Referring to fig. 10, a portion of the first fin layer 211 exposing the sidewalls is removed, and a first opening 260 is formed between adjacent second fin layers 212.
The process of removing the portion of the first fin layer 211 exposing the sidewalls includes: one or two of the dry etching process and the wet etching process are combined.
In this embodiment, the etching process is a wet etching process. The parameters of the wet etching process comprise: the etchant comprises dilute hydrochloric acid, the volume concentration of the etchant is 20-90%, and the temperature is 25-300 ℃.
Since the first fin layer 211 and the second fin layer 212 are made of different materials, the etchant has different etching selectivity for the first fin layer 211 and the second fin layer 212, and the removal rate of the etchant for the first fin layer 211 is far greater than that for the second fin layer 212, so that the second fin layer 212 is less damaged after the first opening is formed.
The dimension of the first opening 260 along the extending direction of the fin structure is: 2 to 5 nanometers.
The significance of the selection of the dimensions for the first opening 260 is: the first opening 260 is used for accommodating an insulating layer in a subsequent process, and if the size of the first opening is larger than 5 nanometers, the space occupied by the insulating layer formed in the subsequent process is too large, so that the space of the first fin portion layer is smaller, and the space where the first fin portion layer is located is used for forming a gate structure in the subsequent process. After the first fin portion layers are removed, second openings formed between adjacent second fin portion layers are large, and the second openings are not beneficial to forming of grid electrode structures surrounding the second fin portion layers; if the size of the first opening is smaller than 2 nanometers, the size of the subsequently formed insulating layer in the extending direction of the fin structure is smaller, the subsequent source-drain doped layer is closer to the channel, the parasitic capacitance between the source-drain doped layer and the channel is not reduced, and the performance of the formed semiconductor structure is poorer.
The first opening 210 is used for subsequently accommodating an insulating layer.
Referring to fig. 11, an insulating layer 270 is formed in the first opening 260 (shown in fig. 10), and sidewalls of the insulating layer 270 are flush with sidewalls of the dummy gate structure 230.
The material of the insulating layer 270 includes: silicon nitride or silicon oxynitride.
The method for forming the insulating layer 270 includes: forming an insulating material film (not shown in the figure) on the surface of the isolation layer 250, the side walls and the bottom surfaces of the source drain openings 240, the first openings 260, and the side walls and the top surfaces of the dummy gate structures 230; and removing the insulating material film on the surface of the isolation layer 250, the side wall and the bottom surface of the source-drain opening 240, and the side wall and the top surface of the dummy gate structure 230, and forming the insulating layer 270 in the first opening 260.
The dimension of the insulating layer 270 along the extending direction of the fin structure is: 2 to 5 nanometers.
The forming process of the insulating material film comprises a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.
Because the first fin layer 270 is subsequently removed to form the gate structure, and the dimension of the insulating layer 270 in the extending direction of the fin structure is larger, the insulating layer 270 can increase the distance between the subsequently formed gate structure and the source-drain doping layer, thereby being beneficial to reducing the parasitic capacitance between the gate structure and the source-drain doping layer, and improving the performance of the semiconductor device.
Referring to fig. 12, after the insulating layer 270 is formed, a source-drain doping layer 280 is formed in the source-drain opening 240 (shown in fig. 9).
The method for forming the source-drain doping layer 280 includes: forming an epitaxial layer in the source-drain opening 240; source and drain ions are doped in the epitaxial layer to form a source and drain doped layer 280.
The material of the epitaxial layer and the conductivity type of the source and drain ions are related to the type of the transistor. In this embodiment, the transistor is an NMOS transistor, the material of the epitaxial layer includes silicon carbide or silicon, and the source-drain ions are N-type ions, such as: phosphorus ions or arsenic ions. In other embodiments, the transistor is a PMOS transistor, the material of the epitaxial layer includes silicon germanium or silicon, and the source and drain ions are P-type ions, such as: boron ions.
The epitaxial layer forming process comprises an epitaxial growth process.
After the source-drain doping layer 280 is formed, the forming method further includes: forming dielectric layers on the top surface of the isolation layer 250, the side wall and the top surface of the source-drain doping layer 280 and the side wall and the top surface of the dummy gate structure 230, wherein the top of the dielectric layers is exposed out of the top surface of the dummy gate structure; removing the pseudo gate structure, and forming a pseudo gate opening in the dielectric layer; after the dummy gate opening is formed, removing the first fin portion layer 211, and forming a second opening between the adjacent second fin portion layers 212; after removing the first fin layer 211, a gate structure surrounding the second fin layer 212 is formed in the second opening.
Accordingly, the present invention further provides a semiconductor structure formed by the above method, referring to fig. 12, including: the semiconductor device comprises a substrate 200, wherein a fin structure is arranged on the substrate 200, the fin structure comprises a bottom area A and a top area B positioned on the bottom area A, the top area B comprises a plurality of layers of composite fin layers 210 stacked along the normal direction of the surface of the substrate 200, the composite fin layers 210 respectively comprise a first fin layer 211 and a second fin layer 212 positioned on the surface of the first fin layer 211, the first fin layer 211 and the second fin layer 212 are made of different materials and cross over a pseudo gate structure 230 of the fin structure, and the pseudo gate structure 230 covers the top surface and part of the side wall surface of the fin structure; source and drain openings in the bottom regions of the fin structures on both sides of the dummy gate structure 230, the source and drain openings exposing the top surface of the bottom region a of the fin structure; the isolation layer 250 is positioned in the source drain opening 240, and the isolation layer 250 covers the side wall of the top region of the fin structure; and the source and drain doping layer 280 is positioned in the source and drain opening 240, and the source and drain doping layer 280 covers part of the surface of the isolation layer 250 and the surface of the sidewall of the top region B of the fin structure.
The following detailed description is made with reference to the accompanying drawings.
The material of the isolation layer 250 includes: silicon oxide, silicon nitride, silicon carbonitride, silicon carbide, aluminum oxide, hafnium oxide, silicon oxynitride, or silicon oxycarbide.
The isolation layer 250 is higher than or flush with the top surface of the first fin layer 211 at the bottommost layer in the top region B of the fin structure.
The isolation layer 250 is lower than or flush with the top surface of the second fin layer 212 at the lowest layer in the top region B of the fin structure.
In the present embodiment, the isolation layer 250 is higher than the top surface of the first fin layer 211 at the bottom layer in the top region B of the fin structure, and lower than the top surface of the second fin layer 212 at the bottom layer in the top region B of the fin structure.
In other embodiments, the isolation layer is flush with the top surface of the first fin portion of the bottommost layer in the top region.
In yet another embodiment, the isolation layer is flush with the top surface of the first fin portion of the bottommost layer in the top region.
The thickness of the isolation layer 250 along the normal direction of the surface of the substrate 200 is: 4 to 200 nanometers.
In this embodiment, the semiconductor structure further includes: first openings 260 (not shown) between adjacent second fin layers 212; an insulating layer 270 located in the first opening 260, wherein sidewalls of the insulating layer 270 are flush with sidewalls of the dummy gate structure 230.
The dimension of the insulating layer 270 along the extending direction of the fin structure is: 2 to 5 nanometers.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a fin part structure, the fin part structure comprises a bottom area and a top area positioned on the bottom area, the top area comprises a plurality of layers of composite fin part layers stacked along the normal direction of the surface of the substrate, each composite fin part layer comprises a first fin part layer and a second fin part layer positioned on the surface of the first fin part layer, and the first fin part layer and the second fin part layer are made of different materials;
forming a pseudo gate structure crossing the fin structure, wherein the pseudo gate structure covers part of the top surface and the side wall surface of the fin structure;
forming source and drain openings in the bottom regions of the fin structures on two sides of the pseudo gate structure, wherein the source and drain openings are exposed out of the top surface of the bottom region of the fin structure;
forming an isolation layer in the source drain opening, wherein the isolation layer covers part of the side wall of the top region of the fin structure;
and forming a source-drain doping layer in the source-drain opening after the isolation layer is formed, wherein the source-drain doping layer covers the surface of the isolation layer and the surface of the side wall of the top region of the fin structure.
2. The method of forming a semiconductor structure of claim 1, wherein the isolation layer comprises a material comprising: silicon oxide, silicon nitride, silicon carbonitride, silicon carbide, aluminum oxide, hafnium oxide, silicon oxynitride, or silicon oxycarbide.
3. The method of forming a semiconductor structure of claim 1, wherein the isolation layer is above or flush with a top surface of a first bottommost fin layer in a top region of the fin structure.
4. The method of forming a semiconductor structure of claim 3, wherein the isolation layer is below or flush with a top surface of a second bottommost fin layer in a top region of the fin structure.
5. The method for forming a semiconductor structure according to claim 1 or 4, wherein the thickness of the isolation layer in the direction of the normal to the substrate surface is: 4 to 200 nanometers.
6. The method of forming a semiconductor structure of claim 1, wherein the spacer layer comprises: forming an isolation material film on the top surface of the bottom region of the fin portion structure, the top surface and the side wall surface of the dummy gate structure and the side wall surface of the top region of the fin portion structure; after the isolation material film is formed, forming a sacrificial layer on the surface of the isolation material film, wherein the source drain opening is filled with the sacrificial layer, and the top surface of the sacrificial layer is flush with the top surface of the isolation material film; etching the isolation material film and the sacrificial layer covering the surface of the isolation material film until the isolation material film on the surface of the bottom area of the fin part structure is exposed to form the isolation layer; after the isolation layer is formed, the sacrificial layer is removed.
7. The method of forming a semiconductor structure of claim 6, wherein the sacrificial layer is a bottom anti-reflective coating.
8. The method of forming a semiconductor structure of claim 1, wherein a fin protection layer is on top of the fin structure.
9. The method of forming a semiconductor structure of claim 1, wherein the isolation layer exposes sidewalls of the first fin layer in at least one top region; after the isolation layer is formed, before the source-drain doping layer is formed, the method further comprises the following steps: and removing part of the first fin portion layer exposed out of the side wall, and forming a first opening between the adjacent second fin portion layers.
10. The method of forming a semiconductor structure of claim 9, further comprising: before forming a source-drain doped layer, an insulating layer is formed in the first opening, and the side wall of the insulating layer is flush with the side wall of the dummy gate structure.
11. The method of forming a semiconductor structure of claim 10, wherein a material of the insulating layer comprises silicon nitride or silicon oxynitride.
12. The method of forming a semiconductor structure of claim 11, wherein a dimension of the insulating layer along an extension direction of the fin structure is: 2 to 5 nanometers.
13. The method of forming a semiconductor structure of claim 1, further comprising: forming dielectric layers on the top surface of the isolation layer, the side wall and the top surface of the source drain doping layer and the side wall and the top surface of the dummy gate structure, wherein the top of the dielectric layer is exposed out of the top surface of the dummy gate structure; removing the pseudo gate structure, and forming a pseudo gate opening in the dielectric layer; after the pseudo gate opening is formed, removing the first fin portion layers, and forming a second opening between the adjacent second fin portion layers; and after the first fin portion layer is removed, a grid electrode structure surrounding the second fin portion layer is formed in the second opening.
14. A semiconductor structure, comprising:
the fin structure comprises a bottom area and a top area positioned on the bottom area, the top area comprises a plurality of layers of composite fin layers stacked along the normal direction of the surface of the substrate, each composite fin layer comprises a first fin layer and a second fin layer positioned on the surface of the first fin layer, and the first fin layer and the second fin layer are made of different materials;
the dummy gate structure stretches across the fin structure, and covers part of the top surface and the side wall surface of the fin structure;
the source and drain openings are positioned in the bottom regions of the fin structures on two sides of the pseudo gate structure and expose the top surfaces of the bottom regions of the fin structures;
the isolation layer is positioned in the source drain opening and covers part of the side wall of the top area of the fin structure;
and the source-drain doping layer is positioned in the source-drain opening and covers the surface of the isolation layer and the surface of the side wall of the top region of the fin structure.
15. The semiconductor structure of claim 14, wherein the isolation layer comprises a material comprising: silicon oxide, silicon nitride, silicon carbonitride, silicon carbide, aluminum oxide, hafnium oxide, silicon oxynitride, or silicon oxycarbide.
16. The semiconductor structure of claim 14, wherein the isolation layer is above or flush with a top surface of a first bottommost fin layer in a top region of the fin structure.
17. The semiconductor structure of claim 16, wherein the isolation layer is below or flush with a top surface of a second bottommost fin layer in a top region of the fin structure.
18. The semiconductor structure of claim 14, wherein the thickness of the isolation layer along the normal to the substrate surface is: 4 to 200 nanometers.
19. The semiconductor structure of claim 14, further comprising: a first opening between adjacent second fin layers; and the side wall of the insulating layer is flush with the side wall of the dummy gate structure.
20. The semiconductor structure of claim 19, wherein a dimension of the insulating layer along an extension direction of the fin structure is: 2 to 5 nanometers.
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CN108321202A (en) * 2017-01-18 2018-07-24 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN109103102A (en) * 2017-06-20 2018-12-28 中芯国际集成电路制造(北京)有限公司 Semiconductor structure and forming method thereof
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Publication number Priority date Publication date Assignee Title
US20170069481A1 (en) * 2015-09-04 2017-03-09 International Business Machines Corporation Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer
CN108321202A (en) * 2017-01-18 2018-07-24 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
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