CN111445849A - Array substrate, electroluminescent display panel and display device - Google Patents
Array substrate, electroluminescent display panel and display device Download PDFInfo
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- CN111445849A CN111445849A CN202010364864.7A CN202010364864A CN111445849A CN 111445849 A CN111445849 A CN 111445849A CN 202010364864 A CN202010364864 A CN 202010364864A CN 111445849 A CN111445849 A CN 111445849A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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Abstract
The invention discloses an array substrate, an electroluminescent display panel and a display device, which comprise a plurality of sub-pixels arranged in an array, wherein in a column of sub-pixels, for at least two adjacent sub-pixels, the first end of an anode reset transistor in a pixel circuit of a previous row of sub-pixels is electrically connected with the grid electrode of a driving transistor in a pixel circuit of a next row of sub-pixels, so that signal lines in the array substrate are reduced, and the space utilization rate is improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, an electroluminescent display panel and a display device.
Background
An Organic light Emitting Diode (O L ED) panel has the characteristics of flexibility, high contrast, low power consumption and the like, and is widely concerned, wherein a pixel circuit is the core technical content of an O L ED panel, and has important research significance.
Disclosure of Invention
The embodiment of the invention provides an array substrate, an electroluminescent display panel and a display device, which can reduce wiring in the array substrate and improve the space utilization rate.
Therefore, an embodiment of the present invention provides an array substrate, including a plurality of sub-pixels arranged in an array; the sub-pixel includes a pixel circuit and a light emitting device;
the pixel circuit comprises a driving transistor and an anode reset transistor; the control end of the anode reset transistor is electrically connected with the scanning signal end, and the second end of the anode reset transistor is electrically connected with the anode of the light-emitting device;
in one column of the sub-pixels, for at least two adjacent sub-pixels, the first end of the anode reset transistor in the sub-pixel of the upper row is electrically connected with the gate of the drive transistor in the sub-pixel of the lower row.
Optionally, in one column of the sub-pixels, for every two adjacent sub-pixels, the first terminal of the anode reset transistor in the upper row of the sub-pixels is electrically connected to the gate of the driving transistor in the lower row of the sub-pixels.
Optionally, the array substrate further includes a plurality of reset signal lines, a plurality of scan signal lines, and an initialization signal line; wherein, one row of the sub-pixels corresponds to one scanning signal line and one reset signal line;
the control end of the anode reset transistor is electrically connected with the scanning signal line;
the pixel circuit further comprises a reset transistor, wherein a first end of the reset transistor is electrically connected with the initialization signal line, a control end of the reset transistor is electrically connected with the reset signal line, and a second end of the reset transistor is electrically connected with the grid electrode of the driving transistor.
Optionally, in one column of the sub-pixels, for two adjacent sub-pixels, the scanning signal line corresponding to the sub-pixel in the upper row is electrically connected to the reset signal line corresponding to the sub-pixel in the lower row.
Optionally, the array substrate further includes a plurality of data signal lines; the pixel circuit further comprises a data writing transistor, wherein a first end of the data writing transistor is electrically connected with the data signal line, a control end of the data writing transistor is electrically connected with the scanning signal line, and a second end of the data writing transistor is electrically connected with the first pole of the driving transistor; and one column of the sub-pixels is correspondingly and electrically connected with one data signal line.
Optionally, a plurality of connecting lines is further included;
and the first end of the anode reset transistor in the sub-pixel of the upper row is electrically connected with the grid electrode of the driving transistor in the sub-pixel of the lower row through one connecting wire.
Optionally, the pixel circuit further comprises: the circuit comprises a first switching transistor, a second switching transistor, a third switching transistor and a storage capacitor; wherein:
a first end of the first switching transistor is electrically connected with a first power supply end, a control end of the first switching transistor is electrically connected with a light-emitting control signal end, and a second end of the first switching transistor is electrically connected with a first electrode of the driving transistor;
a first end of the second switching transistor is electrically connected with a second electrode of the driving transistor, a control end of the second switching transistor is electrically connected with a light-emitting control signal end, and a second end of the second switching transistor is electrically connected with an anode of the light-emitting device;
a first terminal of the third switching transistor is electrically connected to the gate of the driving transistor, a control terminal of the third switching transistor is electrically connected to the scan signal line, and a second terminal of the third switching transistor is electrically connected to the first terminal of the driving transistor;
the first end of the storage capacitor is electrically connected with the first power supply end, and the second end of the storage capacitor is electrically connected with the grid electrode of the driving transistor.
Optionally, all transistors are P-type transistors; alternatively, all transistors are N-type transistors.
Based on the same inventive concept, the embodiment of the invention also provides an electroluminescent display panel, which comprises any one of the array substrates.
Based on the same inventive concept, the embodiment of the invention also provides a display device, which comprises the electroluminescent display panel.
The invention has the following beneficial effects:
the array substrate, the electroluminescent display panel and the display device provided by the embodiment of the invention comprise a plurality of sub-pixels which are arranged in an array manner, and in a column of sub-pixels, for at least two adjacent sub-pixels, the first end of an anode reset transistor in a pixel circuit of a previous row of sub-pixels is electrically connected with the grid electrode of a driving transistor in a pixel circuit of a next row of sub-pixels, so that the number of signal lines in the array substrate is reduced, and the space utilization rate is improved.
Drawings
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 4 is a timing diagram of signals of an array substrate according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. And the embodiments and features of the embodiments may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without any inventive step, are within the scope of protection of the invention.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connect" or "electrically connect," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
It should be noted that the sizes and shapes of the figures in the drawings are not to be considered true scale, but are merely intended to schematically illustrate the present invention. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.
The array substrate provided by the embodiment of the invention, as shown in fig. 1-3, comprises a plurality of sub-pixels P arranged in an array, wherein each sub-pixel P comprises a pixel circuit 100 and a light emitting device L;
the pixel circuit 100 includes a driving transistor DTFT and an anode reset transistor L R, a control terminal of the anode reset transistor L R is electrically connected to the scan signal terminal, and a second terminal of the anode reset transistor L R is electrically connected to the anode of the light emitting device L;
in one column of the sub-pixels P, for at least two adjacent sub-pixels P, the first terminal N2 of the anode reset transistor L R in the upper row of the sub-pixels P is electrically connected to the gate N1 of the driving transistor DTFT in the lower row of the sub-pixels P.
In the array substrate provided by the embodiment of the invention, in two adjacent sub-pixels P in a column of sub-pixels P, the first terminal N2 of the anode reset transistor L R in the upper row of sub-pixels P is electrically connected with the gate N1 of the driving transistor DTFT in the lower row of sub-pixels P, so that when the gate N1 of the driving transistor DTFT in the lower row of sub-pixels P is reset, the anode of the light emitting device L of the upper row of sub-pixels P is also reset, and thus, an additional signal line is not required to be arranged to provide a reset signal to the anode of the light emitting device L, and the number of signal lines in the array substrate is reduced.
Illustratively, the light Emitting device L may include at least one of an Organic L light Emitting diode (O L ED), a Quantum Dot light Emitting diode (Quantum Dot L light Emitting Diodes, Q L ED).
In specific implementation, as shown in fig. 1 to 3, the array substrate may further include a plurality of Reset signal lines Reset, a plurality of scan signal lines Gate, a plurality of Data signal lines Data, and a plurality of initialization signal lines Vinit, wherein one row of sub-pixels P is electrically connected to one scan signal line Gate, one Reset signal line Reset, and one initialization signal line Vinit, one column of sub-pixels P is electrically connected to one Data signal line Data, and the control terminal of the anode Reset transistor L R in the sub-pixel P is electrically connected to the corresponding scan signal line Gate.
In practical implementation, in the embodiment of the present invention, in a column of sub-pixels P, the first terminal N2 of the anode reset transistor L R in the sub-pixel P in the previous row may be set to be electrically connected to the gate N1 of the driving transistor DTFT in the sub-pixel P in the next row only for a part of the adjacent sub-pixels P, or the first terminal N2 of the anode reset transistor L R in the sub-pixel P in the previous row may be set to be electrically connected to the gate N1 of the driving transistor DTFT in the sub-pixel P in the next row for every two adjacent sub-pixels P in a column of sub-pixels P.
In specific implementation, as shown in fig. 2 and 3, in the embodiment of the present invention, the pixel circuit 100 may further include a Reset transistor R, a first terminal of the Reset transistor R is electrically connected to the initialization signal line Vinit, a control terminal of the Reset transistor R is electrically connected to a corresponding Reset signal line Reset, and a second terminal of the Reset transistor R is electrically connected to the Gate N1 of the driving transistor DTFT, when the Reset transistor R is turned on under the signal control of the Reset signal line Reset, the signal of the initialization signal line Vinit may be provided to the Gate N1 of the corresponding driving transistor DTFT, the Gate N1 of the driving transistor DTFT may be Reset, and the signal of the initialization signal line Vinit may be provided to the first terminal N2 of the anode Reset transistor L R in the previous row of sub-pixels P, so that the anode Reset transistor L R turned on under the signal control of the scan signal line Gate provides the signal of the initialization signal line Vinit to the anode of the light emitting device L, and the anode of the light emitting device L is Reset.
In practical implementation, as shown in fig. 2 and 3, one Reset signal line Reset may be electrically connected to one row of sub-pixels P, and the control terminal of the Reset transistor R in one row of sub-pixels P may be electrically connected to the Reset signal line Reset, in one column of sub-pixels P, for at least two adjacent sub-pixels P, the scan signal line Gate corresponding to the previous row of sub-pixels P may be electrically connected to the Reset signal line Reset corresponding to the next row of sub-pixels P, and the signal of the scan signal line Gate of the previous row of sub-pixels P is the same as the signal of the Reset signal line Reset of the next row of sub-pixels P, so that the anode Reset transistor L R in the previous row of sub-pixels P and the Reset transistor R in the next row of sub-pixels P may be turned on simultaneously.
In specific implementation, as shown in fig. 2 and fig. 3, in the embodiment of the present invention, the pixel circuit 100 may further include a Data writing transistor D, a first end of the Data writing transistor D is electrically connected to the Data signal line Data, a control end of the Data writing transistor D is electrically connected to the scan signal line Gate, and a second end of the Data writing transistor D is electrically connected to the first pole of the driving transistor DTFT; one column of sub-pixels is electrically connected with one data signal line correspondingly.
In practical implementation, as shown in fig. 3, the array substrate may further include a plurality of connection lines a, and the first terminal N2 of the anode reset transistor L R is electrically connected to the gate electrode N1 of the driving transistor DTFT in the next row of sub-pixels P through one connection line a.
In specific implementation, the positions of the connection lines a may be flexibly set according to actual conditions, for example, each connection line a and an active layer of a transistor may be set on the same layer and prepared by a one-time composition process, or each connection line a and a Data signal line Data may be set on the same layer and prepared by a one-time composition process, so that the occupied space of the signal lines may be reduced, and the space utilization rate of the array substrate may be improved. Of course, in practical applications, the position of each connecting line a may not be limited thereto, and is not limited thereto.
In a specific implementation, as shown in fig. 2 and 3, the pixel circuit 100 may further include a first switching transistor T1, a second switching transistor T2, a third switching transistor T3 and a storage capacitor Cst, wherein a first terminal of the first switching transistor T1 is electrically connected to the first power terminal E L VDD, a control terminal of the first switching transistor T1 is electrically connected to the emission control signal terminal EM, a second terminal of the first switching transistor T1 is electrically connected to the first terminal of the driving transistor DTFT, a first terminal of the second switching transistor T2 is electrically connected to the second terminal of the driving transistor DTFT, a control terminal of the second switching transistor T2 is electrically connected to the emission control signal terminal EM, a second terminal of the second switching transistor T2 is electrically connected to the anode of the light emitting device L, a first terminal of the third switching transistor T3 is electrically connected to the Gate N1 of the driving transistor DTFT, a control terminal of the third switching transistor T3 is electrically connected to the scanning signal line Gate EM, a second terminal of the third switching transistor T48 is electrically connected to the anode of the driving transistor DTFT 596, and the storage capacitor Cst is not limited to the reset transistor DTFT.
Specifically, in order to make the manufacturing process uniform, as shown in fig. 2 and 3, all the transistors in the array substrate provided in the embodiment of the present invention may be P-type transistors. Of course, all transistors may be N-type transistors, and are not limited herein.
Specifically, in the array substrate provided by the embodiment of the invention, the P-type transistor is turned on under the action of a low-level signal and is turned off under the action of a high-level signal; the N-type transistor is turned on under the action of a high-level signal and is turned off under the action of a low-level signal.
Specifically, in the array substrate provided in the embodiment of the present invention, each Transistor may be a Thin Film Transistor (TFT) or a Metal oxide semiconductor field effect Transistor (MOS), which is not limited herein. The control terminal of each transistor is used as the gate, the first terminal of the switching transistor is used as the source, and the second terminal of the switching transistor is used as the drain, or the first terminal of the switching transistor is used as the drain and the second terminal of the switching transistor is used as the source, according to the type of each transistor and the signal of the gate of each transistor, which is not particularly distinguished herein.
The present invention will be described in detail with reference to specific examples. It should be noted that the present embodiment is intended to better explain the present invention, but not to limit the present invention.
The operation of the array substrate according to the embodiment of the invention is described below with reference to a circuit timing diagram. In the following description, 1 represents a high level, and 0 represents a low level. It should be noted that 1 and 0 are logic levels, which are only used to better explain the specific operation of the embodiment of the present invention, and not specific voltage values.
The following describes the operation process of the array substrate provided by the embodiment of the present invention with reference to the signal timing diagram shown in fig. 4 by taking the array substrate shown in fig. 3 as an example. Specifically, three adjacent sub-pixels P (n-1), P (n +1) in a row of sub-pixels in the array substrate shown in fig. 3 are selected, wherein a row of sub-pixels where the sub-pixel P (n-1) is located is electrically connected to a Reset signal line Reset (n-1), a scanning signal line Gate (n-1), and a light emitting control signal line EM (n-1) correspondingly, a row of sub-pixels where the sub-pixel P (n) is located is electrically connected to a Reset signal line Reset (n), a scanning signal line Gate (n), and a light emitting control signal line EM (n) correspondingly, and a row of sub-pixels where the sub-pixel P (n +1) is located is electrically connected to a Reset signal line Reset (n +1), a scanning signal line Gate (n +1), and a light emitting control signal line EM (n +1) correspondingly. Five stages of the first stage t1, the second stage t2, the third stage t3, the fourth stage t4 and the fifth stage t5 in the signal timing diagram shown in fig. 4 are selected for description.
In the first stage t1, EM (n-1) is 1, Reset (n-1) is 0, Gate (n-1) is 1, EM (n) is 0, Reset (n) is 1, Gate (n) is 1, EM (n +1) is 0, Reset (n +1) is 1, and Gate (n +1) is 1.
Since the EM (N-1) is 1 and both the first switching transistor T1 and the second switching transistor T2 in the subpixel P (N-1) are turned off, the subpixel P (N-1) does not emit light, since the Gate (N-1) is 1, the data writing transistor D, the third switching transistor T3, and the anode Reset transistor L R in the subpixel P (N-1) are turned off, and since Reset (N-1) is 0, the Reset transistor R in the subpixel P (N-1) is turned on, and a signal of the initialization signal line Vinit is supplied to the Gate N1 of the driving transistor DTFT to Reset it.
Since EM (N) ═ 0 and EM (N +1) ═ 0, the sub-pixel P (N), and the sub-pixel P (N +1) each have on the first switching transistor T1 and the second switching transistor T2, and since Reset (N) ═ 1, the Reset transistor R in the sub-pixel P (N) is off, and since Reset (N +1) ═ 1, the Reset transistor R in the sub-pixel P (N +1) is off, and since Gate (N) ═ 1 and Gate (N +1) ═ 1, the sub-pixel P (N), and the data writing transistor D, the third switching transistor T3, and the anode Reset transistor L R in the sub-pixel P (N +1) are all off, the sub-pixel P (N) and the sub-pixel P (N +1) emit light under the control of the signal of the Gate N1 of the driving transistor DTFT.
In the second stage t2, EM (n-1) ═ 1, Reset (n-1) ═ 1, Gate (n-1) ═ 0, EM (n) ═ 1, Reset (n) ═ 0, Gate (n) ═ 1, EM (n +1) ═ 0, Reset (n +1) ═ 1, and Gate (n +1) ═ 1.
Since EM (N-1) is 1, and both the first switching transistor T1 and the second switching transistor T2 in the subpixel P (N-1) are turned off, the subpixel P (N-1) does not emit light, since Reset (N-1) is 1, the Reset transistor R in the subpixel P (N-1) is turned off, since Gate (N-1) is 0, the Data writing transistor D, the third switching transistor T3, and the anode Reset transistor L R in the subpixel P (N-1) are all turned on, the Data writing transistor D supplies a signal of the Data signal line Data to the first pole of the driving transistor DTFT, and the third switching transistor T3 turns on the Gate N1 and the second pole of the driving transistor DTFT, makes the driving transistor DTFT form a diode structure and discharges to the first pole of the driving transistor DTFT to write the signal of the Data signal line Data and the threshold voltage of the driving transistor DTFT to the Gate N1 of the driving transistor DTFT.
Since the first switching transistor T1 and the second switching transistor T2 in the sub-pixel P (N) are both off, the sub-pixel P (N) does not emit light, since reset (N) is 0, the reset transistor R in the sub-pixel P (N) is turned on, the turned-on reset transistor R supplies a signal of the initialization signal line Vinit to the gate N1 of the driving transistor DTFT, and supplies a signal of the initialization signal line Vinit to the first end N2 of the anode reset transistor L R in the sub-pixel P (N-1), the turned-on anode reset transistor L R in the sub-pixel P (N-1) supplies a signal of the initialization signal line Vinit to the anode of the light emitting device L to reset the anode of the light emitting device L, the data write transistor D, the third switching transistor T3, and the anode reset transistor R L R in the sub-pixel P (N) are all off, since gate (N) is 1.
Since EM (n +1) is 0, both the first switching transistor T1 and the second switching transistor T2 in the subpixel P (n +1) are turned on to emit light, since Reset (n +1) is 1, the Reset transistor R in the subpixel P (n +1) is turned off, and since Gate (n +1) is 1, the data writing transistor D, the third switching transistor T3, and the anode Reset transistor L R in the subpixel P (n +1) are turned off.
In the third stage t3, EM (n-1) ═ 0, Reset (n-1) ═ 1, Gate (n-1) ═ 1, EM (n) ═ 1, Reset (n) ═ 1, Gate (n) ═ 0, EM (n +1) ═ 1, Reset (n-1) ═ 0, and Gate (n +1) ═ 1.
Since EM (N-1) is 0, the first switching transistor T1 and the second switching transistor T2 in the subpixel P (N-1) are both turned on, since Gate (N-1) is 1, the data writing transistor D, the third switching transistor T3, and the anode Reset transistor L R in the subpixel P (N-1) are all turned off, and since Reset (N-1) is 1, the Reset transistor R in the subpixel P (N-1) is turned off, and then the subpixel P (N-1) emits light under the control of the voltage of the Gate N1 and the source voltage of the driving transistor DTFT.
Since the first switching transistor T1 and the second switching transistor T2 in the subpixel p (N) are both off, the subpixel p (N) does not emit light, and since reset (N) is 1, the reset transistor R in the subpixel p (N) is off, since gate (N) is 0, the Data writing transistor D, the third switching transistor T3, and the anode reset transistor L R in the subpixel p (N) are all on, the Data writing transistor D supplies a signal of the Data signal line Data to the first pole of the driving transistor DTFT, and the third switching transistor T3 turns on the gate N1 and the second pole of the driving transistor DTFT, so that the driving transistor DTFT forms a diode structure and discharges the Data to the first pole of the driving transistor DTFT to write the signal of the Data signal line Data and the threshold voltage of the driving transistor to the gate N1 of the driving transistor DTFT.
Since Reset (N-1) ═ 0, the Reset transistor R in the sub-pixel P (N +1) is turned on, the turned-on Reset transistor R supplies the signal of the initialization signal line Vinit to the gate N1 of the driving transistor DTFT, and the signal of the initialization signal line Vinit is supplied to the first terminal N2 of the anode Reset transistor L R in the sub-pixel P (N), the turned-on anode Reset transistor L R in the sub-pixel P (N) supplies the signal of the initialization signal line Vinit to the anode of the light emitting device L to Reset the anode of the light emitting device L.
In the fourth phase t4, EM (n-1) ═ 0, Reset (n-1) ═ 1, Gate (n-1) ═ 1, EM (n) ═ 0, Reset (n) ═ 1, Gate (n) ═ 1, EM (n +1) ═ 1, Reset (n +1) ═ 1, and Gate (n +1) ═ 0.
Since EM (N-1) is 0, the first switching transistor T1 and the second switching transistor T2 in the subpixel P (N-1) are both turned on, since Gate (N-1) is 1, the data writing transistor D, the third switching transistor T3, and the anode Reset transistor L R in the subpixel P (N-1) are all turned off, and since Reset (N-1) is 1, the Reset transistor R in the subpixel P (N-1) is turned off, and then the subpixel P (N-1) continues to emit light under the control of the voltage of the Gate N1 and the source voltage of the driving transistor DTFT.
Since the first switching transistor T1 and the second switching transistor T2 in the subpixel p (N) are both turned on because em (N) ═ 0, and the data writing transistor D, the third switching transistor T3, and the anode reset transistor L R in the subpixel p (N) are all turned off because gate (N) ═ 1, and the reset transistor R in the subpixel p (N) is turned off because reset (N) ═ 1, the subpixel p (N) emits light under the control of the voltage of the gate N1 and the source voltage of the driving transistor DTFT.
Since EM (N +1) is 1, the first switching transistor T1 and the second switching transistor T2 in the subpixel P (N +1) are both off, the subpixel P (N +1) does not emit light, since Reset (N +1) is 1, the Reset transistor R in the subpixel P (N +1) is off, since Gate (N +1) is 0, the Data writing transistor D, the third switching transistor T3, and the anode Reset transistor L R in the subpixel P (N +1) are all on, the Data writing transistor D supplies a signal of the Data signal line Data to the first pole of the driving transistor DTFT, and the third switching transistor T3 turns on the Gate N1 and the second pole of the driving transistor DTFT, causes the driving transistor DTFT to form a diode structure and discharge to the first pole of the driving transistor DTFT to write the signal of the Data signal line Data and the threshold voltage of the driving transistor DTFT to the Gate N1.
In the fifth stage t5, EM (n-1) is equal to 0, Reset (n-1) is equal to 1, Gate (n-1) is equal to 1, EM (n) is equal to 0, Reset (n) is equal to 1, Gate (n) is equal to 1, EM (n +1) is equal to 0, Reset (n +1) is equal to 1, and Gate (n +1) is equal to 1.
Since EM (N-1) ═ 0 and EM (N) ═ 0, the first switching transistor T1 and the second switching transistor T2 in the sub-pixels P (N-1), P (N) are all turned on, and since Gate (N-1) ═ 1 and Gate (N) ═ 1, the data writing transistor D, the third switching transistor T3, and the anode Reset transistor L R in the sub-pixels P (N-1), P (N) are all turned off, and since Reset (N-1) ═ 1, the Reset transistor R in the sub-pixel P (N-1) is turned off, and since Reset (N) ═ 1, the Reset transistor R in the sub-pixel P (N) is turned off, the sub-pixels P (N-1), P (N) continue to emit light under the control of the voltage of the Gate N1 and the source voltage of the driving transistor DTFT.
Since EM (N +1) is 0, the first switching transistor T1 and the second switching transistor T2 in the subpixel P (N +1) are both turned on, since Gate (N +1) is 1, the data writing transistor D, the third switching transistor T3, and the anode Reset transistor L R in the subpixel P (N +1) are all turned off, and since Reset (N +1) is 1, the Reset transistor R in the subpixel P (N +1) is turned off, and the subpixel P (N +1) emits light under the control of the voltage of the Gate N1 and the source voltage of the driving transistor DTFT.
Based on the same inventive concept, embodiments of the present invention provide an electroluminescent display panel, including any one of the array substrates described above. The implementation of the electroluminescent display panel can be seen in the above embodiments of the array substrate, and repeated descriptions are omitted.
Based on the same inventive concept, the embodiment of the invention further provides a display device, which comprises the electroluminescent display panel provided by the embodiment of the invention. The implementation of the display device can be seen in the above-mentioned embodiment of the electroluminescent display panel, and repeated descriptions are omitted.
In a specific implementation, the display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein or should not be construed as limiting the invention.
The array substrate, the electroluminescent display panel and the display device provided by the embodiment of the invention comprise a plurality of sub-pixels which are arranged in an array manner, and in a column of sub-pixels, for at least two adjacent sub-pixels, the first end of an anode reset transistor in a pixel circuit of a previous row of sub-pixels is electrically connected with the gate of a driving transistor in a pixel circuit of a next row of sub-pixels, so that signal lines in the array substrate are reduced, and the space utilization rate is improved.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. The array substrate is characterized by comprising a plurality of sub-pixels arranged in an array; the sub-pixel includes a pixel circuit and a light emitting device;
the pixel circuit comprises a driving transistor and an anode reset transistor; the control end of the anode reset transistor is electrically connected with the scanning signal end, and the second end of the anode reset transistor is electrically connected with the anode of the light-emitting device;
in one column of the sub-pixels, for at least two adjacent sub-pixels, the first end of the anode reset transistor in the sub-pixel of the upper row is electrically connected with the gate of the drive transistor in the sub-pixel of the lower row.
2. The array substrate of claim 1, wherein in a column of the subpixels, for every two adjacent subpixels, the first terminal of the anode reset transistor in an upper row of subpixels is electrically connected to the gate of the driving transistor in a lower row of subpixels.
3. The array substrate of claim 2, wherein the array substrate further comprises a plurality of reset signal lines, a plurality of scan signal lines, and initialization signal lines; wherein, one row of the sub-pixels corresponds to one scanning signal line and one reset signal line;
the control end of the anode reset transistor is electrically connected with the scanning signal line;
the pixel circuit further comprises a reset transistor, wherein a first end of the reset transistor is electrically connected with the initialization signal line, a control end of the reset transistor is electrically connected with the reset signal line, and a second end of the reset transistor is electrically connected with the grid electrode of the driving transistor.
4. The array substrate of claim 3, wherein in a column of the sub-pixels, for two adjacent sub-pixels, the scan signal line corresponding to the sub-pixel in the upper row is electrically connected to the reset signal line corresponding to the sub-pixel in the lower row.
5. The array substrate of claim 3, wherein the array substrate further comprises a plurality of data signal lines; the pixel circuit further comprises a data writing transistor, wherein a first end of the data writing transistor is electrically connected with the data signal line, a control end of the data writing transistor is electrically connected with the scanning signal line, and a second end of the data writing transistor is electrically connected with the first pole of the driving transistor; and one column of the sub-pixels is correspondingly and electrically connected with one data signal line.
6. The array substrate of claim 5, further comprising a plurality of connecting lines;
and the first end of the anode reset transistor in the sub-pixel of the upper row is electrically connected with the grid electrode of the driving transistor in the sub-pixel of the lower row through one connecting wire.
7. The array substrate of any one of claims 1-6, wherein the pixel circuit further comprises: the circuit comprises a first switching transistor, a second switching transistor, a third switching transistor and a storage capacitor; wherein:
a first end of the first switching transistor is electrically connected with a first power supply end, a control end of the first switching transistor is electrically connected with a light-emitting control signal end, and a second end of the first switching transistor is electrically connected with a first electrode of the driving transistor;
a first end of the second switching transistor is electrically connected with a second electrode of the driving transistor, a control end of the second switching transistor is electrically connected with a light-emitting control signal end, and a second end of the second switching transistor is electrically connected with an anode of the light-emitting device;
a first terminal of the third switching transistor is electrically connected to the gate of the driving transistor, a control terminal of the third switching transistor is electrically connected to the scan signal line, and a second terminal of the third switching transistor is electrically connected to the first terminal of the driving transistor;
the first end of the storage capacitor is electrically connected with the first power supply end, and the second end of the storage capacitor is electrically connected with the grid electrode of the driving transistor.
8. The array substrate of claim 7, wherein all of the transistors are P-type transistors; alternatively, all transistors are N-type transistors.
9. An electroluminescent display panel comprising the array substrate according to any one of claims 1 to 8.
10. A display device comprising the electroluminescent display panel according to claim 9.
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| CN202010364864.7A CN111445849A (en) | 2020-04-30 | 2020-04-30 | Array substrate, electroluminescent display panel and display device |
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