CN111443753A - Depletion tube reference circuit with soft start - Google Patents
Depletion tube reference circuit with soft start Download PDFInfo
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- CN111443753A CN111443753A CN202010258149.5A CN202010258149A CN111443753A CN 111443753 A CN111443753 A CN 111443753A CN 202010258149 A CN202010258149 A CN 202010258149A CN 111443753 A CN111443753 A CN 111443753A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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Abstract
The invention discloses a depletion tube reference circuit with soft start, which comprises a ramp voltage generating circuit, an error amplifier, a zeroth PMOS tube and a depletion tube reference voltage generating circuit. The ramp voltage generation circuit outputs a ramp voltage Vramp, the depletion tube reference voltage generation circuit outputs a reference voltage Vref, the inverting input end of the error amplifier is connected with the Vramp, the non-inverting input end of the error amplifier is connected with the Vref, the grid electrode of the zeroth PMOS tube is connected with the output end of the error amplifier, the source electrode of the zeroth PMOS tube is connected with a power supply, and the drain electrode of the zeroth PMOS tube is connected with the depletion tube reference voltage generation circuit. The invention can obtain the reference voltage with constant slope rising and avoid surge, and is an ideal reference voltage source of various voltage regulators.
Description
Technical Field
The invention belongs to the field of integrated circuits, and particularly relates to a reference circuit of a depletion transistor.
Background
The reference voltage source is an important unit circuit in IC design, and is widely used in various analog integrated circuits, digital integrated circuits, and digital-analog hybrid integrated circuits. With the development of integrated circuit technology, the requirements for a reference voltage source are higher and higher nowadays, and the reference voltage source is required to have low power consumption, low noise, low temperature coefficient, high PSRR, small layout area and the like. Although the reference voltage source has the advantages of simple structure, low power consumption, low noise, high PSRR, small layout area and the like compared with the traditional band-gap reference, the reference voltage source is more and more widely applied to various integrated circuits, especially various voltage regulators of a power management circuit.
The conventional depletion transistor reference voltage source is shown in fig. 1, and includes a depletion transistor DN0, an enhancement NMOS transistor N0, and a capacitor C0. Although the drain of DN0 is connected to VDD, the gate and the source of DN0 and the gate and the drain of N0 are connected together to form the output Vref of the depletion transistor reference generating circuit, Vref is connected to GND by capacitor C0, and the source of N0 is connected to GND. Although the output voltage Vref of the reference voltage source is shown in equation (1):
k in formula (1)DN0W/L, K is a depletion tube DN0N0W/L, V of enhanced NMOS transistor N0TNIs the threshold voltage, V, of the increasing type NMOS transistor N0TDAlthough the threshold voltage of DN0 is negative, because the threshold voltages of the enhancement NMOS and the depletion NMOS are negative temperature coefficients, the proper width-to-length ratio W/L is selected, and the difference between the two can offset the temperature coefficient, so as to obtain the reference voltage Vref with zero temperature coefficient.
The starting speed of the conventional depletion transistor reference circuit is very high, and the grid source short circuit V is caused by the loss although the threshold voltage of DN0 is a negative valueGSAt 0, even though DN0 is in the through state at the instant of power-on, when power supply VDD suddenly jumps from 0 to the operating voltage, Vref jumps directly along with VDD, and it is difficult to avoid surge of the reference voltage Vref during power-on. When the reference source Vref is used as a reference source for the voltage regulator, the output of the voltage regulator is prone to generate higher surge, which may cause abnormal operation or even damage of a system powered by the output of the voltage regulator.
Therefore, how to improve the conventional reference circuit structure, control the rising rate of the reference voltage, and avoid the generation of surge is a problem to be solved.
Disclosure of Invention
In order to solve the technical problems mentioned in the background technology, the invention provides a depletion transistor reference circuit with soft start.
In order to achieve the technical purpose, the technical scheme of the invention is as follows:
a depletion tube reference circuit with soft start comprises a ramp voltage generating circuit, an error amplifier, a zeroth PMOS tube and a depletion tube reference voltage generating circuit; the ramp voltage generation circuit outputs a ramp voltage Vramp, the reference voltage generation circuit outputs a reference voltage Vref, the inverting input end of the error amplifier is connected to the Vramp, the non-inverting input end of the error amplifier is connected to the Vref, the grid electrode of the zeroth PMOS tube is connected to the output end of the error amplifier, the source electrode of the zeroth PMOS tube is connected to the power supply, and the drain electrode of the zeroth PMOS tube is connected to the reference voltage generation circuit.
Further, the ramp voltage generating circuit includes a current source and a first capacitor; one end of the current source is connected with the power supply, the other end of the current source is connected with the anode of the first capacitor, and the cathode of the first capacitor is grounded; the current source charges the first capacitor with a constant current to generate a ramp voltage Vramp.
Further, the depletion tube reference voltage generating circuit comprises a zeroth depletion type NMOS tube, a zeroth enhancement type NMOS tube and a zeroth capacitor; the drain electrode of the zeroth depletion type NMOS tube is connected with the drain electrode of the zeroth PMOS tube, the source electrode and the grid electrode of the zeroth depletion type NMOS tube are connected with the drain electrode and the grid electrode of the zeroth enhancement type NMOS tube, the connection point generates a reference voltage Vref, the positive electrode of the zeroth capacitor is connected with the Vref, and the negative electrode of the zeroth capacitor and the source electrode of the zeroth enhancement type NMOS tube are grounded.
Further, the error amplifier comprises a first PMOS tube, a second PMOS tube, a first depletion type NMOS tube, a second depletion type NMOS tube and a third depletion type NMOS tube; the first PMOS tube and the second PMOS tube form a load current mirror of the error amplifier, the first depletion type NMOS tube and the second depletion type NMOS tube form a differential input geminate transistor of the differential amplifier, and the third depletion type NMOS tube forms a tail current source of the error amplifier; the grid electrode of the first PMOS tube is connected with the grid electrode and the drain electrode of the second PMOS tube, the source electrode of the first PMOS tube and the source electrode of the second PMOS tube are connected with the power supply, the drain electrode of the first PMOS tube is connected with the grid electrode of the zeroth PMOS tube and the drain electrode of the first depletion type NMOS tube, the drain electrode of the second PMOS tube is connected with the drain electrode of the second depletion type NMOS tube, the grid electrode of the first depletion type NMOS tube is connected with Vramp, the grid electrode of the second depletion type NMOS tube is connected with Vref, the source electrode of the first depletion type NMOS tube is connected with the source electrode of the second depletion type NMOS tube and the drain electrode of the third depletion type NMOS tube, and the source electrode and the grid electrode of the third depletion type NMOS tube are.
Adopt the beneficial effect that above-mentioned technical scheme brought:
the invention can adjust the rising slope of the reference voltage Vref by adjusting the current of the constant current source I1 or the capacitance value of the capacitor C1, and avoid the surge generated by the reference voltage Vref, and the output of the voltage stabilizing chip adopting the depletion tube reference voltage source with soft start also rises linearly like the reference voltage Vref without generating the surge, so the depletion tube reference circuit with soft start designed by the invention is an ideal reference voltage source of various voltage stabilizers.
Drawings
FIG. 1 is a conventional depletion transistor reference voltage circuit diagram;
FIG. 2 is a reference circuit diagram of a depletion transistor with soft start according to the present invention;
fig. 3 is a detailed circuit diagram of the error amplifier of the present invention.
Detailed Description
The technical scheme of the invention is explained in detail in the following with the accompanying drawings.
The invention designs a depletion transistor reference circuit with soft start, which comprises a ramp voltage generating circuit, an error amplifier AMP, a PMOS transistor P0 and a depletion transistor reference voltage generating circuit as shown in figure 2. The ramp voltage generation circuit outputs a ramp voltage Vramp, the depletion tube reference voltage generation circuit outputs a reference voltage Vref, the inverting input end of the error amplifier AMP is connected to the Vramp, the non-inverting input end of the error amplifier AMP is connected to the Vref, the grid electrode of the PMOS tube P0 is connected to the output end of the error amplifier AMP, the source electrode of the PMOS tube P0 is connected to a power supply VDD, and the drain electrode of the PMOS tube P0 is connected to the depletion tube reference voltage generation circuit.
In the present embodiment, preferably, as shown in fig. 2, the ramp voltage generating circuit includes a current source I1 and a capacitor C1. One end of the current source I1 is connected with a power supply, the other end of the current source I1 is connected with the anode of the capacitor C1, and the cathode of the capacitor C1 is grounded. A current source I1 charges a capacitor C1 with a constant current to generate a ramp voltage Vramp.
In this embodiment, preferably, as shown in fig. 2, the depletion transistor reference voltage generating circuit includes a depletion NMOS transistor DN0, an enhancement NMOS transistor N0 and a capacitor C0. The drain electrode of the depletion type NMOS tube DN0 is connected with the drain electrode of the PMOS tube P0, the source electrode and the grid electrode of the depletion type NMOS tube DN0 are connected with the drain electrode and the grid electrode of the enhancement type NMOS tube N0, the connection point generates a reference voltage Vref, the positive electrode of the capacitor C0 is connected with the Vref, and the negative electrode of the capacitor C0 and the source electrode of the enhancement type NMOS tube N0 are grounded.
Ramp voltage Vramp rises from 0 before rising to supply voltage VDD to satisfy the relationship set forth in equation (2):
in the formula (2), I1 represents the current value of the current source I1, C1 represents the capacitance value of the capacitor C1, and t represents the charging time of the current source I1 to the capacitor C1, and it can be known from the formula (2) that the rising slope of Vramp is determined by I1/C1, and the required ramp voltage rising slope can be obtained by selecting the appropriate current value I1 or the capacitance value C1.
As can be seen from the formula (1) in the background art, the value of the reference voltage Vref of the depletion transistor after stabilization is
Vref rises from 0 after power-on, rises to Vref
The former Vref is Vramp (I1/C1) × t, and the rising slope of Vref is determined by I1/C1. When Vref rises to
Then no longer increases, at which point Vramp>Vref, errorThe amplifier AMP outputs low level, the P0 tube is in a completely open switch state, the current of the depletion tube DN0 is not affected by the P0 tube, and the Vref value is determined by the threshold value and the width-to-length ratio W/L of the depletion tube DN0 and the enhancement NMOS tube N0.
The invention designs a specific structure of an error amplifier, and as shown in fig. 3, the error amplifier comprises PMOS tubes P1 and P2 and depletion tubes DN1, DN2 and DN 3. Although DN3 is used as the tail current source of the error amplifier, its gate and source are connected to GND, its drain and the source of depletion tube DN1 and DN2 are connected together, DN1 and DN2 are used as the differential input pair of transistors of the error amplifier, the gate of DN1 is connected to the output Vramp of the ramp voltage generating circuit as the inverting input terminal, and the gate of DN2 is connected to the output Vref of the depletion tube reference voltage generating circuit as the non-inverting input terminal. The differential input pair drain has the advantage of achieving a linear rise in Vref voltage from 0 with a fixed slope of I1/C1. PMOS tubes P1 and P2 are used as load current mirrors of an error amplifier, the grid of P1 is connected with the grid and the drain of P2 to drain of DN2, the drain of P1 is connected with the drain of DN1, the output end of error abandoning is connected with the grid of P0 to control the current of the P0 tube, and the source of P1 is connected with the source of P2 to power supply VDD.
The embodiments are only for illustrating the technical idea of the present invention, and the technical idea of the present invention is not limited thereto, and any modifications made on the basis of the technical scheme according to the technical idea of the present invention fall within the scope of the present invention.
Claims (4)
1. A depletion transistor reference circuit with soft start is characterized in that: the reference voltage generating circuit comprises a ramp voltage generating circuit, an error amplifier, a zeroth PMOS tube and a depletion tube reference voltage generating circuit; the ramp voltage generation circuit outputs a ramp voltage Vramp, the reference voltage generation circuit outputs a reference voltage Vref, the inverting input end of the error amplifier is connected to the Vramp, the non-inverting input end of the error amplifier is connected to the Vref, the grid electrode of the zeroth PMOS tube is connected to the output end of the error amplifier, the source electrode of the zeroth PMOS tube is connected to the power supply, and the drain electrode of the zeroth PMOS tube is connected to the reference voltage generation circuit.
2. The depletion tube reference circuit with soft start according to claim 1, wherein: the ramp voltage generating circuit comprises a current source and a first capacitor; one end of the current source is connected with the power supply, the other end of the current source is connected with the anode of the first capacitor, and the cathode of the first capacitor is grounded; the current source charges the first capacitor with a constant current to generate a ramp voltage Vramp.
3. The depletion tube reference circuit with soft start according to claim 1, wherein: the depletion tube reference voltage generating circuit comprises a zeroth depletion type NMOS tube, a zeroth enhancement type NMOS tube and a zeroth capacitor; the drain electrode of the zeroth depletion type NMOS tube is connected with the drain electrode of the zeroth PMOS tube, the source electrode and the grid electrode of the zeroth depletion type NMOS tube are connected with the drain electrode and the grid electrode of the zeroth enhancement type NMOS tube, the connection point generates a reference voltage Vref, the positive electrode of the zeroth capacitor is connected with the Vref, and the negative electrode of the zeroth capacitor and the source electrode of the zeroth enhancement type NMOS tube are grounded.
4. The depletion tube reference circuit with soft start according to claim 1, wherein: the error amplifier comprises a first PMOS tube, a second PMOS tube, a first depletion type NMOS tube, a second depletion type NMOS tube and a third depletion type NMOS tube; the first PMOS tube and the second PMOS tube form a load current mirror of the error amplifier, the first depletion type NMOS tube and the second depletion type NMOS tube form a differential input geminate transistor of the differential amplifier, and the third depletion type NMOS tube forms a tail current source of the error amplifier; the grid electrode of the first PMOS tube is connected with the grid electrode and the drain electrode of the second PMOS tube, the source electrode of the first PMOS tube and the source electrode of the second PMOS tube are connected with the power supply, the drain electrode of the first PMOS tube is connected with the grid electrode of the zeroth PMOS tube and the drain electrode of the first depletion type NMOS tube, the drain electrode of the second PMOS tube is connected with the drain electrode of the second depletion type NMOS tube, the grid electrode of the first depletion type NMOS tube is connected with Vramp, the grid electrode of the second depletion type NMOS tube is connected with Vref, the source electrode of the first depletion type NMOS tube is connected with the source electrode of the second depletion type NMOS tube and the drain electrode of the third depletion type NMOS tube, and the source electrode and the grid electrode of the third depletion type NMOS tube are.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010258149.5A CN111443753B (en) | 2020-04-03 | 2020-04-03 | Depletion tube reference circuit with soft start |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010258149.5A CN111443753B (en) | 2020-04-03 | 2020-04-03 | Depletion tube reference circuit with soft start |
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| CN111443753B CN111443753B (en) | 2021-10-22 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112363561A (en) * | 2020-11-05 | 2021-02-12 | 上海艾为电子技术股份有限公司 | Linear voltage regulator and soft start method thereof |
| CN113467566A (en) * | 2021-08-06 | 2021-10-01 | 上海艾为电子技术股份有限公司 | Ramp voltage generating circuit, chip and electronic equipment |
| CN117406821A (en) * | 2023-11-07 | 2024-01-16 | 深圳奥简科技有限公司 | Low-dropout linear voltage stabilizing circuit |
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| US6005378A (en) * | 1998-03-05 | 1999-12-21 | Impala Linear Corporation | Compact low dropout voltage regulator using enhancement and depletion mode MOS transistors |
| CN101369162A (en) * | 2007-08-16 | 2009-02-18 | 精工电子有限公司 | Reference voltage circuit |
| CN201804292U (en) * | 2010-04-23 | 2011-04-20 | 比亚迪股份有限公司 | Reference voltage generating circuit |
| CN109067159A (en) * | 2018-09-14 | 2018-12-21 | 上海南芯半导体科技有限公司 | A kind of soft start controller and load switching device of load switching device |
-
2020
- 2020-04-03 CN CN202010258149.5A patent/CN111443753B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6005378A (en) * | 1998-03-05 | 1999-12-21 | Impala Linear Corporation | Compact low dropout voltage regulator using enhancement and depletion mode MOS transistors |
| CN101369162A (en) * | 2007-08-16 | 2009-02-18 | 精工电子有限公司 | Reference voltage circuit |
| CN201804292U (en) * | 2010-04-23 | 2011-04-20 | 比亚迪股份有限公司 | Reference voltage generating circuit |
| CN109067159A (en) * | 2018-09-14 | 2018-12-21 | 上海南芯半导体科技有限公司 | A kind of soft start controller and load switching device of load switching device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112363561A (en) * | 2020-11-05 | 2021-02-12 | 上海艾为电子技术股份有限公司 | Linear voltage regulator and soft start method thereof |
| CN113467566A (en) * | 2021-08-06 | 2021-10-01 | 上海艾为电子技术股份有限公司 | Ramp voltage generating circuit, chip and electronic equipment |
| CN117406821A (en) * | 2023-11-07 | 2024-01-16 | 深圳奥简科技有限公司 | Low-dropout linear voltage stabilizing circuit |
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| CN111443753B (en) | 2021-10-22 |
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