CN111443275B - Circuit test system and circuit test method - Google Patents

Abstract

The present disclosure relates to a circuit testing system and a circuit testing method. The circuit test system comprises a control circuit, an interface circuit, a scan chain circuit and a circuit to be tested. The control circuit is electrically connected to the test machine and used for receiving the scanning control signal. The interface circuit is electrically connected to the control circuit, the test machine, the scan chain circuit and the circuit to be tested. When the scanning control signal is at the first level, the control circuit is used for controlling the interface circuit to transmit the scanning test signal transmitted by the test machine to the scanning chain circuit; and simultaneously, the signal displacement collected by the register in the scan chain circuit is output to a test machine for interpretation. When the scanning control signal is at the second level, the control circuit is used for controlling the interface circuit to transmit the response signal generated by the circuit to be tested to the test machine and collecting the operation result of the combinational logic circuit through the register on the scanning chain.

Description

Circuit test system and circuit test method

Technical Field

The present disclosure relates to a circuit testing system, and more particularly, to a technique for receiving a test signal from a testing machine to determine whether a circuit under test is abnormal.

Background

A Scan chain (Scan chain) is an implementation manner of Design for Testability (DFT), and a plurality of registers are configured in an integrated circuit to detect each region of the integrated circuit to determine whether an abnormality occurs. However, the scan chain technique does not test all areas on the integrated circuit, and thus there is still room for improvement.

Disclosure of Invention

One embodiment of the present disclosure is a circuit testing system including a control circuit, an interface circuit, a scan chain circuit, and a circuit under test. The control circuit is electrically connected to the test machine and receives the scanning control signal. The interface circuit is electrically connected to the control circuit, the test machine, the scan chain circuit and the circuit to be tested. When the scanning control signal is at the first level, the control circuit controls the interface circuit to transmit the scanning test signal transmitted by the test machine to the scanning chain circuit. When the scanning control signal is at the second level, the control circuit controls the interface circuit to transmit the response signal generated by the circuit to be tested to the test machine.

Drawings

FIG. 1 is a schematic diagram of a microchip used in the present disclosure.

FIG. 2 is a schematic diagram of a circuit testing system according to some embodiments of the present disclosure.

FIG. 3 is a waveform diagram of a circuit testing system according to some embodiments of the present disclosure.

Fig. 4A, 4B, and 4C are schematic diagrams of switch circuits according to embodiments of the disclosure.

FIG. 5 is a flow chart of a circuit testing method according to some embodiments of the present disclosure.

FIG. 6 is a schematic diagram of a circuit testing system according to some embodiments of the present disclosure.

Fig. 7 and 8 are waveform diagrams of circuit testing systems according to some embodiments of the present disclosure.

Fig. 9A, 9B, and 9C are schematic diagrams of switch circuits according to some embodiments of the disclosure.

FIG. 10 is a flow chart of a circuit testing method according to some embodiments of the present disclosure.

Detailed Description

Please refer to fig. 1, which is a schematic diagram of a microchip applied in the present disclosure. In some embodiments, the circuit testing method of the present disclosure is used to test a circuit in a microchip. As shown in FIG. 1, the microchip comprises a plurality of circuits to be tested C1-C3 and a plurality of scan cells R1-R3. Scan chain technology can detect a portion of the circuitry in a microchip, and the coverage of the detection (coverage) can be improved by the improvements of the present disclosure.

In Scan test (Scan test) by Scan chain technique, the detection process includes Shift mode (Shift) and Capture mode (Capture). In the shift mode, the tester inputs scan test signals into the registers of the scan cells R1-R3 one by one according to the clock signal generated by the scan clock (scan clock), and the process of inputting the scan test signals with the pulse (pulse) is called "shift", as shown by the dotted line path in the figure. In the acquisition mode, the scan clock stops outputting the clock signal, and the signals in the register are output to the circuits to be tested C1-C3 (as shown by the solid line path in the figure), so that the circuits to be tested C1-C3 perform operations; then, the test machine continues to send clock signals, so that the circuits to be tested C1-C3 output the operation results to the registers in the scan units R1-R3, and the process of outputting the results to the scan units R1-R3 after the operation is called acquisition.

In the shift mode, the tester outputs the continuous clock signal again, and inputs new scan test signals into the registers of the scan cells R1-R3 one by one. At this time, the operation results in the registers of the scan cells R1-R3 are outputted to the tester along with the clock signal to determine whether they match the expected results. However, the scan test cannot completely detect all the circuits under test C1-C3. As shown in FIG. 1, since the input terminal of the DUT C1 and the output terminal of the DUT C3 are not connected to the scan cells, the DUT C1 and DUT C3 cannot be detected by the scan chain technique. In order to improve the test coverage of the circuits under test C1 and C3 in the conventional scan chain test technology, a scan wrapping element (San Wrapper) is inserted into the input terminal of the circuit under test C1 and the output terminal of the circuit under test C3. The basic principle of scan wrapping is to change the circuit connections of the circuits under test C1 and C3 and the I/O interface circuit in the true operating Mode (Normal Mode) through a multiplexer during the scan Mode, so that the electrical connections become a group of registers controllable by the scan chain. Therefore, the improvement method does not cover the electrical connection under all real working modes, and can not solve the problem that the internal circuits of a plurality of input/output interfaces are not completely and effectively tested.

The present disclosure can improve the coverage of scan chain technology. Referring now to FIG. 2, therein is shown a schematic diagram of a circuit testing system 100 in some embodiments of the present disclosure. The circuit testing system 100 includes a testing machine 200, a control circuit 110, an interface circuit 120, a scan chain circuit 130, and a circuit under test 140. The control circuit 110 is electrically connected to the test platform 200 through the interface circuit 120 to receive the scan control signal SE, the scan auxiliary signal SF, the clock signal clk, and the scan mode signal SM. Fig. 2 is a schematic diagram of the present disclosure, in which the scan chain circuit 130 may include a plurality of scan chains (scan chains) and a plurality of scan clocks (scan clocks). The scan control signal SE is a control signal in a scan test, and details will be described later.

The interface circuit 120 includes a plurality of input/output cells (input/output cells) electrically connected to the control circuit 110, the test machine 200, the scan chain circuit 130 and the circuit under test 140. As shown in fig. 2, in some embodiments, the interface circuit 120 includes at least a first input/output unit 120A, a second input/output unit 120B, and a third input/output unit 120C. Each of the input/output units may include a plurality of input/output devices. The circuit under test 140 can be regarded as the circuit under test C1, C3 in FIG. 1. In the integrated circuit within the microchip, the circuits are interrelated, and therefore, although the circuit under test 140 is shown as including the first sub-circuit 140A and the second sub-circuit 140B in fig. 2, this illustration is merely for convenience of illustration of the present technology and does not limit the first sub-circuit 140A and the second sub-circuit 140 to be completely independent circuits.

In some embodiments, the control circuit 110 receives the scan control signal SE through the interface circuit 120. The interface circuit 120 is a transmission interface for the microchip to an external circuit. In some embodiments, the scan chain circuit 130 is an internal circuit (which can be considered as scan cells R1, R2, R3 and the circuit under test C2 in fig. 1) in the microchip that can be tested by the scan chain technique.

The manner in which the circuit testing system 100 detects the scan chain circuit 130 through the scan chain technique is described herein. In some embodiments, the scan chain circuit 130 includes a combinational circuit 131 and a plurality of scan cells F1-F4 connected in series. The combination circuit 131 may include a plurality of detection regions, each of which corresponds to one of the scan cells F1 through F4. Each of the scan cells F1-F4 includes a register and a multiplexer, wherein a control terminal of the multiplexer receives a scan control signal SE to allow the register to selectively receive the output signal from the combination circuit 131 or the previous scan cell.

When the scan control signal SE is at a first level (e.g., an enable level), the scan control signal SE controls the scan chain circuit 130 to be in the shift mode. At this time, the tester 200 inputs different scan test signals Sc1 (e.g., 0 or 1) to the scan cells F1-F4 in the scan chain circuit 130 according to the clock cycle through the first input/output cell 120A of the interface circuit 120 and the clock signal outputted continuously. The multiplexers in the scan cells F1-F4 input the scan test signal Sc1 to the registers, and the multiplexers in the scan cells F1-F4 select to receive the output signal of the previous scan cell, so the registers in the scan cells F1-F4 are connected in series.

When the scan control signal SE is at a second level (e.g., a disable level), the scan control signal SE controls the scan chain circuit 130 to be in the Capture mode. At this time, the tester 200 stops outputting the clock signal, so that the multiplexers in the scan cells F1-F4 do not receive the scan test signal Sc1, but transmit the previously received scan test signal Sc1 to the combination circuit 131 for operation. Then, the test bench 200 recovers the output clock signal, since the multiplexers in the scan cells F1-F4 are changed to receive the operation results of the combinational circuit 131 and the second sub-circuit 140B (e.g., the second response signal Sr2 shown in FIG. 2) according to the scan control signal SE. Accordingly, the registers in the scan chain units F1-F4 form the structural connection lines for collecting the combinational circuit 131 and the second response signal Sr2 to collect the output signal of the combinational circuit 131 and the second response signal Sr 2.

When the scan control signal SE is restored from the second level to the first level (i.e., is in the shift mode again), the scan cells F1-F4 receive the scan test signal Sc1 again. As shown in fig. 2, the scan unit F4 transmits the scan response signal Sc2 received in the acquisition mode to the second input/output unit 120B of the interface circuit 120, so as to transmit the scan response signal Sc2 to the test stage 200 through the second input/output unit 120B. The tester 200 determines whether the combinational circuit 131 operates normally according to the scan response signal Sc 2. The foregoing is only a concept of scan chain technology, and the details of the implementation of scan chain technology can be understood by those skilled in the art, and therefore, will not be described herein.

When the scan control signal SE is at the second level (i.e., the scan chain circuit 130 is controlled to be in the acquisition mode), the test platform 200 does not need to send the scan test signal Sc1 through the interface circuit 120 (e.g., the first-third input/output cells 120A-120C), and therefore the interface circuit 120 is in an idle and available state. The present disclosure can control the state of the interface circuit 120 by the control circuit 110 when the scan control signal SE is at the second level without scanning the cladding element, so as to enable the signal transceiving between the circuit under test 140 and the test machine 200. Thus, the registers in the scan cells F1-F2 can collect the output signal of the second sub-circuit 140B, so that the test apparatus 200 can determine whether the circuit under test 140, the logic circuit 112, and the interface circuit 120 are operating normally.

Accordingly, the interface circuit 120 is utilized to transmit signals in the "acquisition mode" and the "shift mode" to enable the tester 200 to detect the circuit 140 under test, thereby solving the problem that the "circuit directly connected to the interface circuit 120 in the microchip" cannot be completely detected in the prior art of scan chain.

For clarity of the detailed description of the present disclosure, the operation of each of the input/output units 120A-120C in the interface circuit 120 is described herein. Referring to fig. 2, when an input/output unit is a bi-directional interface (e.g., the input/output units 120A to 120C shown in fig. 2), they all include an input terminal I, an output terminal O, a control terminal oe (output enable), and a test terminal IO (i.e., an external bi-directional input/output terminal IO). This illustration is only for the convenience of the present technology, and does not limit each of the input/output units 120A-120C to be a bi-directional interface. In the shift mode, the first input/output unit 120A is mainly used for receiving the scan test signal Sc 1. The second input/output unit 120B is mainly used for outputting the scan response signal Sc2 to the test apparatus 200. Therefore, in practical applications, the first input/output unit 120A may be a bidirectional input/output interface or a unidirectional input interface, and the second input/output unit 120B may be a bidirectional input/output interface or a unidirectional output interface; the third input-output unit 120C may be any input-output interface. If the input/output units 120A to 120C are unidirectional input/output interfaces, the control terminal OE will not be included, the unidirectional output interface will not include the output terminal O, and the unidirectional input interface will not include the input terminal I. Since those skilled in the art can understand the internal circuits of the input/output cells 120A-120C, only the operations related to the circuit testing method of the present disclosure will be described herein: when the signal received by the control terminal OE is at an enable level, the input terminal I is conducted to the test terminal IO (hereinafter referred to as output mode), and the test terminal IO is also conducted to the internal output terminal O; i.e. indirectly making the input terminal I also conduct to the output terminal O. When a signal received by the control end OE is at a forbidden energy level, the input end I is disconnected with the test end IO; only the test terminal IO is conducted to the internal output terminal O (hereinafter referred to as input mode).

IN the embodiment shown IN FIG. 2, the first input/output unit 120A of the interface circuit 120 serves as an input terminal (SCAN _ IN) of the SCAN chain test, and the second input/output unit 120B serves as an output terminal (SCAN _ OUT) of the SCAN chain test. The third I/O unit 120C is a bi-directional I/O interface through which the test platform 200 does not need to transmit scan control signals in the shift mode. For convenience of description, the terminals of the first input/output cell 120A are referred to as a first control terminal OE, a first test terminal IO, a first input terminal I and a first output terminal O. Similarly, the terminals of the second and third input/ output cells 120B and 120C are respectively referred to as a second control terminal OE, a second test terminal IO, a second input terminal I and a second output terminal O, and a third control terminal OE, a third test terminal IO, a third input terminal I and a third output terminal O.

When the scan control signal SE is at the first level (i.e., the shift mode), the control circuit 110 outputs the first and third control signals S1 and S3 at the disable level to the first and third control terminals OE, so that the first input/output unit 120A receives the scan test signal Sc1 through the first output terminal O and the third input/output unit 120C maintains the input mode. Meanwhile, the control circuit 110 outputs the second control signal S2 with the enable level to the second control terminal OE, so that the second input/output unit 120B receives the scan response signal Sc2 generated by the scan chain circuit 130 through the second input terminal I, and transmits the scan response signal Sc2 to the test apparatus 200.

In some embodiments, the first control terminal OE is electrically connected to the control circuit 110, the first test terminal IO is electrically connected to the test machine 200, and the first output terminal O is electrically connected to the scan chain circuit 130 and the second sub-circuit 140B. The second control terminal OE is electrically connected to the control circuit 110, the second test terminal IO is electrically connected to the test machine 200, and the second input terminal I is electrically connected to the scan chain circuit 130 and the first sub-circuit 140A through the multiplexer.

In some embodiments, the control circuit 110 includes a switch circuit 111 and a logic circuit 112. The logic circuit 112 is a circuit existing in the microchip in the normal operation mode, and its function is not limited. The switch circuit 111 is electrically connected to the logic circuit 112 and is configured to receive the scan control signal SE from the test platform 200. When the scan control signal SE is at the second level, the switch circuit 111 turns on the logic circuit 112 to the control end OE of each of the input/output units 120A to 120C of the interface circuit 120 according to the scan control signal SE, so that the test machine 200 can detect each region of the circuit under test 140.

Referring to FIG. 2, the operation of the circuit testing system 100 is described. When the scan control signal SE is at the first level, the logic circuit 112 in the control circuit 110 receives the input signal (e.g., SM, SE, and SF shown in fig. 2) from the tester 200, and the switch circuit 111 is in the off state, so that the logic circuit 112 does not control the control end OE of each of the input/output units 120A to 120C in the interface circuit 120. When the scan control signal SE is at the second level, the logic circuit 112 generates an output signal according to a signal (e.g., the output value of the first sub-circuit 140A) received in the normal operation mode. At this time, the switch circuit 111 is turned on, so the output signals generated by the logic circuit 112 form the first to third control signals S1 to S3 through the switch circuit 111. For example, if the first control signal S1 received by the first control terminal OE of the first input/output unit 120A is at an enable level, the first input/output unit 120A is controlled to be in the output mode, and the first input terminal I is conducted to the first test terminal IO at this time, if the signal received by the test apparatus 200 is correct, it represents that the first sub-circuit 140A and the logic circuit 112 connected to the first output terminal I are operating normally, and the internal circuit of the first input/output unit 120A is also operating normally.

On the contrary, if the second control signal S2 received by the second control terminal OE of the second input/output unit 120B is at the disable level, the second input/output unit 120B is controlled to be in the input mode, and the second output terminal O is conducted to the first test terminal IO. After the shift and collection mode is properly operated, if the signal received by the tester 200 is correct, it indicates that the second sub-circuit 140B, the scan chain circuit 130, and the logic circuit 112 connected to the second output terminal O are correctly operated, and the internal circuits of the second input/output unit 120B are also normally operated. If the signal received by the test apparatus 200 does not match the expected signal, it indicates that any of the coverage test circuits (e.g., the second sub-circuit 140B or the internal circuit of the second I/O unit 120B) is abnormal. Similarly, when the signals received by the control terminals OE of the other input/output units are at the enabled or disabled level, the corresponding to-be-tested circuit 140 and the internal circuits of the input/output units can be determined to be normal or not by the same principle.

In the acquisition mode of the scan chain technique, the control interface unit 120 enables the circuit under test 140 and the test machine 200 to perform signal transmission to improve the detection coverage. However, in the switching process between the shift mode and the sampling mode, the test machine 200 can send signals to the input/output units 120A to 120C in real time, but the scan control signal SE sent by the test machine 200 to the control circuit 110 may generate the first to third control signals S1 to S3 with great delay through the internal routing of the chip to be tested, so that there is a certain probability that the test machine 200 and the input/output units 120A to 120C output signals at the same time. If the signals transmitted by the corresponding wires are different, a signal collision (Bus content) will occur, which may damage the input/output unit.

To avoid signal collision, the present disclosure provides three embodiments for overcoming the signal collision problem. In the first embodiment, the circuit testing system 100 controls the tester 200 to delay a predetermined Time (referred to as a "turn-back Time" herein) before sending the scan test signal Sc1, and then send the signal to each of the i/o units 120A-120B.

In the first embodiment, the test platform 200 sends the scan control signal SE and the scan auxiliary signal SF to the switch circuit 111. When the scan control signal SE is at the second level and the scan auxiliary signal SF is at the disable level, the circuit under test 140 transmits a response signal to the test machine 200 through the interface circuit 120. When the scan control signal SE is at the second level and the scan auxiliary signal SF is at the enable level, the interface circuit 120 is in the input mode and stops receiving the response signal transmitted by the sub-circuit to be tested 140. At this time, the tester 200 outputs appropriate test signals (e.g., the first to third test signals St1 to St3) to the first to third input/output units 120A to 120C of the interface circuit 120.

Referring to fig. 3, fig. 3 is a signal waveform diagram of the circuit testing system 100, in which clock signals clk0 and clk1 are signals output to the scan chain circuit 130 in the scan chain technique, and the scan test signal Sc1 is stored into registers in the scan chain units F1 to F4 one by one with a clock cycle. In the embodiment, the scan control signal SE represents the sampling mode when the enable level is set to be the phase shift mode, and the disable level is set to be the capture mode. The I/O cells 120A-120C are in the "external signal state Pout" when they are used to receive signals from the tester 200, and are in the "internal signal state Pin" when the I/O cells 120A-120C are used to receive signals from the DUT 140 or the scan chain circuit 130.

As shown in fig. 3, the first input/output unit 120A is taken as an example to illustrate the operation manner thereof. In this embodiment, the first sub-circuit 140A of the circuit under test 140 is electrically connected to the first input terminal I of the first input/output unit 120A. The second sub-circuit 140B of the circuit under test 140 is electrically connected to the first output terminal O of the first input/output unit 120A. When the scan control signal SE is at the first level, the tester 200 outputs a continuous clock signal and transmits various scan test signals Sc1 to the scan chain circuit 130 through the first input/output unit 120A according to the clock cycle. When the scan control signal SE changes from the first level to the second level, the test machine 200 stops outputting the clock signal; after the first turn-back time T1, the first test signal St1 is sent to the first input/output unit 120A for testing the second sub-circuit 140B. After a certain period of time, the tester 200 outputs only one pulse signal, so that the operation result (i.e., the second response signal Sr2) of the combinational circuit 131 or the second sub-circuit 140B is output to the registers of the scan chain cells F1-F4.

Then, when the scan auxiliary signal SF is at the disable level, the switch circuit 111 is turned on; at this time, the test apparatus 200 receives the signal outputted by the first input/output unit 120A, and the logic circuit 112 generates the first control signal S1 in the normal operation mode. The signal received by the first control terminal OE may be an enable signal or a disable signal, and thus the state of the first input/output cell 120A may be the external signal state Pout or the internal signal state Pin (depending on the operation result of the logic circuit 112). If the signal received by the first control terminal OE is the enable signal, the operation result of the first sub-circuit 140A in the circuit under test 140 is the first response signal Sr 1. Then, the first response signal Sr1 is transmitted back to the testing machine 200 through the first input/output unit 120A. When the signal received by the first control terminal OE is the disable signal, the first input/output unit 120A can receive the first test signal St1 from the test apparatus 200, but since the clock signal is stopped at this time, the second response signal Sr2 generated by the second sub-circuit 140B according to the first test signal St1 cannot pass through the register in the scan chain circuit 130 and is not transmitted back to the test apparatus 200. However, as mentioned in the above paragraph, when the scan control signal SE is disabled and the scan auxiliary signal SF is enabled, the test tool 200 triggers a clock to store the second response signal Sr2 into a register in the scan chain circuit 130. When the displacement mode is entered again, the second input/output unit 120B may transmit the second response signal Sr2 back to the testing apparatus 200. Therefore, the testing range will completely cover the first and second sub-circuits 140A, 140B and the logic circuit 112.

In some embodiments, when the testing apparatus 200 receives the first response signal Sr1 through the first input/output unit 120A, the first input/output unit 120A is in the output mode (i.e., the first control signal S1 is enabled). Before the scan control signal SE is controlled to be at the first level again (i.e., to be shifted to the shift mode again), the test bench 200 forces the control circuit 110 to output the first control signal S1 as disable by enabling the scan auxiliary signal SF one pulse cycle ahead (e.g., at the second turnaround time T2 shown in FIG. 3), so that the first input/output unit 120A is changed to the input mode at an early stage, and then enters the shift mode to avoid the signal collision problem. During the second rotation time, the first to third i/o units 120A to 120C are in the input mode and the wires electrically connected to the first to third i/o units 120A to 120C of the test machine 200 are all in the input state.

In some other embodiments, the first sub-circuit 140A of the circuit under test 140 is further electrically connected to the second input terminal I, and the second sub-circuit 140B of the circuit under test 140 is further electrically connected to the second output terminal O. When the scan control signal SE changes from the first level to the second level, the test apparatus 200 stops the clock signal and the scan auxiliary signal SF is still at the enabled level to force the second input/output unit 120B to be in the input mode, and after the first transition time T1, the test apparatus 200 sends the second test signal St2 to the second input/output unit 120B to avoid signal collision. The second test signal St2 sent by the tester 200 is transmitted to the second sub-circuit 140B, and a pulse is triggered to make the registers in the scan chain units F1-F4 collect the operation results of the second response signal Sr2 and the combinational logic 131. Then, the scan auxiliary signal SF becomes the disable level, so that the logic circuit 112 generates the second control signal S2 in the normal operation mode, and the test platform 200 receives the signal output by the second input/output unit 120B. The second control terminal OE may receive an enable or disable level, and operates in the same manner as the first io cell 120A. Before the scan control signal SE is converted to the first level (i.e., the shift mode) again, the test bench 200 receives the first response signal Sr1 from the circuit under test 140 through the second input/output unit 120B, and the test bench 200 enables the scan auxiliary signal SF by advancing one pulse period (i.e., the second return time T2) to force the control circuit 110 to output the second control signal S2 as disable, so that the second input/output unit 120B changes to the input mode in advance, and then enters the shift mode, and receives the scan response signal Sc2 output by the scan chain circuit 130 through the second input/output unit 120B (i.e., the action during execution of the shift program). In some embodiments, the second response signal Sr2 is first stored in a register of the scan chain circuit 130 and then returned to the test apparatus 200 through the second interface circuit 120B during the shift mode to interpret the test result. For the second input-output unit 120B, signal collision may only occur when the acquisition mode transitions to the acquisition mode, whereas for the first input-output unit 120A, signal collision may only occur when the acquisition mode transitions to the acquisition mode.

Similarly, the control circuit 110 can control the control terminal OE of the third input/output unit 120C with the third control signal S3 to detect whether its internal circuit is normal. When the scan control signal SE transits from the first level to the second level, the test bench 200 can also send the third test signal St3 to the third input/output unit 120C after the first transition time T1 to avoid signal collision. In some embodiments, the length of the first transition-back time T1 or the second transition-back time T2 may be at least one pulse period of the clock signals clk0, clk 1. Thus, the situation that the circuit under test 140 and the test machine 200 simultaneously transmit signals to the same input/output unit 120A-120C can be avoided.

In some embodiments, the switch circuit 111 is configured to receive the scan control signal SE and the scan auxiliary signal SF, and the switch circuit 111 turns on the logic circuit 112 to the interface circuit 120 only when the scan control signal SE is at a second level (e.g., a disable level) and the scan auxiliary signal SF is at the disable level. The above operation is reflected in the waveform diagram of fig. 3, and the truth table of the control circuit 110 is shown in table one:

watch 1

Fig. 4A is a schematic diagram of the switch circuit 111 for controlling the first input/output unit 120A in the control circuit 110. In some embodiments, the switch circuit 110 includes an and gate 111a (and gate) and a nor gate 111b (nor gate). The two input terminals of the nor gate 111b are used for receiving the scan switch signal SE and the scan auxiliary signal SF. Two input terminals of the and gate 111a are electrically connected to the logic circuit 112a and the output terminal of the nor gate 111 b. The output terminal of the and gate 111a outputs the first control signal S1 to control the first control terminal OE of the first input/output unit 120A.

Fig. 4B is a schematic diagram of the switch circuit 111 for controlling the second input/output unit 120B in the control circuit 110. In some embodiments, the switch circuit 111 includes an implicit not gate 111d (NIMPLY gate) and an OR gate 111c (OR gate). The two input terminals of the not gate 111d are used for receiving the scan auxiliary signal SF and electrically connected to the logic circuit 112. Two input terminals of the or gate 111c are electrically connected to the output terminal of the inclusive not gate 111d, and are used for receiving the scan control signal SE. The output terminal of the or gate 111c is used for outputting the second control signal S2 to control the second control terminal OE of the second input/output unit 120B.

Fig. 4C is a schematic diagram of the switch circuit 111 of the control circuit 110 for controlling the third input/output unit 120C. In some embodiments, the switch circuit 111 includes an inclusive not gate 111e (NIMPLY gate). The two input terminals of the not gate 111e are respectively used for receiving the scan auxiliary signal SF and electrically connected to the logic circuit 112. Accordingly, when the scan auxiliary signal SF is at the disable level, the switch circuit 111 turns on the logic circuit 112 to the third input/output unit 120C.

Referring now to FIG. 5, steps of a circuit testing method are illustrated. In step S501, the control circuit 110 receives a scan control signal SE from the test tool 200. In step S502, when the scan control signal SE is at the first level (i.e. shift mode), the control circuit 110 controls the interface circuit 120 to receive the scan test signal Sc1 through the first input/output unit 120A and to transmit the scan test signal Sc1 to the registers connected in series on the scan chain circuit 130. The purpose of this is to set the initial value of the register. Subsequently, when the scan control signal SE is at the second level, the scan chain circuit 130 will operate according to the scan test signal Sc 1. When the scan control signal SE is restored to the first level again, the test tool 200 may receive the scan response signal Sc2 through the second input/output unit 120B. This is the process of scan testing.

In step S503, when the scan control signal SE is at the second level (the acquisition mode), the control end OE of each of the input/output units 120A to 120C receives the output signal generated by the logic circuit 112, and accordingly generates the first control signal S1 to the third control signal S3, so that each of the input/output units 120A to 120C is electrically connected to the circuit under test 140 for detection. At the beginning of the acquisition mode, the tool 200 first stops generating the clock signal (clk) and maintains the scan auxiliary signal SF at the first level (e.g., the enable level), so that the output signals received by the control terminals OE of the input/output units 120A to 120C are at the disable level; the input/output units 120A to 120C transmit the test signals St1 to St3 generated by the test machine 200 to the circuit under test 140. Next, the tester 200 outputs a clock signal (clk) with one period (pulse) to store the second response signal Sr2 into the electrically connected register in the scan chain circuit 130. When the next shift mode is entered again, the second response signal Sr2 can be transmitted to the test tool 200 through the second input/output unit 120B.

Accordingly, after (at least) one pulse period after the test tool 200 generates the clock signal (clk pulse), the test tool 200 changes the scan auxiliary signal SF to a second level (e.g., a disable level). At this time, the logic circuit 112 operates according to the normal operation state to generate the first to third control signals S1 to S3. The control signals S1-S3 may be at an enable level or a disable level due to the values collected by the registers in the scan chain cells F1-F4, and the circuit characteristics of the first sub-circuit 140A and the logic circuit 112, respectively. In step S504, if the first control signal S1 is enabled, the first response signal Sr1 generated by the first sub-circuit 140A can be directly transmitted to the test apparatus 200 through the first input/output interface 120A. Similarly, the second and third control signals S2 and S3 are applied to the input/ output units 120B and 120C, and so on. That is, when the output signal received by the control end OE of each of the input/output units 120A to 120C is at the enable level, each of the input/output units 120A to 120C transmits the first response signal Sr1 generated by the first sub-circuit 140A to be tested to the test apparatus 200.

In step S505, if the output signals received by the control terminals OE of the input/output units 120A to 120C are at the disable level, the input/output units 120A to 120C transmit the test signals St1 to St3 generated by the test machine 200 to the second sub-circuit 140B of the circuit under test 140. Through the above operations, the logic circuit 112, the scan chain circuit 130, the circuit under test 140 and each of the input/output cells 120A-120C can be fully covered. For example, if the test apparatus 200 receives the first response signal Sr1 through the first input/output unit 120A, it can be determined whether the first input/output unit 120A and the first sub-circuit 140A are normal. Similarly, if the testing apparatus 200 receives the first response signal Sr1 through the second input/output unit 120B, it can be determined whether the second input/output unit 120B and the first sub-circuit 140A are normal.

Please refer to fig. 6, which is a system architecture diagram illustrating a second embodiment and a third embodiment for solving the signal collision problem in the present disclosure. The circuit testing system 300 includes a control circuit 310, an interface circuit 320, a scan chain circuit 330, and a circuit under test 340. The control circuit 310 is electrically connected to the test stage 200 and configured to receive a scan control signal SE. The interface circuit 320 is electrically connected to the control circuit 310, the test platform 200, the scan chain circuit 330 and the circuit under test 340. When the scan control signal SE is at the first level, the control circuit 310 is used to control the interface circuit 320 to conduct the scan chain circuit 330 to the tester 200, so as to transmit the scan test signal Sc1 transmitted from the tester 200 to the serial register in the scan chain circuit 330. When the scan control signal SE is at the second level, the control circuit 310 is used to control the interface circuit 320 to conduct the circuit under test 340 to the test apparatus 200, so as to transmit the first response signal Sr1 generated by the first sub-circuit 340A of the circuit under test 340 to the test apparatus 200. In addition, the tester 200 generates a clock signal (scan clk) to make the register in the scan chain circuit 330 collect the response signal (e.g., the second response signal Sr2) generated by the circuit under test 340 and the operation result of the combinational circuit 331. When the scan control signal SE returns to the first level again (i.e., the next shift mode), the interface circuit 120 may transmit the collection of the register in the scan chain circuit 330 back to the test apparatus 200 for interpretation.

To avoid the problem of signal collision when the circuit testing system 300 is in the capture mode, in the second embodiment of the disclosure, when the scan control signal SE is at the second level, the control circuit 310 controls the control terminal OE of each of the input/output units 320A to 320C at the enable level, so that each of the input/output units 320A to 320C is controlled to be in the output mode. Since the input/output units 320A-320C are not used for receiving signals from the test apparatus 200 in the output mode, when the scan control signal SE is switched from the first level to the second level (i.e., the enable level is changed to the disable level), it is ensured that the signal collision problem that the test apparatus 200 simultaneously sends signals to the same input/output unit (e.g., the second input/output unit 320B) when the circuit under test 340 is still sending signals to the input/output unit does not occur.

In the embodiment shown in fig. 6, the first input/output unit 320A of the interface circuit 320 is used as an input terminal of the scan chain test, and the second input/output unit 320B is used as an output terminal of the scan chain test. The first sub-circuit 340A of the circuit under test 340 is electrically connected to the input terminals I of the input/output units 320A-320C. The second sub-circuit 340B of the circuit under test 340 is electrically connected to the output ends O of the input/output units 320A-320C. This illustration is merely for convenience of illustration of the present technology, and does not limit each of the input/output units 320A-320C to be a bi-directional interface. In the shift mode, the first input/output unit 320A is mainly used for receiving the scan test signal Sc 1. The second input/output unit 320B is mainly used for outputting the scan response signal Sc2 to the test apparatus 200. Therefore, in practical applications, the first input/output unit 320A may be a bidirectional input/output interface or a unidirectional input interface, and the second input/output unit 320B may be a bidirectional input/output interface or a unidirectional output interface; the third input-output unit 320C may be any input-output interface. If the input/output units 320A-320C are unidirectional input/output interfaces, the control terminal OE is not included, the unidirectional output interface does not include the output terminal O, and the unidirectional input interface does not include the input terminal I.

In the second embodiment of the present disclosure, when the scan control signal SE is at the second level, the control circuit 310 controls the control terminals OE of the input/output cells 320A to 320C to be at the enabled level.

As shown in fig. 6 and 7, the circuit testing system 300 can detect the circuit under test 340 through the input/output units 320A-320C in the interface circuit 320. First, the second input/output unit 320B is taken as an example, and the manner of detecting the circuit under test 340 through the second input/output unit 320B is described as follows. When the scan control signal SE is at the first level (i.e., shift mode), the tester 200 continuously outputs the clock signal and outputs a scan test signal Sc1 to the scan chain circuit 330 via the first input/output cell 320A every clock cycle. At the end of the shift pattern, the registers of the scan chain circuit 330 store various test patterns (patterns) set by the tester 200. The circuit testing system 300 performs scan chain testing in the same manner as described above with respect to the embodiment of FIG. 2.

Accordingly, when the scan control signal SE is at the second level (i.e. in the capture mode), the test apparatus 200 stops the clock signal (clk), and the control circuit 310 controls the second control terminal OE to be at the enable level. At this time, the test pattern (pattern) set in the register of the scan chain circuit 330 is used as the input value of the first sub-circuit 340A, and the first response signal Sr1 is obtained through calculation. Then, the first response signal Sr1 is transmitted to the test apparatus 200 through the second input terminal I of the second input/output unit 320B and its internal circuit.

Meanwhile, a loopback (loopback) path is formed by the second input terminal I and the second output terminal O of the second input/output unit 320B, and the first response signal Sr1 is transmitted to the second sub-circuit 340B. The testing apparatus 200 can determine whether the internal circuits of the first sub-circuit 340A and the second input/output unit 320B are functioning normally according to the first response signal Sr 1. After a suitable delay time, the test machine 200 outputs a pulse signal to make the register of the scan chain circuit 330 collect the operation results of the second response signal Sr2 and the combinational circuit 331. After the scan control signal SE is changed from the second level to the first level again (i.e., the shift mode), the test bench 200 starts outputting a periodic clock (clk) signal to the circuit testing system 300. At this time, the tester 200 inputs the scan test signal Sc1 through the first input/output unit 320A in the interface circuit, and shifts and sets the registers in the scan chain circuit 330 one by one with the period of the clock pulse; meanwhile, the registers in the scan chain circuit 330 are shifted one by one via the second input/output unit 320B in the interface circuit to output the capture result to the tester 200. By the above-mentioned method, the operation results of the second response signal Sr2 and the combinational logic 331 can be obtained, and whether the second input I and the second output O of the second sub-circuit 340B, the combinational logic 331 and the interface circuit 320B are operating normally can be determined.

Similarly, the circuit testing system 300 can also test the internal circuits of the circuit under test 340 and the first input/output unit 320A through the first input/output unit 320A. As shown in fig. 6, when the scan control signal SE is at the second level, the test bench 200 stops outputting the clock signal (clk), and the control circuit 310 controls the first control terminal OE to be at the enable level. The first sub-circuit 340A can obtain the scan test signal Sc1 sent by the test apparatus 200 through the register in the scan chain circuit 330, and then transmit the first response signal Sr1 to the test apparatus 200 through the first input terminal I of the first input/output unit 320A. Meanwhile, the first response signal Sr1 is looped back (loopback) to the second sub-circuit 340B through the first output terminal O of the first input-output cell 320A. The test apparatus 200 can determine whether the internal circuits of the first sub-circuit 340A and the first input/output unit 320A are operating normally according to the first response signal Sr 1. After a suitable delay time, the test machine 200 outputs a pulse signal to the register of the scan chain circuit 330 to collect the operation result of the second response signal Sr2 and the combinational circuit 331. After the scan control signal SE is changed from the second level to the first level, the clock signal is restarted and transmitted to the register value in the scan chain circuit 330 via the second input/output unit 320B, so as to transmit the collected operation result to the test apparatus 200, so that the test apparatus 200 can determine whether the control end OE, the first input end I, and the first output end O of the second sub-circuit 340B, the combinational logic 331, and the interface circuit 320A operate normally.

Similarly, the testing machine 200 can also send the third test signal St3 and receive the first response signal Sr1 through the third input/output unit 320C to test the internal circuits of the circuit under test 340 and the third input/output unit 320C. In the second and third embodiments of the present invention, in the shift mode, the third control signal S3 output by the control circuit 310 is at a disable level, so that the third input/output unit 320C is in an input state, and the test apparatus 200 does not output a signal to the third input/output unit 320C. When the acquisition mode is switched, the third control signal S3 output by the control circuit 310 is at an enable level, so that the third input/output unit 320C is in an output state. The first response signal Sr1 is returned to the second sub-circuit 340B via the third input I and the third output O of the third input-output cell 320C. By the above method, signal collision is avoided and it can be determined whether the internal circuits of the circuit under test 340 and the third input/output unit 320C are normal.

The second embodiment of the present disclosure enables the scan test coverage to include internal circuits of the first sub-circuit 340A, the second sub-circuit 340B, the first input/output unit 320A, the second input/output unit 320B, and the third input/output unit 320C. But to avoid possible signal collisions. The solution is to control each of the I/O units 320A-320C to be in an "output mode" during the acquisition mode. Accordingly, when the scan control signal SE is switched from the first level to the second level (i.e., the enable level is switched to the disable level), there is no signal collision problem that the test equipment 200 sends signals to the same input/output unit 320A-320C while the circuit under test 340 is still sending signals to each of the input/output units 320A-320C.

In the second embodiment of the present disclosure, when the scan control signal SE is switched from the second level (acquisition mode) to the first level (shift mode), the first input/output unit 320A changes from the output mode to the input mode. At this time, there is a delay in the transmission of the scan control signal SE to the control circuit 310, which causes a signal collision problem. The second embodiment of the disclosure delays the test apparatus 200 by at least one pulse period (e.g., the third turn-back time T3 shown in FIG. 7) before outputting the scan test signal Sc1 to the first input/output cell 320A when the sampling mode is switched to the shift mode, thereby preventing signal collision on the first input/output cell 320A. In addition, the third control signal S3 outputted by the control circuit 310 in the shift mode is disabled, and the third control signal S3 outputted in the acquisition mode is enabled, so that the third input/output unit 320C does not collide with the testing machine 200.

In the second embodiment, the test equipment 200 delays the signal transmission to avoid the signal collision problem of the first input/output unit 320A. In the third embodiment of the present disclosure, referring to fig. 6 and 8, the control circuit 310 can fix the first input/output cell 320A for receiving the scan test signal Sc1 in the input mode (i.e. the first control end OE is at the disable level) during the acquisition mode, so that, as shown in fig. 8, by maintaining the first input/output cell 320A at the "external signal state Pout" all the time, although the coverage rate of detection is reduced, signal collision can be avoided in the simplest manner. As shown in fig. 6, when the scan control signal SE is at the second level (i.e., the acquisition mode), the control circuit 310 fixes the first control terminal OE of the first input/output unit 320A at a disable level. Accordingly, the first input/output unit 320A will not receive the first response signal Sr1 transmitted from the first sub-circuit 340A of the circuit under test 340 through the first input terminal I, so that no signal collision occurs when the scan control signal SE is switched from the second level to the first level (i.e., the disable level is changed to the enable level). In the third embodiment of the present disclosure, if the first response signal Sr1 is correct, in the acquisition mode, the test platform 200 needs to receive the first response signal Sr1 through the second to third input/output units 320B to 320C, so as to determine whether the first sub-circuit 340A is normal.

Accordingly, the test bench 200 transmits the first test signal St1 to the second sub-circuit 340B through the first output terminal O of the first input/output unit 320A. Meanwhile, the circuit system 300 under test also sends back (loopback) the received first response signal Sr1 as the second test signal St2 and the third test signal St3 to the second sub-circuit 340B through the input terminal I and the output terminal O of the second input/output unit 320B and the third input/output unit 320C, respectively. After the second sub-circuit 340B completes the operation according to the first to third test signals St1, St2, and St3, the tester 200 triggers a clock signal to enable the register in the scan chain circuit 330 to collect the second response signal Sr 2. When the circuit testing system 300 reenters the shift mode, the second sub-circuit 340B shifts the contents of the registers in the scan chain circuit 330 out of the system 300 to be tested one by one and transmits the shifted contents to the tester 200, so that the tester 200 can determine whether the second sub-circuit 340B, the combinational circuit 331, the registers in the scan chain circuit 330, and the internal circuits of the second to third input/output units 320B to 320C operate normally. In this way, although the first input/output unit 320A cannot be passed, the state of the first sub-circuit 340A is tested; while the fault coverage (fault coverage) of the circuits (e.g., the logic circuit 312) related to the first input terminal I and the control terminal OE of the first input/output unit 320A is lost, the problem of signal collision of the interface circuit 320 can be completely avoided.

In some embodiments, the control circuit 310 includes a switch circuit 311 and a logic circuit 312. Referring to fig. 9A and 9B, different embodiments of the switch circuit 311 are shown. In the second embodiment of the present disclosure, as shown in fig. 9A, a switch circuit 311 for controlling the first input/output unit 320A in the control circuit 310 is shown. The switch circuit 311 includes a switch circuit 311a (e.g., a multiplexer). The two input terminals of the switching circuit 311a are electrically connected to the logic circuit 312, and receive the scan control signal SE through the inverter. The control terminal of the switching circuit 311a is used to receive a scan mode signal sm (scan mode signal) sent by the testing machine 200. The scan mode signal SM is maintained at an enable level, and in the acquisition mode, after the scan control signal SE is input to the switching circuit 311a through the inverter, the switching circuit 311a controls the first control terminal OE of the first input/output unit 320A to be at the enable level.

In the second and third embodiments, fig. 9B is a schematic diagram of a switch circuit 311 in the control circuit 310 for controlling the second input/output unit 320B. The switching circuit 311 includes an or gate 311b, and two input terminals of the or gate 311b are electrically connected to the logic circuit 312 and the scan mode signal SM. Accordingly, the control circuit 310 can control the second input/output unit 320B to always maintain the enabled level.

In some embodiments, please refer to fig. 9C, which shows a switch circuit 311 of the control circuit 310 for controlling the third input/output unit 320C. The switch circuit 311 includes a switch circuit 311c, and two input terminals of the switch circuit 311c are respectively electrically connected to the logic circuit 312 and receive the scan control signal SE through the inverter. The control terminal of the switching circuit 311a is switched according to the scan mode signal SM, so that in the acquisition mode, after the scan control signal SE is input to the switching circuit 311a through the inverter, the switching circuit 311a controls the third control terminal OE of the third input/output unit 320C to be at an enable level.

Referring to fig. 10, a flow of steps of a circuit testing method according to the second and third embodiments of the present disclosure is described. In step S1001, the control circuit 310 receives a scan control signal SE from the test tool 200. In step S1002, when the scan control signal SE is at the first level, the control circuit 310 controls the interface circuit 320 to transmit the scan test signal Sc1 to the scan chain circuit 330. In step S1003, when the scan control signal SE is at the second level, the control circuit 310 sets the control terminals OE of the second input unit 320B and the third input/output unit 320C at the enabling level via the second control signal S2 and the third control signal S3, so that the first sub-circuit 340A can transmit the first response signal Sr1 to the tester and the second sub-circuit 340B via the second input/output unit 320B or the third input/output unit 320C.

In step S1004, the control circuit 310 outputs a first control signal S1 to control the first control terminal OE. In the second embodiment of the present disclosure, in step S1005, the output signal of the control circuit 310 (i.e., the first control signal) is at the enable level, and the first sub-circuit 340 transmits the first response signal Sr1 to the test apparatus 200 and the second sub-circuit 320B. The test apparatus 200 determines whether the internal circuits of the first sub-circuit 320A and the first input/output unit 310A are normal according to the first response signal Sr 1. Next, in step S1007, when the scan control signal SE returns to the first level, the test bench 200 indirectly receives the second response signal Sr2 transmitted by the second sub-circuit 340B through the scan chain register to determine whether the internal circuits of the second sub-circuit 320B and the first input/output unit 310A are normal.

In the third embodiment of the present disclosure, in step S1006, the output signal (i.e., the first control signal) of the control circuit 310 is at the disable level, and the testing machine 200 transmits the first testing signal St1 to the second sub-circuit 320B through the first output terminal O. Next, in step S1007, when the scan control signal SE returns to the first level, the test bench 200 indirectly receives the second response signal Sr2 transmitted by the second sub-circuit 320B through the scan chain register to determine whether the second sub-circuit 320B is normal.

In addition, in the above embodiments, the input/output units 120A to 120C and 320A to 320C are bi-directional input/output interface circuits (bi-directional I/O cells), but the invention is not limited thereto, and some of the input/output units 120A to 120C and 320A to 320C may be input interface circuits (pure input) or output interface circuits (pure output).

[ description of symbols ]

100. 300 circuit test system

110. 310 control circuit

111. 311 switching circuit

111a AND gate 111b NOR gate

111c, 311b or door

111d inclusive inverter

112. 312 logic circuit

120. 320 interface circuit

120A, 120B, 120C input/output unit

130. 330 scan chain circuit

131. 331 combination circuit

F1, F2, F3 and F4 scan chain units

140. 340 circuit under test

140A, 140B, 340A, 340B subcircuits

200 test machine

311a, 311c switching circuit

320A, 320B, 320C input/output unit

I input terminal O output terminal

IO test end OE control end

St1, St2, St3 test signals

S1, S2, S3 control signals

Sc1 scanning test signal

Sc2 scanning response signal

Sr1 and Sr2 response signals

SE Scan control Signal

SF scan assist signal

SM scan mode signal

Clk, Clk0, Clk1 clock signals

Pin internal signal state

Pout external signal state

T1, T2, T3 switch back to time.

Claims (9)

1. A circuit test system, comprising:

a control circuit, electrically connected to a test machine, for receiving a scan control signal; and

an interface circuit, which is electrically connected to the control circuit, the test machine, a scan chain circuit and a circuit to be tested; when the scanning control signal is at the first level, the control circuit is used for controlling the interface circuit to transmit a scanning test signal transmitted by the test machine to the scanning chain circuit;

when the scanning control signal is at a second level, the control circuit is used for controlling the interface circuit to transmit a response signal generated by the circuit to be tested to the test machine;

wherein, this interface circuit contains:

the control circuit controls the interface circuit to receive the scan test signal through the first input/output unit when the scan control signal is at the first level; and

a second I/O unit, when the scan control signal is at the first level, the control circuit controls the interface circuit to transmit a scan response signal generated by the scan chain circuit to the tester through the second I/O unit,

the circuit to be tested is electrically connected to a first input end and a first output end of the first input/output unit, and/or the circuit to be tested is electrically connected to a second input end and a second output end of the second input/output unit.

2. The circuit testing system of claim 1, wherein the second input/output unit transmits the response signal generated by the circuit under test to the tester when the scan control signal is at the second level.

3. The circuit testing system of claim 1, wherein the first input/output unit transmits the response signal generated by the circuit under test to the tester when the scan control signal is at the second level.

4. The circuit testing system of claim 1, wherein the first input/output unit comprises a first control terminal, a first testing terminal and a first output terminal; the first control end is electrically connected to the control circuit, the first test end is electrically connected to the test machine, and the first output end is electrically connected to the scan chain circuit;

the second input/output unit comprises a second control end, a second test end and a second input end; the second control end is electrically connected to the control circuit, the second test end is electrically connected to the test machine, and the second input end is electrically connected to the scan chain circuit.

5. The circuit testing system of claim 4, wherein the control circuit comprises a switch circuit and a logic circuit, the switch circuit is electrically connected to the logic circuit and is configured to receive the scan control signal; when the scanning control signal is at the second level, the switch circuit conducts the logic circuit to the interface circuit.

6. The circuit testing system according to claim 5, wherein the switch circuit is further configured to receive a scan auxiliary signal, and the circuit under test transmits the response signal to the tester through the interface circuit when the scan control signal is at the second level and the scan auxiliary signal is at a disable level; when the scanning control signal is at the second level and the scanning auxiliary signal is at an enable level, the interface circuit is used for receiving a testing signal transmitted by the testing machine.

7. The circuit testing system of claim 6, wherein the circuit under test is electrically connected to the first input terminal and the first output terminal of the first input/output unit; when the scanning control signal is converted from the first level to the second level, the test machine sends a first test signal to the first input/output unit after a first turn-back time; when the test machine receives the response signal transmitted by the circuit to be tested through the first input/output unit, the test machine advances a second turn-back time to enable the scanning auxiliary signal.

8. The circuit testing system of claim 6, wherein the circuit under test is electrically connected to the second input terminal and the second output terminal of the second input/output unit; when the scanning control signal is converted from the first level to the second level, the test machine sends a second test signal to the second input/output unit after a first conversion time; when the test machine receives the response signal transmitted by the circuit to be tested through the second input/output unit, the test machine advances a second turn-back time to enable the scanning auxiliary signal.

9. A circuit testing method, comprising:

receiving a scanning control signal transmitted from a testing machine through a control circuit;

when the scanning control signal is at a first level, controlling an interface circuit to transmit a scanning test signal transmitted by the test machine to a scanning chain circuit through the control circuit; and

when the scanning control signal is at a second level, the interface circuit is controlled by the control circuit to transmit a response signal generated by the circuit to be tested to the test machine;

wherein, this interface circuit contains:

a first input/output unit, wherein when the scan control signal is at the first level, the control circuit controls the interface circuit to receive the scan test signal through the first input/output unit; and

a second input/output unit, when the scan control signal is at the first level, the control circuit controls the interface circuit to transmit a scan response signal generated by the scan chain circuit to the tester through the second input/output unit,

the circuit to be tested is electrically connected to a first input end and a first output end of the first input/output unit, and/or the circuit to be tested is electrically connected to a second input end and a second output end of the second input/output unit.

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