CN111435679B - 具有非对称应变源极/漏极结构的半导体元件其制作方法 - Google Patents

具有非对称应变源极/漏极结构的半导体元件其制作方法 Download PDF

Info

Publication number
CN111435679B
CN111435679B CN201910030933.8A CN201910030933A CN111435679B CN 111435679 B CN111435679 B CN 111435679B CN 201910030933 A CN201910030933 A CN 201910030933A CN 111435679 B CN111435679 B CN 111435679B
Authority
CN
China
Prior art keywords
region
layer
substrate
stress
trench
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910030933.8A
Other languages
English (en)
Other versions
CN111435679A (zh
Inventor
杨柏宇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to CN201910030933.8A priority Critical patent/CN111435679B/zh
Priority to US16/260,158 priority patent/US10903362B2/en
Publication of CN111435679A publication Critical patent/CN111435679A/zh
Priority to US17/118,524 priority patent/US11444195B2/en
Priority to US17/120,243 priority patent/US11444196B2/en
Application granted granted Critical
Publication of CN111435679B publication Critical patent/CN111435679B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7847—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate using a memorization technique, e.g. re-crystallization under strain, bonding on a substrate having a thermal expansion coefficient different from the one of the region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明公开一种具有非对称应变源极/漏极结构的半导体元件其制作方法，其中该半导体元件包含：一基底，具有一上表面；一第一区域，位于该基底中；一第二区域，位于该基底中，并与该第一区域间隔开；一通道区域，介于该第一区域与该第二区域之间；一栅极结构，位于该通道区域上；m个差排，位于该第一区域内，其中m为大于或等于1的整数；以及n个差排，位于该第二区域内，其中n为大于或等于0的整数，又其中m大于n。

Description

具有非对称应变源极/漏极结构的半导体元件其制作方法
技术领域
本发明涉及半导体制作工艺技术领域，特别是涉及一种具有非对称(asymmetric)应变(strained)源极/漏极结构的场效晶体管其制作方法。
背景技术
已知，随着半导体元件尺寸的不断缩小，为顾及元件性能，常导致在设计时需要有所取舍，例如，在驱动电流(drive current)与接面漏电(junction leakage)两者之间的取舍。举例来说，在场效晶体管(FET)元件中，源极侧特性是较小的逼近度由于较高的应力而能产生较高的驱动电流，漏极侧特性是较小的逼近度则会导致较高的接面漏电。
此外，诸如场效晶体管元件的半导体元件通常使用垂直注入制作工艺来建构基底中掺杂区域。这使得元件通常在基底中具有对称的源极/漏极(S/D)结构。因此，如何同时优化驱动电流和接面漏电这两种特性已是一项设计上的挑战。
发明内容
本发明提供了一种改良的半导体结构及其制作方法，可以同时优化场效晶体管元件的驱动电流和接面漏电这两种特性，提升元件效能。
本发明一方面提供一种形成半导体结构的方法。首先提供一基底，包含一上表面、一栅极结构，设于该上表面、间隙壁，设于该栅极结构的侧壁上、一第一区域(例如，源极区域)，位于该基底中，以及一第二区域(例如，漏极区域)，位于该基底中。干蚀刻该第一区域及该第二区域，分别形成一第一沟槽及一第二沟槽。再遮盖该第二区域。然后经由该第一沟槽湿蚀刻该第一区域，以形成一增宽的第一沟槽。再于该增宽的第一沟槽中及该第二沟槽中形成一应力诱发层。
根据本发明另一实施例，形成半导体结构的方法包括：提供一基底，包含一上表面、一栅极结构，设于该上表面、间隙壁，设于该栅极结构的侧壁上、一第一区域，位于该基底中，以及一第二区域，位于该基底中；遮盖该第二区域，并且非晶化该第一区域，如此于该第一区域内形成一非晶层；在该基底上沉积一应力层，其中该应力层顺形的覆盖该栅极结构、该间隙壁、该第一区域及该第二区域；以及再结晶该非晶层，如此于该第一区域内形成一差排。
本发明另一方面提供一种半导体结构，包含：一基底，具有一上表面；一第一区域，位于该基底中；一第二区域，位于该基底中，并与该第一区域间隔开；一通道区域，介于该第一区域与该第二区域之间；一栅极结构，位于该通道区域上；m个差排，位于该第一区域内，其中m为大于或等于1的整数；以及n个差排，位于该第二区域内，其中n为大于或等于0的整数，又其中m大于n。
为让本发明的上述目的、特征及优点能更明显易懂，下文特举优选实施方式，并配合所附的附图，作详细说明如下。然而如下的优选实施方式与附图仅供参考与说明用，并非用来对本发明加以限制者。
附图说明
图1至图4为本发明一实施例所绘示的一种PMOS晶体管结构的制作方法剖面示意图；
图5至图11为本发明另一实施例所绘示的一种NMOS晶体管结构的制作方法剖面示意图；
图12至图13为本发明又另一实施例所绘示的一种NMOS晶体管结构的制作方法剖面示意图；
图14及图15为本发明其他实施例NMOS晶体管结构的不同变化的示意图；
图16至图21为本发明又另一实施例所绘示的一种NMOS晶体管结构的制作方法剖面示意图。
主要元件符号说明
1 PMOS晶体管结构
100 基底
100a 上表面
101 N型阱
2～6 NMOS晶体管结构
20 栅极结构
202 间隙壁
210 多晶硅层
220 栅极介电层
230 氮化硅盖层
30 第一区域
301 LDD区
302 源极重掺杂区
310 第一沟槽
320 沟槽
330 增宽的第一沟槽
330a 底面
330b 侧壁
350、370 应力诱发层
40 第二区域
401 LDD区
402 漏极重掺杂区
410 第二沟槽
450 应力诱发层
500 遮盖层
60 离子注入制作工艺
600 光致抗蚀剂图案
610、620 非晶硅层
611、612 差排
70 应力层
711、712 差排
具体实施方式
在下文中，将参照附图说明细节，该些附图中的内容也构成说明书细节描述的一部分，并且以可实行该实施例的特例描述方式来绘示。下文实施例已描述足够的细节使该领域的一般技术人士得以具以实施。
当然，也可采行其他的实施例，或是在不悖离文中所述实施例的前提下作出任何结构性、逻辑性、及电性上的改变。因此，下文的细节描述不应被视为是限制，反之，其中所包含的实施例将由随附的权利要求来加以界定。
本发明披露一种改良的场效晶体管元件及其制作方法，可以同时优化场效晶体管元件的驱动电流和接面漏电，提升元件效能。
请参阅图1至图4，其为依据本发明一实施例所绘示的一种PMOS晶体管结构1的制作方法剖面示意图。如图1所示，首先，提供一基底100，例如，P型硅基底，但不限于此。基底100中可以形成有一N型阱101。基底100包含一上表面100a。根据本发明实施例，在上表面100a上形成有一栅极结构20，例如，包括一多晶硅层210、一栅极介电层220以及一氮化硅盖层230，但不限于此。在栅极结构20的各侧壁上可以设有一间隙壁202，例如，氮化硅间隙壁，但不限于此。
此外，在基底100中另有一第一区域30以及一第二区域40，分别位于栅极结构20的相对两侧。第一区域30以及一第二区域40彼此分隔，互不重叠。在第一区域30以及一第二区域40之间具有一通道区域200。根据本发明实施例，第一区域30是作为场效晶体管元件的源极区域，第二区域40是作为场效晶体管元件的漏极区域。
根据本发明实施例，在第一区域30及第二区域40内分别设有一轻掺杂漏极(lightly doped drain，LDD)区301及LDD区401。LDD区301及LDD区401设于N型阱101中。例如，LDD区301及LDD区401可以是P型LDD区。
如图2所示，接着进行一干蚀刻制作工艺，例如，各向异性干蚀刻制作工艺或反应性离子干蚀刻制作工艺等，向下蚀刻第一区域30及第二区域40的基底100，并且蚀穿LDD区301及LDD区401，分别形成一第一沟槽310及一第二沟槽410。
如图3所示，接着遮盖第二区域40。例如，于基底100上全面沉积一遮盖层500，例如，氮化硅层，其中遮盖层500覆盖栅极结构20、间隙壁202、第一区域30，与第二区域40。接着，可以利用光刻及蚀刻制作工艺，去除部分的遮盖层500，以显露出第一区域30。剩下的遮盖层500仅遮盖住第二区域40、邻近第二区域40的间隙壁202及部分的栅极结构20。
接着，进行一湿蚀刻制作工艺，经由第一沟槽310湿蚀刻第一区域30，以形成一增宽的第一沟槽330。上述湿蚀刻制作工艺可以包括含羟基(OH)的物质，包括，但不限于，氢氧化钾、氢氧化四甲基铵(TMAH)或氢氧化钠。根据本发明实施例，增宽的第一沟槽330可以具有一六角形剖面轮廓。根据本发明实施例，增宽的第一沟槽330可以具有一底面330a及侧壁330b，例如，底面330a及侧壁330b可以是<111>晶向的硅表面。
此时，第一区域30内形成的增宽的第一沟槽330略微朝向栅极结构20正下方的区域(即通道区域200)延伸，而第二区域40内的第二沟槽410因为未经过湿蚀刻，故无此结构。
接着，如图4所示，在湿蚀刻第一区域30之后，去除剩余的遮盖层500，显露出第一区域30及第二区域40。然后，同时于增宽的第一沟槽330中及第二沟槽410中分别形成一应力诱发层350及一应力诱发层450，例如，硅锗(SiGe)层。根据本发明实施例，应力诱发层350、450可以利用选择性外延法形成，但不限于此。后续，可以继续进行源极和漏极的重掺杂离子注入，分别于第一区域30内形成一源极重掺杂区302，于第二区域40内形成一漏极重掺杂区402。例如，源极重掺杂区302和漏极重掺杂区402可以是P型重掺杂区。
从图4可看出，在第一区域30的应力诱发层350的体积较在第二区域40的应力诱发层450的体积更大，且更接近栅极结构20正下方的通道区域200，如此构成非对称应变源极/漏极结构，这使得源极的应力诱发层350能够更逼近PMOS晶体管结构1的通道区域200，能够在通道区域200诱发出更大的应力，藉以提升PMOS晶体管结构1的驱动电流。
另一方面，第二区域40的应力诱发层450，由于其体积较小且距离通道区域200较远，故可以降低漏极端的接面漏电，因此，本发明具有非对称应变源极/漏极结构的场效晶体管能够同时优化驱动电流和接面漏电这两种特性。
请参阅图5至图11，其为依据本发明另一实施例所绘示的一种NMOS晶体管结构2的制作方法剖面示意图，其中，相同或类似的元件、结构或材料层仍沿用相同的符号来表示。
如图5所示，首先，同样提供一基底100，例如，P型硅基底，但不限于此。基底100包含一上表面100a。根据本发明实施例，在上表面100a上形成有一栅极结构20，例如，包括一多晶硅层210、一栅极介电层220以及一氮化硅盖层230，但不限于此。在栅极结构20的各侧壁上可以设有一间隙壁202，例如，氮化硅间隙壁，但不限于此。
此外，在基底100中另有一第一区域30以及一第二区域40，分别位于栅极结构20的相对两侧。第一区域30以及一第二区域40彼此分隔，互不重叠。根据本发明实施例，第一区域30是作为场效晶体管元件的源极区域，第二区域40是作为场效晶体管元件的漏极区域。
根据本发明实施例，在第一区域30及第二区域40内分别设有一LDD区301及LDD区401。例如，LDD区301及LDD区401可以是N型LDD区。
如图6所示，接着，遮盖第二区域40。例如，以一光致抗蚀剂图案600，完全遮盖第二区域40。光致抗蚀剂图案600可以仅遮盖住第二区域40、邻近第二区域40的间隙壁202及部分的栅极结构20。然后，进行一离子注入制作工艺60，将掺质，例如，硅(Si)、锗(Ge)或氙(Xe)等离子，注入第一区域30内的基底100中，以非晶化第一区域30，如此仅于第一区域30内形成一非晶硅层610。
如图7和图8所示，进行一应力存储技术(stress memorization technique，SMT)制作工艺。例如，先于基底100上沉积一应力层70，其中应力层70顺形的覆盖栅极结构20、间隙壁202、第一区域30、第一区域30内的非晶硅层610，及第二区域40。根据本发明实施例，应力层70可以包含氮化硅层、氧化硅层或氮氧化硅层，但不限于此。根据本发明实施例，应力层70可以具有一伸张(tensile)应力。
然后，进行一退火制作工艺，再结晶非晶层610，如此仅于第一区域30内形成一差排(dislocation)611，如图8所示。根据本发明实施例，上述退火制作工艺可以是两步骤退火制作工艺，例如，第一阶段退火的温度是介于400至750℃，而第二阶段退火的温度是大于900℃。
如图9所示，接着去除应力层70，显露出第二区域40。此时，在第一区域30内形成的差排611可以提供通道区域200适当的伸张应力，如此构成一应变源极结构。
此外，根据本发明另一实施例，可以重复图6至图9的步骤，如此于第一区域30内形成多个差排611，如图10所示，以增加源极的伸张应力。最后，可以继续进行源极和漏极的重掺杂离子注入，分别于第一区域30内形成一源极重掺杂区302，在第二区域40内形成一漏极重掺杂区402。例如，源极重掺杂区302和漏极重掺杂区402可以是N型重掺杂区，如此形成具有非对称应变源极/漏极结构的NMOS场效晶体管2，如图11所示。
请参阅图12至图13，其为依据本发明又另一实施例所绘示的一种NMOS晶体管结构3的制作方法剖面示意图，其中，相同或类似的元件、结构或材料层仍沿用相同的符号来表示。为简化说明，图12的步骤是接续图9的步骤之后进行。
如图12所示，去除应力层70之后，可以于第一区域30内形成一沟槽320。沟槽320可以是以各向异性干蚀刻形成的沟槽，且邻近间隙壁202(或者说是对准间隙壁202的外侧壁而形成的)。在第一区域30内的差排611的上部会被蚀除，但是其下部仍会保留在第一沟槽320底部处。
如图13所示，然后于沟槽320内形成一应力诱发层370，例如，磷化硅(SiP)外延层或碳化硅(SiC)外延层。根据本发明实施例，应力诱发层370可以利用选择性外延法形成，但不限于此。根据本发明实施例，在成长出应力诱发层370时，会在应力诱发层370中形成差排711。
最后，可以继续进行源极和漏极的重掺杂离子注入，分别于第一区域30内形成一源极重掺杂区302，在第二区域40内形成一漏极重掺杂区402。例如，源极重掺杂区302和漏极重掺杂区402可以是N型重掺杂区，如此形成具有非对称应变源极/漏极结构的NMOS场效晶体管3。
请参阅图14及图15。图14及图15显示出本发明其他实施例NMOS晶体管结构的不同变化。
图14与图13的差别在于，图14中的NMOS晶体管结构4在其第一区域30中具有多个差排711。
图15与图14的差别在于，图15中的NMOS晶体管结构5在其第二区域40内也可以形成有应力诱发层370，并且在第二区域40内的应力诱发层370也可以形成有差排712，其中，在第二区域40内的应力诱发层370的差排712的数量少于在第一区域30内的应力诱发层370的差排711的数量。
根据本发明实施例，如图15所示，本发明一种NMOS晶体管结构5，包含一基底100，具有一上表面100a、一第一区域30，位于基底100中、一第二区域40，位于基底100中，并与第一区域30间隔开、一通道区域200，介于第一区域30与第二区域40之间、一栅极结构20，位于通道区域200上。第一区域30内可以有m个差排711，其中m为大于或等于1的整数，而第二区域40内可以有n个差排712，其中n为大于或等于0的整数，又其中m大于n，例如m＝3，n＝1。第一区域30与第二区域40均为N型掺杂区域。第二区域40另包含一应力诱发层370，而n个差排712设于应力诱发层370中。应力诱发层370包含磷化硅层或碳化硅层。
请参阅图16至图21，其为依据本发明又另一实施例所绘示的一种NMOS晶体管结构6的制作方法剖面示意图，其中，相同或类似的元件、结构或材料层仍沿用相同的符号来表示。
如图16所示，首先，同样提供一基底100，例如，P型硅基底，但不限于此。基底100包含一上表面100a。根据本发明实施例，在上表面100a上形成有一栅极结构20，例如，包括一多晶硅层210、一栅极介电层220以及一氮化硅盖层230，但不限于此。在栅极结构20的各侧壁上可以设有一间隙壁202，例如，氮化硅间隙壁，但不限于此。
此外，在基底100中另有一第一区域30以及一第二区域40，分别位于栅极结构20的相对两侧。第一区域30以及一第二区域40彼此分隔，互不重叠。根据本发明实施例，第一区域30是作为场效晶体管元件的源极区域，第二区域40是作为场效晶体管元件的漏极区域。
根据本发明实施例，在第一区域30及第二区域40内分别设有一LDD区301及LDD区401。例如，LDD区301及LDD区401可以是N型LDD区。
然后，如图17所示，进行一离子注入制作工艺60，将掺质，例如，硅(Si)、锗(Ge)或氙(Xe)等离子，注入第一区域30及第二区域40内的基底100中，以非晶化第一区域30及第二区域40，如此分别于第一区域30及第二区域40内形成一非晶硅层610及一非晶硅层620。
如图18和图19所示，进行一应力存储技术(SMT)制作工艺。例如，先于基底100上沉积一应力层70，其中应力层70顺形的覆盖栅极结构20、间隙壁202、第一区域30、第一区域30内的非晶硅层610、第二区域40，及第二区域40内的非晶硅层620。根据本发明实施例，应力层70可以包含氮化硅层、氧化硅层或氮氧化硅层，但不限于此。根据本发明实施例，应力层70可以具有一伸张应力。
然后，进行一退火制作工艺，再结晶非晶层610及非晶硅层620，如此于第一区域30内形成一差排611，在第二区域40内形成一差排612，如图19所示。根据本发明实施例，上述退火制作工艺可以是两步骤退火制作工艺，例如，第一阶段退火的温度是介于400至750℃，而第二阶段退火的温度是大于900℃。
如图20所示，接着去除应力层70，显露出栅极结构20、间隙壁202、第一区域30及第二区域40。此时，在第一区域30及第二区域40内形成的差排611及差排612可以提供通道区域200适当的伸张应力。可以重复图6至图9的步骤，如此于第一区域30内形成多个差排611，如图21所示，以增加源极的伸张应力。
最后，可以继续进行源极和漏极的重掺杂离子注入，分别于第一区域30内形成一源极重掺杂区302，在第二区域40内形成一漏极重掺杂区402。例如，源极重掺杂区302和漏极重掺杂区402可以是N型重掺杂区，如此形成具有非对称应变源极/漏极结构的NMOS场效晶体管6。
根据本发明实施例，如图21所示，本发明一种NMOS晶体管结构6，包含一基底100，具有一上表面100a、一第一区域30，位于基底100中、一第二区域40，位于基底100中，并与第一区域30间隔开、一通道区域200，介于第一区域30与第二区域40之间、一栅极结构20，位于通道区域200上。第一区域30内可以有m个差排611，其中m为大于或等于1的整数，而第二区域40内可以有n个差排612，其中n为大于或等于0的整数，又其中m大于n，例如m＝3，n＝1。第一区域30与第二区域40均为N型掺杂区域。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (13)

1.一种形成半导体结构的方法，包含：
提供基底，包含上表面、设于该上表面的栅极结构、设于该栅极结构的侧壁上的间隙壁、位于该基底中的第一区域以及位于该基底中的第二区域，其中该第一区域以及该第二区域分别位于该栅极结构的相对两侧，且该第一区域以及该第二区域设置为与该栅极结构直接相邻；
干蚀刻该第一区域及该第二区域，分别在该第一区域中形成第一沟槽及在该第二区域中形成第二沟槽，其中该第一沟槽和该第二沟槽均与该栅极结构直接相邻；
在该基底上全面沉积遮盖层，其中该遮盖层覆盖该栅极结构、该间隙壁、该第一区域，与该第二区域；
去除部分的该遮盖层，以显露出该第一区域中的该第一沟槽，其中该第二沟槽被该遮盖层填充；
经由该第一沟槽湿蚀刻该第一区域，以形成一增宽的第一沟槽；以及
在湿蚀刻该第一区域之后，去除该遮盖层；
在去除该遮盖层之后，在该第二沟槽及该增宽的第一沟槽中中形成应力诱发层。
2.如权利要求1所述的方法，其中该增宽的第一沟槽具有六角形剖面轮廓。
3.如权利要求1所述的方法，其中该应力诱发层包含硅锗层。
4.一种形成半导体结构的方法，包含：
提供基底，包含上表面、一设于该上表面的栅极结构、设于该栅极结构的侧壁上的间隙壁、位于该基底中的第一区域以及位于该基底中的第二区域；
遮盖该第二区域并且非晶化该第一区域，如此于该第一区域内形成非晶层；
在该基底上沉积应力层，其中该应力层顺形的覆盖该栅极结构、该间隙壁、该第一区域及该第二区域；
再结晶该非晶层，如此于该第一区域内形成一差排；
在该第一区域内形成第一沟槽；以及
在该第一沟槽内形成应力诱发层。
5.如权利要求4所述的方法，其中所述遮盖该第二区域，并且非晶化该第一区域包含：
形成光致抗蚀剂图案，完全遮盖该第二区域；以及
进行离子注入，将掺质注入该第一区域中。
6.如权利要求4所述的方法，其中该应力层包含氮化硅层、氧化硅层或氮氧化硅层。
7.如权利要求4所述的方法，其中所述再结晶该非晶层包含：
进行退火制作工艺。
8.如权利要求4所述的方法，其中另包含：
去除该应力层。
9.一种半导体元件，其特征在于，包含：
基底，具有上表面；
第一区域，位于该基底中，其中该第一区域包括应力诱发层；
第二区域，位于该基底中，并与该第一区域间隔开；
通道区域，介于该第一区域与该第二区域之间；
栅极结构，位于该通道区域上；
m个差排，位于该第一区域内，其中m为大于或等于1的整数，其中该m个差排的每一个从该应力诱发层延伸到该应力诱发层下方的该基底中；以及
n个差排，位于该第二区域内，其中n为大于或等于0的整数，又其中m大于n。
10.如权利要求9所述的半导体元件，其中该第二区域另包含另一应力诱发层。
11.如权利要求10所述的半导体元件，其中该应力诱发层和该另一应力诱发层包含磷化硅层或碳化硅层。
12.如权利要求9所述的半导体元件，其中该第一区域与该第二区域均为N型掺杂区域。
13.如权利要求9所述的半导体元件，其中m＝3，n＝1。
CN201910030933.8A 2019-01-14 2019-01-14 具有非对称应变源极/漏极结构的半导体元件其制作方法 Active CN111435679B (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN201910030933.8A CN111435679B (zh) 2019-01-14 2019-01-14 具有非对称应变源极/漏极结构的半导体元件其制作方法
US16/260,158 US10903362B2 (en) 2019-01-14 2019-01-29 Semiconductor device with asymmetric strained source/drain structure and fabrication method
US17/118,524 US11444195B2 (en) 2019-01-14 2020-12-10 Method for fabricating semiconductor device with asymmetric strained source/drain structure
US17/120,243 US11444196B2 (en) 2019-01-14 2020-12-13 Method for fabricating semiconductor device with asymmetric strained source/drain structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910030933.8A CN111435679B (zh) 2019-01-14 2019-01-14 具有非对称应变源极/漏极结构的半导体元件其制作方法

Publications (2)

Publication Number Publication Date
CN111435679A CN111435679A (zh) 2020-07-21
CN111435679B true CN111435679B (zh) 2023-06-13

Family

ID=71516866

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910030933.8A Active CN111435679B (zh) 2019-01-14 2019-01-14 具有非对称应变源极/漏极结构的半导体元件其制作方法

Country Status (2)

Country Link
US (3) US10903362B2 (zh)
CN (1) CN111435679B (zh)

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7355221B2 (en) * 2005-05-12 2008-04-08 International Business Machines Corporation Field effect transistor having an asymmetrically stressed channel region
US7465976B2 (en) 2005-05-13 2008-12-16 Intel Corporation Tunneling field effect transistor using angled implants for forming asymmetric source/drain regions
US7342284B2 (en) * 2006-02-16 2008-03-11 United Microelectronics Corp. Semiconductor MOS transistor device and method for making the same
US8304805B2 (en) * 2009-01-09 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor diodes fabricated by aspect ratio trapping with coalesced films
US8952429B2 (en) 2010-09-15 2015-02-10 Institute of Microelectronics, Chinese Academy of Sciences Transistor and method for forming the same
CN102468164B (zh) 2010-10-29 2014-10-08 中国科学院微电子研究所 晶体管及其制造方法
CN102468166B (zh) * 2010-10-29 2015-01-28 中国科学院微电子研究所 晶体管及其制造方法
US8828817B2 (en) * 2012-01-23 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of forming the same
US8841190B2 (en) 2012-03-30 2014-09-23 The Institute of Microelectronics Chinese Academy of Science MOS device for making the source/drain region closer to the channel region and method of manufacturing the same
US8877599B2 (en) 2012-05-15 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a semiconductor device
US8889501B2 (en) 2012-06-01 2014-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming MOS devices with raised source/drain regions
US8691644B2 (en) * 2012-07-05 2014-04-08 Texas Instruments Incorporated Method of forming a CMOS device with a stressed-channel NMOS transistor and a strained-channel PMOS transistor
CN104217953B (zh) * 2013-06-05 2017-06-13 中芯国际集成电路制造(上海)有限公司 Pmos晶体管及其制作方法
US8895396B1 (en) * 2013-07-11 2014-11-25 United Microelectronics Corp. Epitaxial Process of forming stress inducing epitaxial layers in source and drain regions of PMOS and NMOS structures
US9406797B2 (en) * 2014-03-07 2016-08-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor integrated circuit with dislocations
KR102202754B1 (ko) 2014-08-14 2021-01-15 삼성전자주식회사 반도체 장치
TWI636574B (zh) * 2014-12-03 2018-09-21 聯華電子股份有限公司 半導體結構

Also Published As

Publication number Publication date
CN111435679A (zh) 2020-07-21
US20210098622A1 (en) 2021-04-01
US11444195B2 (en) 2022-09-13
US20210098623A1 (en) 2021-04-01
US10903362B2 (en) 2021-01-26
US11444196B2 (en) 2022-09-13
US20200227554A1 (en) 2020-07-16

Similar Documents

Publication Publication Date Title
US9514995B1 (en) Implant-free punch through doping layer formation for bulk FinFET structures
US10868175B2 (en) Method for manufacturing semiconductor structure
US7745847B2 (en) Metal oxide semiconductor transistor
KR101410092B1 (ko) 고 이동도 및 고 에너지 대역갭 물질들을 갖는 반도체 구조물 및 방법
US8940602B2 (en) Self-aligned structure for bulk FinFET
KR100699839B1 (ko) 다중채널을 갖는 반도체 장치 및 그의 제조방법.
CN107403835B (zh) 半导体装置及其制作工艺
US8183640B2 (en) Method of fabricating transistors and a transistor structure for improving short channel effect and drain induced barrier lowering
US8106466B2 (en) MOS transistor and method for fabricating the same
US7670914B2 (en) Methods for fabricating multiple finger transistors
US10014406B2 (en) Semiconductor device and method of forming the same
US9093473B2 (en) Method for fabricating metal-oxide semiconductor transistor
CN107924915A (zh) 用于多阈值PMOS晶体管的嵌入式SiGe工艺
CN111435679B (zh) 具有非对称应变源极/漏极结构的半导体元件其制作方法
US8951873B2 (en) Semiconductor devices having encapsulated stressor regions and related fabrication methods
CN111435684B (zh) 具有应变通道的晶体管及其制作方法
TWI790476B (zh) 積體電路晶粒及其製造方法
US20170243954A1 (en) Method of fabricating finfet device
TWI533379B (zh) 半導體裝置及其製造方法
US20120315734A1 (en) Method for fabricating semiconductor device
KR19980068006A (ko) 반도체 소자 및 그 제조방법

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant