CN111435639A - 半导体结构及其形成方法 - Google Patents
半导体结构及其形成方法 Download PDFInfo
- Publication number
- CN111435639A CN111435639A CN201811605467.3A CN201811605467A CN111435639A CN 111435639 A CN111435639 A CN 111435639A CN 201811605467 A CN201811605467 A CN 201811605467A CN 111435639 A CN111435639 A CN 111435639A
- Authority
- CN
- China
- Prior art keywords
- dielectric layer
- interlayer dielectric
- gate electrode
- electrode material
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 105
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 239000010410 layer Substances 0.000 claims abstract description 131
- 238000002955 isolation Methods 0.000 claims abstract description 123
- 239000011229 interlayer Substances 0.000 claims abstract description 101
- 239000007772 electrode material Substances 0.000 claims abstract description 90
- 238000000227 grinding Methods 0.000 claims abstract description 87
- 239000000758 substrate Substances 0.000 claims abstract description 50
- 238000011282 treatment Methods 0.000 claims abstract description 50
- 229910052751 metal Inorganic materials 0.000 claims abstract description 31
- 239000002184 metal Substances 0.000 claims abstract description 31
- 239000008367 deionised water Substances 0.000 claims abstract description 14
- 229910021641 deionized water Inorganic materials 0.000 claims abstract description 14
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims abstract description 14
- 238000011049 filling Methods 0.000 claims abstract description 12
- 239000012530 fluid Substances 0.000 claims abstract description 10
- 230000008569 process Effects 0.000 claims description 70
- 238000005498 polishing Methods 0.000 claims description 46
- 239000000463 material Substances 0.000 claims description 40
- 238000007517 polishing process Methods 0.000 claims description 37
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 239000000126 substance Substances 0.000 claims description 12
- 239000002002 slurry Substances 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 238000007781 pre-processing Methods 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 238000002203 pretreatment Methods 0.000 claims 1
- 230000000694 effects Effects 0.000 description 17
- 230000002378 acidificating effect Effects 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 125000006850 spacer group Chemical group 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 239000007788 liquid Substances 0.000 description 6
- 239000000243 solution Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- 239000003929 acidic solution Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 238000006703 hydration reaction Methods 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 229910003481 amorphous carbon Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000003801 milling Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000005461 lubrication Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 230000009291 secondary effect Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
- B24B37/042—Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Mechanical Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
一种半导体结构及其形成方法,形成方法包括:提供基底,基底上形成有伪栅结构,伪栅结构露出的基底上形成有层间介质层,层间介质层露出伪栅结构顶部;在相邻伪栅结构之间的层间介质层中形成隔离结构,隔离结构还延伸至基底中;形成隔离结构后,去除伪栅结构,在层间介质层内形成栅极开口;向栅极开口内填充栅电极材料,栅电极材料还覆盖层间介质层顶部;进行至少一次研磨处理,去除高于层间介质层顶部的栅电极材料,保留栅极开口内的栅电极材料作为栅电极层,研磨处理步骤包括:采用金属用研磨液进行第一研磨处理;采用去离子水进行第二研磨处理。通过第二研磨处理,降低层间介质层顶面形成有栅电极材料的残留物的概率,改善了器件性能。
Description
技术领域
本发明实施例涉及半导体制造领域,尤其涉及一种半导体结构及其形成方法。
背景技术
集成电路尤其超大规模集成电路的主要半导体器件是金属-氧化物-半导体场效应管(MOS晶体管)。随着超大规模集成电路的发展趋势,集成电路越来越复杂,半导体器件技术节点不断减小。当半导体器件尺寸减小到一定程度时,各种因为半导体器件的物理极限所带来的二级效应相继出现,例如:半导体器件漏电流大的问题。为了改善漏电流的问题,目前主要采用高k栅介质材料代替传统的二氧化硅栅介质材料,并使用金属作为栅电极,以避免高k材料与传统栅电极材料发生费米能级钉扎效应以及硼渗透效应。
而且,随着半导体器件尺寸的不断缩小,相邻晶体管之间的距离也随之缩小,相邻晶体管的源漏掺杂层容易出现相连(merge)的现象,从而引起相邻晶体管源区和漏区之间的桥接。为了防止相邻晶体管源区和漏区之间的桥接(source-drain bridge),现有技术引入了单扩散隔断(single diffusion break,SDB)隔离结构的制造技术。
发明内容
本发明实施例解决的问题是提供一种半导体结构及其形成方法,改善器件性能。
为解决上述问题,本发明实施例提供一种半导体结构的形成方法,包括:提供基底,所述基底上形成有伪栅结构,所述伪栅结构露出的基底上形成有层间介质层,所述层间介质层覆盖所述伪栅结构侧壁且露出所述伪栅结构顶部;在相邻所述伪栅结构之间的所述层间介质层中形成隔离结构,所述隔离结构还延伸至所述基底中;形成所述隔离结构后,去除所述伪栅结构,在所述层间介质层内形成栅极开口;向所述栅极开口内填充栅电极材料,所述栅电极材料还覆盖所述层间介质层顶部;进行至少一次研磨处理,去除高于所述层间介质层顶部的栅电极材料,保留所述栅极开口内的栅电极材料作为栅电极层,所述研磨处理的步骤包括:采用金属用研磨液对栅电极材料进行第一研磨处理;在所述第一研磨处理后,采用去离子水对隔离结构进行第二研磨处理。
可选的,向所述栅极开口内填充栅电极材料之后,在进行所述研磨处理之前,还包括:对所述栅电极材料进行预处理,去除部分厚度的所述栅电极材料,露出所述隔离结构顶部。
可选的,采用化学机械研磨方式和回刻方式中的一种或两种,进行所述预处理。
可选的,所述研磨处理的次数为3次至12次。
可选的,在每一次研磨处理中,所述第二研磨处理的工艺时间为5秒至15秒。
可选的,在每一次研磨处理中,所述第二研磨处理的工艺时间为10秒至15秒。
可选的,在所述第一研磨处理的步骤中,所述金属用研磨液的PH值为2至6。
可选的,所述第二研磨处理的参数包括:下压力为1.0psi至3.0psi,基座转速为30rpm至100rpm,去离子水的流速为100ml/min至300ml/min。
可选的,所述隔离结构的材料为氮化硅、多晶硅或金属氮化物。
可选的,所述隔离结构的硬度高于所述层间介质层的硬度。
可选的,所述层间介质层的材料为氧化硅,所述隔离结构的材料为氮化硅。
可选的,形成所述隔离结构的步骤包括:依次刻蚀相邻所述伪栅结构间的层间介质层和部分厚度基底,形成位于所述层间介质层和基底内的沟槽;向所述沟槽内填充隔离材料,所述隔离材料还覆盖所述层间介质层顶部;采用平坦化工艺,去除高于所述层间介质层顶部的隔离材料,保留所述沟槽内的隔离材料作为所述隔离结构。
可选的,所述平坦化工艺为化学机械研磨工艺和回刻工艺中的一种或两种。
可选的,向所述栅极开口内填充栅电极材料的步骤中,所述栅电极材料为W、Al、Cu、Ag、Au、Pt、Ni或Ti。
相应的,本发明实施例还提供一种采用本发明所述形成方法所形成的半导体结构。
与现有技术相比,本发明实施例的技术方案具有以下优点:
本发明实施例向栅极开口内填充栅电极材料后,进行至少一次研磨处理以去除高于层间介质层顶部的栅电极材料,保留所述栅极开口内的栅电极材料作为栅电极层,所述研磨处理包括依次进行的第一研磨处理和第二研磨处理,且第一研磨处理采用金属用研磨液、第二研磨采用去离子水,其中,第一研磨处理用于去除栅电极材料,金属用研磨液通常为酸性研磨液,在每一次第一研磨处理后,晶圆(wafer)表面仍有酸性溶液残留,因此在相继进行的第二研磨处理过程中,所述隔离结构处于酸性环境中,所述隔离结构发生水合反应,使得受到第二研磨处理影响的隔离结构的硬度和强度下降,易于通过该第二研磨处理以减薄所述隔离结构;为此,即使在层间介质层和基底中形成隔离结构后,出现所述隔离结构顶部凸出于层间介质层顶部的情况,也能够在去除高于所述层间介质层顶部的栅电极材料的步骤中,去除凸出于层间介质层的隔离结构,使得位于所述层间介质层顶面的栅电极材料能够暴露在第一研磨处理的工艺环境中,相应降低去除所述层间介质层顶面的栅电极材料的难度,从而显著降低在所述层间介质层顶面形成栅电极材料的残留物的概率,进而改善器件性能。
附图说明
图1至图6是一种半导体结构的形成方法中各步骤对应的结构示意图;
图7至图14是本发明半导体结构的形成方法一实施例中各步骤对应的结构示意图;
图15是图7至图14所示实施例中不同研磨条件下,栅电极材料和隔离结构总去除量的柱状图、以及去除选择比的折线图。
具体实施方式
目前,在半导体结构中引入SDB隔离结构后,容易导致器件性能下降。现结合一种半导体结构的形成方法分析其性能下降的原因。
参考图1至图6,示出了一种半导体结构的形成方法中各步骤对应的结构示意图。
参考图1,提供基底10,所述基底10上形成有伪栅结构20,所述伪栅结构20露出的基底10上形成有层间介质层30,所述层间介质层30覆盖所述伪栅结构20侧壁且露出所述伪栅结构20顶部。
参考图2,依次刻蚀相邻所述伪栅结构20之间的层间介质层30和部分厚度的基底10,形成沟槽35。
参考图3,在所述沟槽35(如图2所示)中形成SDB隔离结构40。
为了提高SDB隔离结构40的隔离效果,目前SDB隔离结构40选用的材料通常为氮化硅。
参考图4,形成所述SDB隔离结构40后,去除所述伪栅结构20(如图3所示),在所述层间介质层30内形成栅极开口32。
参考图5,向所述栅极开口32(如图4所示)内填充栅电极材料55,所述栅电极材料55还覆盖所述层间介质层30顶部。
参考图6,采用化学机械研磨工艺对所述栅电极材料55(如图5所示)进行平坦化处理,保留所述栅极开口32(如图4所示)内的栅电极材料55作为栅电极层50。
在沟槽35中形成SDB隔离结构40的制程通常包括隔离材料填充的步骤以及对隔离材料进行平坦化(例如:化学机械研磨)处理的步骤,由于层间介质层30的材料通常为氧化硅,层间介质层30较为松软,在形成SDB隔离结构40的平坦化制程中,层间介质层30顶面容易出现碟陷(dishing)问题,从而导致SDB隔离结构40顶部凸出于层间介质层30顶部,而且,SDB隔离结构40的图形密集度(pattern density)越低,层间介质层30的碟陷问题越严重。
栅电极材料55通常为金属材料(例如:W),为此,采用化学机械研磨工艺对所述栅电极材料55(如图4所示)进行平坦化处理时,去除栅电极材料55所采用的研磨液通常为酸性研磨液。
但是,该研磨液对SDB隔离结构40的去除速率(remove rate,RR)较低,导致凸出于层间介质层30的SDB隔离结构40对栅电极材料55的研磨起到阻挡作用,在完成对栅电极材料55的研磨后,层间介质层30顶部容易形成有金属残留物51,进而对器件的性能产生不良影响。
为了解决所述技术问题,本发明实施例向栅极开口内填充栅电极材料后,进行至少一次研磨处理以去除高于层间介质层顶部的栅电极材料,保留所述栅极开口内的栅电极材料作为栅电极层,所述研磨处理包括依次进行的第一研磨处理和第二研磨处理,且第一研磨处理采用金属用研磨液、第二研磨采用去离子水,其中,第一研磨处理用于去除栅电极材料,金属用研磨液通常为酸性研磨液,在每一次第一研磨处理后,晶圆表面仍有酸性溶液残留,因此在相继进行的第二研磨处理过程中,所述隔离结构处于酸性环境中,所述隔离结构发生水合反应,使得受到第二研磨处理影响的隔离结构的硬度和强度下降,易于通过该第二研磨处理以减薄所述隔离结构;为此,即使出现隔离结构凸出于层间介质层的情况,也能够在去除高于所述层间介质层顶部的栅电极材料的步骤中,去除凸出于层间介质层的隔离结构,使得位于所述层间介质层顶面的栅电极材料能够暴露在第一研磨处理的工艺环境中,相应降低了去除层间介质层顶面的栅电极材料的难度,从而显著降低在层间介质层顶面形成栅电极材料的残留物的概率,进而改善器件性能。
为使本发明实施例的上述目的、特征和优点能够更为明显易懂,下面结合附图对本发明的具体实施例做详细的说明。
图7至图14是本发明半导体结构的形成方法一实施例中各步骤对应的结构示意图。
参考图7,提供基底100,所述基底100上形成有伪栅结构200,所述伪栅结构200露出的基底100上形成有层间介质层300,所述层间介质层300覆盖所述伪栅结构200侧壁且露出所述伪栅结构200顶部。
所述基底100用于为后续制程提供工艺平台。
本实施例中,以所形成的器件为鳍式场效应晶体管为例,所述基底100包括衬底101以及凸出于所述衬底101的鳍部102。
具体地,所述衬底101的材料为硅。在另一些实施例中,所述衬底101的材料还可以为锗、锗化硅、碳化硅、砷化镓或镓化铟等其他材料,所述衬底还能够为绝缘体上的硅衬底或者绝缘体上的锗衬底等其他类型的衬底。
本实施例中,所述鳍部102与衬底101为一体结构。在其他实施例中,所述鳍部也可以是外延生长于衬底上的半导体层,从而达到精确控制所述鳍部高度的目的。
因此,本实施例中,所述鳍部102的材料与所述衬底101的材料相同,所述鳍部102的材料为硅。在其他实施例中,所述鳍部的材料还可以是锗、锗化硅、碳化硅、砷化镓或镓化铟等适宜于形成鳍部的半导体材料,所述鳍部的材料也可以与所述衬底的材料不同。
所述伪栅结构200用于为后续金属栅结构的形成占据空间位置。
本实施例中,所述伪栅结构200横跨所述鳍部102,且覆盖所述鳍部102的部分顶部和部分侧壁。
本实施例中,以所述伪栅结构200为单层结构为例,所述伪栅结构200的材料为多晶硅。
在另一些实施例中,在所述伪栅结构为单层结构的情况下,所述伪栅结构的材料还可以为氧化硅、氮化硅、氮氧化硅、碳化硅、碳氮化硅、碳氮氧化硅或非晶碳等其他材料。
在其他实施例中,所述伪栅结构还可以为叠层结构,包括伪栅氧化层以及位于所述伪栅氧化层上的伪栅层;其中,所述伪栅层的材料可以为多晶硅或非晶碳,所述伪氧化层的材料可以为氧化硅或氮氧化硅。
本实施例中,所述伪栅结构200侧壁上形成有侧墙250。
所述侧墙250用于定义后续源漏掺杂层的形成区域,还用于在后续工艺中对所述伪栅结构200侧壁起到保护作用。
所述侧墙250的材料可以为氧化硅、氮化硅、碳化硅、碳氮化硅、碳氮氧化硅、氮氧化硅、氮化硼和碳氮化硼中的一种或多种,所述侧墙250可以为单层结构或叠层结构。本实施例中,所述侧墙250为单层结构,所述侧墙250的材料为氮化硅。
本实施例中,在形成所述侧墙250后,在所述伪栅结构200和侧墙250露出的基底100上形成所述层间介质层300。
所述层间介质层300用于实现相邻器件之间的电隔离,还用于定义后续所形成金属栅结构的尺寸和位置。
所述层间介质层300的材料为绝缘材料。本实施例中,所述层间介质层300的材料为氧化硅。在其他实施例中,所述层间介质层的材料还可以为氮化硅或氮氧化硅等其他介质材料。
本实施例中,所述层间介质层300顶部和侧墙250顶部相齐平。
结合参考图8至图10,在相邻所述伪栅结构200之间的所述层间介质层300中形成隔离结构400(如图10所示),所述隔离结构400还延伸至所述基底100中。
所述隔离结构400作为SDB隔离结构,用于对相邻器件起到隔离作用。
随着器件尺寸的减小,沿所述鳍部110的延伸方向,相邻鳍部110末端之间的距离(head to head,HTH)越来越小,相邻金属栅结构之间的距离也越来越小,所述隔离结构400分布在鳍部102的延伸方向上,通过所述隔离结构400,能够使相邻器件之间实现隔离,降低相邻器件的源区和漏区之间发生桥接问题的概率,从而使得器件的性能和良率得以提升。
为此,本实施例中,沿垂直于所述伪栅结构200侧壁的方向上,在相邻所述伪栅结构200之间形成所述隔离结构400。
本实施例中,所述隔离结构400的材料为氮化硅。氮化硅是常用的隔离材料,具有较好的隔离效果以及工艺兼容性。在另一些实施例中,所述隔离结构的材料还可以为多晶硅或金属氮化物(例如:氮化钛或氮化钽等)。
为此,所述隔离结构400的硬度高于所述层间介质层300的硬度。
具体地,形成所述隔离结构400的步骤包括:
参考图8,依次刻蚀相邻所述伪栅结构200之间的层间介质层300和部分厚度基底100,形成位于所述层间介质层300和基底100内的沟槽350。
所述沟槽350用于为后续隔离结构的形成提供空间位置。
本实施例中,依次刻蚀所述层间介质层300和部分厚度的鳍部102,使得所述层间介质层300和鳍部102围成所述沟槽350,即所述沟槽350底部位于所述鳍部102中。在其他实施例中,还可以依次刻蚀所述层间介质层、鳍部和部分厚度的衬底,使得所述层间介质层、鳍部和衬底围成所述沟槽,所述沟槽底部相应位于所述衬底中。
参考图9,向所述沟槽350(如图8所示)内填充隔离材料450,所述隔离材料450还覆盖所述层间介质层300顶部。
本实施例中,所述隔离材料450为氮化硅,所述隔离材料450通过化学气相沉积的方式填充于所述沟槽350内。
参考图10,采用平坦化工艺,去除高于所述层间介质层300顶部的隔离材料450(如图9所示),保留所述沟槽350(如图8所示)内的隔离材料450作为所述隔离结构400。
本实施例中,所述平坦化工艺为化学机械研磨工艺。
在其他实施例中,还可以采用其他平坦化工艺。例如,对所述隔离材料进行回刻处理,以去除高于所述层间介质层顶部的隔离材料,或者,采用化学机械研磨和回刻处理相结合的工艺,去除高于所述层间介质层顶部的隔离材料。
需要说明的是,由于所述层间介质层300的硬度小于所述隔离结构400的硬度,因此在去除高于所述层间介质层300顶部的隔离材料450后,所述隔离结构400周边的层间介质层300顶面容易出现碟陷问题,即容易出现所述隔离结构400顶部凸出于所述层间介质层300顶部的情况,相应也会导致所述侧墙250凸出于所述层间介质层300。
参考图11,形成所述隔离结构400后,去除所述伪栅结构200(如图10所示),在所述层间介质层300内形成栅极开口320。
所述栅极开口320用于为后续形成金属栅结构提供空间位置。
本实施例中,去除所述伪栅结构200后,所述侧墙250和基底100围成所述栅极开口320。
参考图12,向所述栅极开口320(如图11所示)内填充栅电极材料550,所述栅电极材料550还覆盖所述层间介质层300顶部。
所述栅电极材料550用于为后续栅电极层的形成提供工艺基础,其中,栅电极层用于作为金属栅结构的一部分。
本实施例中,所述栅电极材料550为W。在其他实施例中,所述栅电极材料还可以为Al、Cu、Ag、Au、Pt、Ni或Ti。
为了为后续的研磨处理提供足够的工艺窗口,以提高后续所形成栅电极层的表面平坦度,所述栅电极材料550不仅填充于所述栅极开口320内,至少还覆盖所述层间介质层300顶部。
本实施例中,所述栅电极材料550还覆盖所述隔离结构400顶部和侧墙250顶部。
结合参考图13和图14,进行至少一次研磨处理,去除高于所述层间介质层300顶部的栅电极材料550(如图12所示),保留所述栅极开口320(如图11所示)内的栅电极材料550作为栅电极层500,所述研磨处理的步骤包括:采用金属用研磨液对所述栅电极材料550进行第一研磨处理;在所述第一研磨处理后,采用去离子水对所述隔离结构400进行第二研磨处理。
所述第一研磨处理用于去除栅电极材料550,因此所述金属用研磨液通常为酸性研磨液,在每一次第一研磨处理后,晶圆表面仍有酸性溶液残留,因此在相继进行的第二研磨处理过程中,所述隔离结构400处于酸性环境中,所述隔离结构400会发生水合反应,使得受到第二研磨处理影响的隔离结构400的硬度和强度下降,在第二研磨处理机械力的作用下,易于通过该第二研磨处理以减薄所述隔离结构400。
为此,在形成所述隔离结构400后,即使出现所述隔离结构400顶部凸出于层间介质层300顶部的情况,通过所述研磨处理,也能够在去除高于所述层间介质层300顶部的栅电极材料550的步骤中,去除凸出于层间介质层300的隔离结构400,使得位于所述层间介质层300顶面的栅电极材料550能够暴露在第一研磨处理的工艺环境中,相应降低了去除所述层间介质层300顶面的栅电极材料550的难度,从而避免在所述层间介质层300层顶面形成栅电极材料550的残留物,进而改善器件性能。
其中,去离子水还用于作为所述第二研磨处理的研磨液,并起到润滑作用,这不仅保障了第二研磨处理的正常进行,而且能够降低工艺成本、显著降低副作用的产生。
而且,去离子水作为所述第二研磨处理的研磨液,使得第二研磨处理的研磨液PH值较大,并在去离子水的作用下,去除了金属用研磨液中的研磨粒子,从而降低所述第二研磨处理对所述栅电极材料550和层间介质层300的影响。
相应的,即使出现所述侧墙250凸出于所述层间介质层300的情况,凸出于所述层间介质层300的侧墙250同样也能在所述研磨处理中被去除,使得去除所述层间介质层300顶面的栅电极材料550的效果得到进一步保障,相应还有利于提高各栅电极层500的高度均一性,以改善器件性能的均一性。
所述栅电极材料550为金属材料,因此,所述金属用研磨液为酸性研磨液,以保障较高的去除速率。酸性研磨液中具有较多的氧化剂,在第一研磨处理的过程中,通过金属用研磨液使栅电极材料550发生氧化,转化为金属氧化物,金属氧化物与金属相比更软,便于机械去除。
根据所述栅电极层500所选用的材料,选取相应PH值的金属用研磨液,以保证对所述栅电极材料550的研磨效果,且所述金属用研磨液为酸性研磨液。
其中,所述金属用研磨液的PH值不宜过大。如果所述PH值过大,则在后续第二研磨处理的过程中,在去离子水的作用下,容易导致隔离结构400所处的酸性环境变弱,从而降低第二研磨处理去除隔离结构400的去除效果。为此,本实施例中,所述金属用研磨液的PH值为2至6,例如为4或5。
需要说明的是,增加所述研磨处理的次数,则有利于增加第二研磨处理对所述隔离结构400的去除效果,相应的,在完成所述研磨处理后,所述层间介质层300层顶面有栅电极材料550的残留物的概率显著降低;但是,如果次数过多,则所述多次第二研磨处理的总时间相应增加,从而降低制造效率,而且,为了保证所形成栅电极层500的厚度能够满足工艺需求,次数的增加相应会导致单次第一研磨处理的时间减少,这容易降低第一研磨处理的工艺稳定性,从而对栅电极材料550的研磨效果造成不良影响。为此,本实施例中,为了保障较好的工艺效果,所述研磨处理的次数为3次至12次。
结合参考图15,图15示出了不同研磨条件下,栅电极材料和隔离结构总去除量的柱状图、以及去除选择比的折线图。
横坐标表示研磨处理的次数,主纵坐标表示栅电极材料和隔离结构的总去除量,次纵坐标表示去除选择比;其中,斜线填充的柱状图表示栅电极材料的总去除量,白色填充的柱状图表示隔离结构的总去除量;去除选择比指的是:栅电极材料总去除量和隔离结构总去除量的比值。
虚线框601表示的是未进行第二研磨处理的情况(即仅采用金属用研磨液进行一次研磨处理的情况),用作为比较基准,虚线框602表示的是循环进行三次研磨处理的情况,虚线框603表示的是循环进行四次研磨处理的情况,虚线框604表示的是循环进行六次研磨处理的情况,虚线框605表示的是循环进行十次研磨处理的情况。
由图可知,采用金属用研磨液进行研磨处理的总时间相同的情况下,通过相继进行第一研磨处理和第二研磨处理,有利于减小栅电极材料和隔离结构的总去除量的差值;增加研磨处理的循环次数,也能减小栅电极材料和隔离结构的总去除量的差值,从而在研磨去除栅电极材料的同时,能够去除凸出于层间介质层的隔离结构。
还需要说明的是,在每一次研磨处理中,所述第二研磨处理的工艺时间不宜过短,也不宜过长。如果工艺时间过短,相应会降低所述第二研磨处理对所述隔离结构400的去除效果,相应的,在完成所述研磨处理后,所述层间介质层300层顶面仍有栅电极材料550残留物的概率较高;随着第二研磨处理工艺时间的增加,晶圆表面的酸性环境逐渐减弱,所述第二研磨处理对隔离结构400的影响逐渐减小,甚至,所述第二研磨处理的工艺时间超过一定数值时,第二研磨处理不再对隔离结构400产生影响,因此,工艺时间过长反而会造成成本和时间的浪费。为此,本实施例中,在每一次研磨处理中,所述第二研磨处理的工艺时间为5秒至15秒。
具体地,为了进一步增强所述第二研磨处理对所述隔离结构400的去除效果,在每一次研磨处理中,所述第二研磨处理的工艺时间为10秒至15秒。
在所述第二研磨处理的过程中,下压力(Down Force)不宜过小,也不宜过大。如果下压力过小,则容易降低所述第二研磨处理对所述隔离结构400的去除效果;如果下压力过大,则容易对栅电极材料550造成损伤。为此,本实施例中,所述第二研磨处理的下压力为1.0psi至3.0psi。其中,psi指的是磅每平方英寸(Pounds Per Square inch)。
在所述第二研磨处理的过程中,基座转速(Platen Speed)不宜过小,也不宜过大。如果转速过小,为了保障第二研磨处理对隔离结构400的去除效果,相应会导致研磨效率的下降;如果转速过大,则容易导致第二研磨处理的处理效果均一性变差。为此,本实施例中,基座转速为30rpm至100rpm。其中,rpm指的是转数每分钟(Roung Per Minute)。
在所述第二研磨处理的过程中,去离子水的流速不宜过小,也不宜过大。如果流速过小,则容易导致晶圆表面和研磨垫之间的摩擦力增大,反而会提高隔离结构400和栅电极材料550的粗糙度;如果流速过大,则容易导致晶圆表面的残留酸性溶液被迅速稀释,无法保证所述隔离结构400有足够的时间处于所需酸性环境中,从而导致第二研磨处理对隔离结构400的去除效果变差。为此,本实施例中,去离子水的流速为100ml/min至300ml/min。
如图13所示,本实施例中,由于所述栅电极材料550还覆盖所述隔离结构400顶部和侧墙250顶部,因此,在进行所述多次研磨处理之前,还包括:对所述栅电极材料550进行预处理,去除部分厚度的所述栅电极材料550,露出所述隔离结构400顶部。
通过使剩余栅电极材料550露出所述隔离结构400的顶部,从而为后续进行研磨处理做好工艺准备,降低了后续工艺难度。
本实施例中,采用化学机械研磨的方式进行所述预处理。通过采用化学机械研磨的方式,在完成所述预处理后,即可同一设备的情况下进行后续的第一研磨处理,不仅有利于提高制造效率,还有利于降低工艺风险。
在另一些实施例中,也可以采用回刻的方式进行所述预处理,或者,采用回刻和化学机械研磨相结合的方式进行所述预处理。
需要说明的是,在其他实施例中,根据形成栅电极材料后,所述栅电极材料顶部至隔离结构顶部的距离,也可以不进行所述预处理。
相应的,继续参考图14,本发明实施例还提供一种采用前述形成方法所形成的半导体结构。
所述半导体结构包括:基底100;位于所述基底100上的栅电极层500;层间介质层400,位于所述栅电极层500露出的基底100上,所述层间介质层400覆盖所述栅电极层500侧壁且露出所述栅电极层500顶部;隔离结构400,位于相邻所述栅电极层500之间的层间介质层300内,且延伸至部分厚度的基底100内。
在所述半导体结构中,层间介质层300顶部形成有金属残留物(即栅电极层500的材料残留物)的概率较低,从而提高了半导体器件的性能。
对本实施例所述半导体结构的具体描述,可参考前述实施例中的相应描述,在此不再赘述。
虽然本发明披露如上,但本发明并非限定于此。任何本领域技术人员,在不脱离本发明的精神和范围内,均可作各种更动与修改,因此本发明的保护范围应当以权利要求所限定的范围为准。
Claims (15)
1.一种半导体结构的形成方法,其特征在于,包括:
提供基底,所述基底上形成有伪栅结构,所述伪栅结构露出的基底上形成有层间介质层,所述层间介质层覆盖所述伪栅结构侧壁且露出所述伪栅结构顶部;
在相邻所述伪栅结构之间的所述层间介质层中形成隔离结构,所述隔离结构还延伸至所述基底中;
形成所述隔离结构后,去除所述伪栅结构,在所述层间介质层内形成栅极开口;
向所述栅极开口内填充栅电极材料,所述栅电极材料还覆盖所述层间介质层顶部;
进行至少一次研磨处理,去除高于所述层间介质层顶部的栅电极材料,保留所述栅极开口内的栅电极材料作为栅电极层,所述研磨处理的步骤包括:采用金属用研磨液对所述栅电极材料进行第一研磨处理;在所述第一研磨处理后,采用去离子水对所述隔离结构进行第二研磨处理。
2.如权利要求1所述的半导体结构的形成方法,其特征在于,向所述栅极开口内填充栅电极材料之后,在进行所述研磨处理之前,还包括:对所述栅电极材料进行预处理,去除部分厚度的所述栅电极材料,露出所述隔离结构顶部。
3.如权利要求2所述的半导体结构的形成方法,其特征在于,采用化学机械研磨方式和回刻方式中的一种或两种,进行所述预处理。
4.如权利要求1所述的半导体结构的形成方法,其特征在于,所述研磨处理的次数为3次至12次。
5.如权利要求1所述的半导体结构的形成方法,其特征在于,在每一次研磨处理中,所述第二研磨处理的工艺时间为5秒至15秒。
6.如权利要求1所述的半导体结构的形成方法,其特征在于,在每一次研磨处理中,所述第二研磨处理的工艺时间为10秒至15秒。
7.如权利要求1所述的半导体结构的形成方法,其特征在于,在所述第一研磨处理的步骤中,所述金属用研磨液的PH值为2至6。
8.如权利要求1所述的半导体结构的形成方法,其特征在于,所述第二研磨处理的参数包括:下压力为1.0psi至3.0psi,基座转速为30rpm至100rpm,去离子水的流速为100ml/min至300ml/min。
9.如权利要求1所述的半导体结构的形成方法,其特征在于,所述隔离结构的材料为氮化硅、多晶硅或金属氮化物。
10.如权利要求1所述的半导体结构的形成方法,其特征在于,所述隔离结构的硬度高于所述层间介质层的硬度。
11.如权利要求1所述的半导体结构的形成方法,其特征在于,所述层间介质层的材料为氧化硅,所述隔离结构的材料为氮化硅。
12.如权利要求1所述的半导体结构的形成方法,其特征在于,形成所述隔离结构的步骤包括:依次刻蚀相邻所述伪栅结构间的层间介质层和部分厚度基底,形成位于所述层间介质层和基底内的沟槽;
向所述沟槽内填充隔离材料,所述隔离材料还覆盖所述层间介质层顶部;
采用平坦化工艺,去除高于所述层间介质层顶部的隔离材料,保留所述沟槽内的隔离材料作为所述隔离结构。
13.如权利要求12所述的半导体结构的形成方法,其特征在于,所述平坦化工艺为化学机械研磨工艺和回刻工艺中的一种或两种。
14.如权利要求1所述的半导体结构的形成方法,其特征在于,向所述栅极开口内填充栅电极材料的步骤中,所述栅电极材料为W、Al、Cu、Ag、Au、Pt、Ni或Ti。
15.一种如权利要求1至14任一项所述的形成方法所形成的半导体结构。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201811605467.3A CN111435639B (zh) | 2018-12-26 | 2018-12-26 | 半导体结构及其形成方法 |
US16/601,844 US10964797B2 (en) | 2018-12-26 | 2019-10-15 | Semiconductor structure and method for forming same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201811605467.3A CN111435639B (zh) | 2018-12-26 | 2018-12-26 | 半导体结构及其形成方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN111435639A true CN111435639A (zh) | 2020-07-21 |
CN111435639B CN111435639B (zh) | 2023-05-05 |
Family
ID=71123102
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201811605467.3A Active CN111435639B (zh) | 2018-12-26 | 2018-12-26 | 半导体结构及其形成方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US10964797B2 (zh) |
CN (1) | CN111435639B (zh) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111508897A (zh) * | 2019-01-31 | 2020-08-07 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
US11195745B2 (en) | 2019-05-20 | 2021-12-07 | International Business Machines Corporation | Forming single and double diffusion breaks for fin field-effect transistor structures |
CN111653524A (zh) * | 2020-06-11 | 2020-09-11 | 上海华力集成电路制造有限公司 | 一种鳍式场效应晶体管的制造方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102543700A (zh) * | 2010-12-23 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | 铝金属栅极的形成方法 |
US20150179432A1 (en) * | 2013-12-19 | 2015-06-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and systems for chemical mechanical polish and clean |
US20160111336A1 (en) * | 2014-10-17 | 2016-04-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and Structure for FinFET Isolation |
US20180151395A1 (en) * | 2016-11-25 | 2018-05-31 | Samsung Electronics Co., Ltd. | Cleaning composition, cleaning apparatus, and method for manufacturing semiconductor device |
US20180286699A1 (en) * | 2017-03-31 | 2018-10-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Polishing process for forming semiconductor device structure |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6943113B1 (en) * | 2000-05-11 | 2005-09-13 | Infineon Technologies Ag | Metal chemical polishing process for minimizing dishing during semiconductor wafer fabrication |
JP2008288226A (ja) * | 2007-05-15 | 2008-11-27 | Renesas Technology Corp | 半導体装置およびその製造方法 |
-
2018
- 2018-12-26 CN CN201811605467.3A patent/CN111435639B/zh active Active
-
2019
- 2019-10-15 US US16/601,844 patent/US10964797B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102543700A (zh) * | 2010-12-23 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | 铝金属栅极的形成方法 |
US20150179432A1 (en) * | 2013-12-19 | 2015-06-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and systems for chemical mechanical polish and clean |
US20160111336A1 (en) * | 2014-10-17 | 2016-04-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and Structure for FinFET Isolation |
US20180151395A1 (en) * | 2016-11-25 | 2018-05-31 | Samsung Electronics Co., Ltd. | Cleaning composition, cleaning apparatus, and method for manufacturing semiconductor device |
US20180286699A1 (en) * | 2017-03-31 | 2018-10-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Polishing process for forming semiconductor device structure |
Also Published As
Publication number | Publication date |
---|---|
US10964797B2 (en) | 2021-03-30 |
US20200211859A1 (en) | 2020-07-02 |
CN111435639B (zh) | 2023-05-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10032916B2 (en) | Formation method of semiconductor device structure with gate stack | |
US8846513B2 (en) | Semiconductor device comprising replacement gate electrode structures and self-aligned contact elements formed by a late contact fill | |
US20150076624A1 (en) | Integrated circuits having smooth metal gates and methods for fabricating same | |
US20150295063A1 (en) | Mechanism for forming metal gate structure | |
CN106816470B (zh) | 具有栅极堆叠件的半导体器件结构的结构和形成方法 | |
CN111435639B (zh) | 半导体结构及其形成方法 | |
US20230377898A1 (en) | Methods for reducing scratch defects in chemical mechanical planarization | |
US11069559B1 (en) | Semiconductor structure and method of forming same | |
TW201725612A (zh) | 半導體元件及其形成方法 | |
CN111489972B (zh) | 半导体结构及其形成方法 | |
US20190013204A1 (en) | Method of fabricating buried word line and gate on finfet | |
CN112151380B (zh) | 半导体结构及其形成方法 | |
CN109637927B (zh) | 金属栅的制造方法 | |
CN114446788A (zh) | 半导体结构的形成方法 | |
CN111863723A (zh) | 半导体结构及其形成方法 | |
CN111554636B (zh) | 半导体结构及其形成方法 | |
CN114068394B (zh) | 半导体结构的形成方法 | |
CN113871345B (zh) | 半导体结构的形成方法 | |
CN118116869A (zh) | 半导体结构的形成方法 | |
JP2010027690A (ja) | 半導体装置の製造方法 | |
CN107845576B (zh) | 半导体结构的形成方法 | |
CN117476464A (zh) | 半导体结构的形成方法 | |
KR100945867B1 (ko) | 반도체 소자의 다층 배선 형성 방법 | |
CN115020236A (zh) | 后栅工艺中多晶硅伪栅去除方法 | |
CN114724946A (zh) | 平坦化方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |