CN111430918B - Phased array antenna control system - Google Patents
Phased array antenna control system Download PDFInfo
- Publication number
- CN111430918B CN111430918B CN202010352030.4A CN202010352030A CN111430918B CN 111430918 B CN111430918 B CN 111430918B CN 202010352030 A CN202010352030 A CN 202010352030A CN 111430918 B CN111430918 B CN 111430918B
- Authority
- CN
- China
- Prior art keywords
- antenna
- data
- chip
- pin
- electrically connected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q3/00—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system
- H01Q3/26—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture
- H01Q3/30—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture varying the relative phase between the radiating elements of an array
- H01Q3/34—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture varying the relative phase between the radiating elements of an array by electrical means
Landscapes
- Variable-Direction Aerials And Aerial Arrays (AREA)
Abstract
The embodiment of the disclosure provides a phased array antenna system, and belongs to the technical field of antennas. The phased array antenna system includes: the field programmable gate array chip comprises a plurality of data pins and a plurality of chip select pins; the antenna module comprises a plurality of antenna modules, the antenna modules are arranged in an array mode, each antenna module comprises a latch and an antenna unit, one site of one data pin and one site of one chip selection pin are electrically connected with the latches, so that the latches are connected with the field programmable gate array chip in parallel, and one end of each antenna is electrically connected with one latch. Through the processing scheme disclosed by the invention, the plurality of antenna modules are connected with the field programmable gate array chip in parallel, so that the use of pins is reduced, data can be input and latched in real time when the antenna is used, then the latch drives the antenna to form a beam, and the control efficiency and stability of the phased array antenna system are improved.
Description
Technical Field
The present disclosure relates to the field of antenna technology, and more particularly, to a phased array antenna control system.
Background
At present, with the development of society, the progress of information era is accelerated continuously, communication becomes more and more convenient, and in a communication mode, a phased array technology is widely applied due to high efficiency, but in the existing phased array antenna control system, because of the numerous phased array antenna array units, the unit modules of each antenna move hundreds and even thousands, which is undoubtedly huge pressure for a control chip, and one pin of the control chip corresponds to one control according to the traditional phased array antenna control system, and obviously, the requirement of driving cannot be met.
It can be seen that a need exists for a phased array antenna system that has high control efficiency and stability.
Disclosure of Invention
In view of this, the embodiments of the present disclosure provide a phased array antenna system, which aims to improve the problem of poor control efficiency and stability of the existing phased array antenna system.
In a first aspect, an embodiment of the present disclosure provides a phased array antenna system, including:
the field programmable gate array chip comprises a plurality of data pins and a plurality of chip selection pins, and a plurality of sites are arranged on each data pin and each chip selection pin;
the antenna comprises a plurality of antenna modules, wherein the antenna modules are arranged in an array mode, each antenna module comprises a latch and an antenna unit, one site of a data pin and one site of a chip selection pin are electrically connected with the latches so that the latches are connected with the field programmable gate array chip in parallel, one end of each antenna is electrically connected with one latch, the data pin is used for inputting data to the latches, and the chip selection pin is used for adjusting the level.
According to a specific implementation manner of the embodiment of the present disclosure, at least two of the antenna modules are arranged horizontally to form a group of antenna modules, and the plurality of groups of antenna modules are arranged in parallel in the longitudinal direction, so that all the antenna modules form an array arrangement.
According to a specific implementation manner of the embodiment of the present disclosure, the latch includes a data input terminal, a level terminal and a data output terminal;
the antenna unit includes a diode;
the data input end is electrically connected with the data pin, the level end is electrically connected with the chip selection pin, the data output end is electrically connected with the anode of one diode, and the cathode of the diode is grounded.
According to a specific implementation manner of the embodiment of the present disclosure, the phased array antenna control system further includes a power supply component, and the power supply component is electrically connected to a power supply pin of the field programmable gate array chip.
According to a specific implementation manner of the embodiment of the present disclosure, a shared comparator is further disposed inside the field programmable gate array chip, and a chip selection terminal of the field programmable gate array chip is electrically connected to all the chip selection pins through the shared comparator.
According to a specific implementation manner of the embodiment of the present disclosure, the antenna unit further includes a real time delay unit, one end of the real time delay unit is electrically connected to the data output end, and the other end of the real time delay unit is electrically connected to the positive electrode of the diode.
The phased array antenna system in an embodiment of the present disclosure includes: the field programmable gate array chip comprises a plurality of data pins and a plurality of chip selection pins, and a plurality of sites are arranged on each data pin and each chip selection pin; the antenna comprises a plurality of antenna modules, wherein the antenna modules are arranged in an array mode, each antenna module comprises a latch and an antenna unit, one site of a data pin and one site of a chip selection pin are electrically connected with the latches so that the latches are connected with the field programmable gate array chip in parallel, one end of each antenna is electrically connected with one latch, the data pin is used for inputting data to the latches, and the chip selection pin is used for adjusting the level. According to the scheme, each latch is correspondingly connected with one site on one data pin and one site on one chip selection pin, so that the latches are connected with the field programmable gate array chip in parallel, the use of the pins is reduced, data can be input and latched in real time when the latches are used, and the control efficiency and the stability of the phased array antenna system are improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a phased array antenna system according to an embodiment of the present disclosure.
Summary of reference numerals:
a phased array antenna system 100;
a field programmable gate array chip 110, a data pin 111, a chip select pin 112;
the antenna module 120, the latch 121, the antenna unit 122, the data input terminal 123, the level terminal 124, and the data output terminal 125.
Detailed Description
The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.
The embodiments of the present disclosure are described below with specific examples, and other advantages and effects of the present disclosure will be readily apparent to those skilled in the art from the disclosure in the specification. It is to be understood that the described embodiments are merely illustrative of some, and not restrictive, of the embodiments of the disclosure. The disclosure may be embodied or carried out in various other specific embodiments, and various modifications and changes may be made in the details within the description without departing from the spirit of the disclosure. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.
It is noted that various aspects of the embodiments are described below within the scope of the appended claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the disclosure, one skilled in the art should appreciate that one aspect described herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number of the aspects set forth herein. Additionally, such an apparatus may be implemented and/or such a method may be practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present disclosure, and the drawings only show the components related to the present disclosure rather than the number, shape and size of the components in actual implementation, and the type, amount and ratio of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details.
Referring to fig. 1, a phased array antenna system is provided in an embodiment of the present disclosure. As shown in fig. 1, the phased array antenna system 100 mainly includes:
the Field Programmable Gate Array (FPGA) chip 110 includes a plurality of DATA pins 111(DATA) and a plurality of chip SELECT pins 112(ROW SELECT), and each of the DATA pins 111 and each of the chip SELECT pins 112 has a plurality of sites;
the antenna module 120 comprises a LATCH 121(LATCH) and an antenna unit 122, wherein a position of a data pin 111 and a position of a chip select pin 112 are electrically connected to one LATCH 121, so that the LATCH 121 is connected to the fpga chip 110 in parallel, one end of each antenna unit 122 is electrically connected to one LATCH 121, the data pin 111 is used for inputting data to the LATCH 121, and the chip select pin 112 is used for adjusting the level.
Considering that when a phased array antenna is used for communication, the number of phased array antenna units is large, and the number of unit modules of each antenna is hundreds, even thousands, which is undoubtedly a huge pressure on a control chip, and it is obviously impossible to meet the driving requirement according to the control chip of the conventional phased array antenna control system that one pin corresponds to one control.
During specific assembly, a plurality of antenna modules 120 are arranged in an array, each of which is electrically connected to one site of one data pin 111 and one site of one chip select pin 112, so that the latch 121 is connected in parallel with the field programmable gate array chip 110, and one end of each antenna unit 122 is electrically connected to one latch 121.
When 900 antenna modules 120 need to be driven, 900 antenna modules 120 may be arranged in an array of 30 by 30, each data pin 111 has 30 sites, and each chip select pin 112 has 30 sites, then each latch 121 in the antenna module 120 is electrically connected to one site on one data pin 111 and one site on one chip select pin 112, so that each data pin 111 is electrically connected to 30 latches 121, each chip select pin 112 is electrically connected to 30 latches 121, so that the latch 121 is connected in parallel to the fpga chip 110, data is input through the data pin 111, and the first chip select pin 112 is selected to be at a high level, so that the output data reaches the latch 121 corresponding to the first chip select pin 112, the chip select pin 112 of the first row is then switched low so that data is latched in the latch 121 corresponding to the first one of the chip select pins 112. Of course, the same procedure may be adopted to latch different data in the second and subsequent latches 121 corresponding to the chip select pins 112, and then each latch 121 drives the antenna unit 122 to form a beam according to the latched data.
The phased array antenna system provided by the embodiment of the disclosure, be provided with a plurality of data pins and a plurality of chip selection pin on the field programmable gate array chip, all be provided with a plurality of sites on every data pin and the chip selection pin, a site on every data pin and a site on the chip selection pin all correspond an antenna module, so that a plurality of antenna modules and field programmable gate array chip are parallelly connected, the use of pin has been reduced, and can input data and latch data in real time when using, by the wave beam of circuit control phased array antenna, dynamic response is very fast, the control efficiency and the stability of phased array antenna system have been improved.
On the basis of the above embodiment, at least two antenna modules 120 of all the antenna modules 120 are arranged horizontally to form a group of the antenna modules 120, and multiple groups of the antenna modules 120 are arranged in parallel longitudinally, so that all the antenna modules 120 form an array arrangement.
In specific implementation, if all the antenna modules 120 have 900 antenna modules, 30 antenna modules 120 may be set as a group, which is divided into 30 groups, the antenna modules 120 in a group are arranged horizontally, and the 30 antenna modules 120 are arranged in parallel, so that the antenna modules 120 in each group are arranged longitudinally, and thus all the antenna modules 120 form an array arrangement, which is convenient for the data pins 111 and the chip select pins 112 to connect.
Further, the latch 121 includes a data input terminal 123(Q), a level terminal 124(EN), and a data output terminal 125 (D);
the antenna element 122 includes a diode;
the data input terminal 123 is electrically connected to the data pin 111, the level terminal 124 is electrically connected to the chip select pin 112, the data output terminal 125 is electrically connected to the positive electrode of one of the diodes, and the negative electrode of the diode is grounded.
When the data latch is used, data is input to the data input end 123 through the data pin 111, when the chip select pin 112 connected to the level end 124 is at a high level, the data is output to the data output end 125, then the chip select pin 112 is switched to a low level, so that the data is latched in the data output end 125, assignment is completed, then the data output end 125 drives the diodes to form a beam according to the data, the data is not changed after latching, stability is improved, and the diodes are directly driven by the latch 121, so that the use of a driving circuit is reduced.
Further, the phased array antenna control system further includes a power supply component electrically connected to the power supply pin of the field programmable gate array chip 110.
Optionally, a shared comparator is further disposed inside the field programmable gate array chip 110, and a chip selection end of the field programmable gate array chip 110 is electrically connected to all the chip selection pins 112 through the shared comparator.
When the power supply module is used, the power supply module is electrically connected with a power supply pin of the field programmable gate array chip 110 to supply power for the working process of the field programmable gate array chip 110 and for the latch 121 to drive the diode, the shared comparator is arranged between a chip selection end of the programmable gate array chip and all the chip selection pins 112, when data needs to be input to the latch 121 corresponding to the first chip selection pin 112, the shared comparator selects the first chip selection pin 112 as a high level, and when data needs to be latched to the latch 121 corresponding to the first chip selection pin 112, the shared comparator selects the first chip selection pin 112 as a low level.
Optionally, the antenna unit 122 further includes a real time delay unit, one end of the real time delay unit is electrically connected to the data output end, and the other end of the real time delay unit is electrically connected to the positive electrode of the diode.
In specific implementation, considering that the beam direction has a large deviation along with the frequency change, the real time delay unit may be provided, one end of the real time delay unit is electrically connected to the data output end, and the other end of the real time delay unit is electrically connected to the positive electrode of the diode, so that the beam direction formed by the diode changes less along with the frequency change.
In summary, in the phased array antenna system according to the embodiment of the disclosure, the field programmable gate array chip and the antenna modules are arranged, and the plurality of antenna modules are connected in parallel with the field programmable gate array chip, so that the use of pins is reduced, data can be input and latched in real time when the phased array antenna system is used, and then the latches drive the antennas to form beams, thereby improving the control efficiency and stability of the phased array antenna system.
The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present disclosure should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (5)
1. A phased array antenna control system, comprising:
the field programmable gate array chip comprises a plurality of data pins and a plurality of chip selection pins, and a plurality of sites are arranged on each data pin and each chip selection pin;
the antenna modules are arranged in an array mode, each antenna module comprises a latch and an antenna unit, one site of a data pin and one site of a chip selection pin are electrically connected with the latch so that the latch is connected with the field programmable gate array chip in parallel, one end of each antenna is electrically connected with the latch, the data pin is used for inputting data to the latch, and the chip selection pin is used for adjusting the level;
the latch comprises a data input end, a level end and a data output end;
the antenna unit includes a diode;
the data input end is electrically connected with one site of the data pin, the level end is electrically connected with one site of the chip selection pin, the data output end is electrically connected with the anode of one diode, and the cathode of the diode is grounded.
2. The system of claim 1, wherein at least two of the antenna modules are arranged laterally to form a group of the antenna modules, and the plurality of groups of the antenna modules are arranged longitudinally in parallel to each other, such that all of the antenna modules form an array arrangement.
3. The system of claim 2, wherein the phased array antenna control system further comprises a power supply component electrically connected to a power pin of the field programmable gate array chip.
4. The system according to claim 3, wherein a shared comparator is further arranged inside the field programmable gate array chip, and a chip selection terminal of the field programmable gate array chip is electrically connected with all the chip selection pins through the shared comparator.
5. The system of claim 4, wherein the antenna unit further comprises a real time delay, one end of the real time delay is electrically connected to the data output terminal, and the other end of the real time delay is electrically connected to the positive electrode of the diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010352030.4A CN111430918B (en) | 2020-04-28 | 2020-04-28 | Phased array antenna control system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010352030.4A CN111430918B (en) | 2020-04-28 | 2020-04-28 | Phased array antenna control system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111430918A CN111430918A (en) | 2020-07-17 |
| CN111430918B true CN111430918B (en) | 2021-07-09 |
Family
ID=71554710
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010352030.4A Active CN111430918B (en) | 2020-04-28 | 2020-04-28 | Phased array antenna control system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111430918B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102495565A (en) * | 2011-11-25 | 2012-06-13 | 中国电子科技集团公司第三十八研究所 | Phased array radar antenna beam control device |
| CN106342231B (en) * | 2009-06-16 | 2014-01-01 | 中国航空工业集团公司雷华电子技术研究所 | Passive phased-array radar stimulating module |
| US9450620B1 (en) * | 2015-06-25 | 2016-09-20 | Nitero Pty Ltd. | Fast indirect antenna control |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104617390B (en) * | 2015-02-11 | 2017-03-29 | 中国电子科技集团公司第三十八研究所 | A kind of spaceborne massive phased array antenna beam control device |
| KR20170136546A (en) * | 2015-04-13 | 2017-12-11 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Decoders, receivers, and electronics |
-
2020
- 2020-04-28 CN CN202010352030.4A patent/CN111430918B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106342231B (en) * | 2009-06-16 | 2014-01-01 | 中国航空工业集团公司雷华电子技术研究所 | Passive phased-array radar stimulating module |
| CN102495565A (en) * | 2011-11-25 | 2012-06-13 | 中国电子科技集团公司第三十八研究所 | Phased array radar antenna beam control device |
| US9450620B1 (en) * | 2015-06-25 | 2016-09-20 | Nitero Pty Ltd. | Fast indirect antenna control |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111430918A (en) | 2020-07-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN113131225B (en) | Irregular antenna array optimization method based on subarray factor gain maximization | |
| CN104932134A (en) | Touch control display substrate | |
| CN105634627A (en) | Antenna array coupling calibration network device and method | |
| CN111430918B (en) | Phased array antenna control system | |
| CN103975285B (en) | Implementing an inter-processor communication in a multi-core system using mmwave radios | |
| CN103293456B (en) | Aging testing apparatus | |
| CN109301500B (en) | Design method of Chebyshev microstrip array antenna | |
| CN114204271B (en) | Broadband low-RCS array antenna design method based on interdigital arrangement super-surface | |
| CN114400042B (en) | Memory test system | |
| Choo et al. | Design of electrically small wire antennas using genetic algorithm taking into consideration of bandwidth and efficiency | |
| CN113471716B (en) | Holographic antenna, control method, computer device, and storage medium | |
| US8190382B2 (en) | Tool to analyze performance of power-beam photovoltaic receiver | |
| CN111489709A (en) | Backlight source driving circuit, backlight module and liquid crystal display device | |
| CN110806507A (en) | In-situ automatic test method for bundled radio frequency cable and LRM modular interface | |
| CN104318896A (en) | Display screen scanning method and display screen | |
| Chen et al. | Performance of a massively parallel method of moment solver and its application | |
| CN116306459B (en) | Pin arrangement method, system, medium and equipment of quantum chip layout | |
| CN111353248B (en) | Electromagnetic simulation optimization method and system | |
| CN203759063U (en) | Probe test fixture | |
| CN116720287B (en) | Antenna unit directional diagram numerical value synthesis method and system based on multiple feeds | |
| CN112965181B (en) | Large-scale integrated photonic device array control circuit and method | |
| CN110943756B (en) | Parallel SPI bus-based line matrix type wave control system data transmission method | |
| CN114791552A (en) | HTOL test board and clock circuit thereof | |
| CN117706497A (en) | Automatic identification method for subarray positions in phased array radar antenna area array | |
| Steer et al. | Architectures and prototyping laboratory for the development of space-based microwave power transmission systems |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |