CN111430464A - Split gate MOSFET device with reduced switching losses and method of making same - Google Patents
Split gate MOSFET device with reduced switching losses and method of making same Download PDFInfo
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
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Abstract
The invention relates to a split gate MOSFET device capable of reducing switching loss and a manufacturing method thereof. The invention reduces the switching loss, solves the problem of overlarge IGSS electric leakage, can improve the voltage endurance capability at the corner of the bottom of the groove and can accurately adjust the sizes of the input capacitor Ciss and the output capacitor Coss. The manufacturing process of the invention is compatible with the widely used semiconductor manufacturing technology, and is beneficial to popularization and batch production.
Description
Technical Field
The invention relates to the technical field of power semiconductor devices, in particular to a split gate MOSFET device structure and a manufacturing method thereof.
Background
Currently, power MOSFETs are mainly studied for the purpose of reducing power consumption, and semiconductor device power consumption includes conduction loss and switching loss. A Metal-Oxide-Semiconductor Field effect transistor (MOSFET) is a Field effect transistor that can be widely used, and the characteristics of the device are continuously close to the one-dimensional limit of silicon material (which expresses the theoretical relationship between the characteristic on-resistance of the drift region of the device and the breakdown voltage when the device is turned off).
With the continuous improvement and innovation of devices, a Split-gate type trench device structure (MOSFET) is proposed in the field, and within a medium-low voltage range, the structure can break the one-dimensional limit of a silicon material and has lower on-resistance, so that lower on-loss can be realized, and the device characteristics are greatly improved. At present, a common split gate MOSFET structure is shown in fig. 1, and the process manufacturing method is as follows: firstly, manufacturing and finishing separation Gate polysilicon (Source poly), growing an oxide layer through thermal oxidation, obtaining a Gate oxide layer (Gate oxide), an isolation oxide layer between the separation Gate polysilicon (Source poly) and the control Gate polysilicon (Gate poly) through an etching process, and manufacturing the control Gate polysilicon (Gate poly) and the control Gate polysilicon (Gate poly), wherein the manufacturing method of the process is embodied in the prior art;
however, the current split gate MOSFET device still has many disadvantages:
1. the overlapping area of the gate and the source in the trench is large, namely Cgs is large, and according to the input capacitance Ciss formula: cis is Cgs + Cgd, and Cgs is large, so that the input capacitance cis is large, the switching loss is high, and the switching loss is particularly remarkable under a high-frequency working condition;
2. in the existing manufacturing method, the isolation oxide layer between the gate and the source in the trench is very thin and slightly larger than the thickness of the gate oxide layer, so that the coupling capacitance between the gate and the source is relatively large, the input capacitance Ciss is relatively large, the switching loss is high, and meanwhile, the process of the very thin isolation oxide layer is not easy to control, and the problem of overlarge IGSS electric leakage is easily caused, so that the performance of a device is seriously influenced;
3. due to the special device structure, the oxide layer at the bottom of the groove is also very thin and is slightly larger than the thickness of the gate oxide layer, meanwhile, the oxide layer in the groove of the existing split gate MOSFET device is formed through thermal oxidation growth or deposition growth, the compactness of the device is poor, and the device and the corner at the bottom of the groove are easy to break down under high pressure, so that the performance of the device is seriously influenced.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide a split gate MOSFET device structure and a manufacturing method thereof, wherein the split gate MOSFET device structure can reduce the switching loss and improve the voltage endurance capability of the device.
According to the technical scheme provided by the invention, the split gate MOSFET device for reducing the switching loss comprises a cellular area and a terminal protection area, wherein the cellular area is positioned in the central area of the device, and the terminal protection area surrounds the cellular area; the cell area comprises a semiconductor substrate, the semiconductor substrate comprises a first conductive type substrate and a first conductive type epitaxial layer which is positioned on the first conductive type substrate and is adjacent to the first conductive type substrate, the upper surface of the first conductive type epitaxial layer is a first main surface of the semiconductor substrate, and the lower surface of the first conductive type substrate is a second main surface of the semiconductor substrate;
a plurality of grooves which are uniformly distributed are arranged in the first conduction type epitaxial layer, the grooves extend along the direction of the first conduction type epitaxial layer from the first main surface to the second main surface, an upper part and a lower part are arranged in the grooves, the upper part comprises control gate polycrystalline silicon and gate oxide layers positioned on two sides of the control gate polycrystalline silicon, and the lower part comprises separation gate polycrystalline silicon and a medium isolation cavity for containing the separation gate polycrystalline silicon; the volume of the separation gate polysilicon is smaller than that of the control gate polysilicon, and the thickness of a dielectric isolation cavity between the separation gate polysilicon and the control gate polysilicon is larger than that of the gate oxide layer.
Preferably, a second conductivity type body region is provided between adjacent trenches, the second conductivity type body region is provided in the first conductivity type epitaxial layer, and a first conductivity type source region is provided in the second conductivity type body region, the first conductivity type source region being provided on both sides of the second conductivity type body region.
Preferably, a drain metal is provided on the second main surface of the semiconductor substrate; an insulating medium layer is arranged on the first main surface of the semiconductor substrate, grid metal and source metal are arranged on the insulating medium layer at intervals, the source metal penetrates through the insulating medium layer to be in ohmic contact with the second conduction type body region and the first conduction type source region, and the grid metal penetrates through the insulating medium layer to be in ohmic contact with the control grid polysilicon in the groove.
Preferably, the medium isolation cavity is of a single-layer structure and is of single-layer SiO2A layer or single layer of SiN; or the medium isolation cavity is of a multilayer structure and is made of SiO2A structure in which layers and SiN layers are alternately distributed.
A method of fabricating a split-gate MOSFET device with reduced switching losses, comprising the steps of:
selecting a first conductive type substrate, and growing a first conductive type epitaxial layer on the first conductive type substrate, wherein the upper surface of the first conductive type epitaxial layer is a first main surface, and the lower surface of the first conductive type substrate is a second main surface;
under the masking of the hard mask layer window, carrying out anisotropic dry etching on the first main surface, forming a plurality of uniformly distributed grooves in the first conduction type epitaxial layer, and removing the hard mask layer window;
adopting an ICPECVD technology, exciting a plasma process by using an inductive coupling mode, and growing a thick silicon dioxide layer on the first main surface and in the groove;
depositing conductive polysilicon on the thick silicon dioxide layer, wherein the groove is filled with the conductive polysilicon;
etching the conductive polysilicon and the thick silicon dioxide layer to obtain small-volume separation gate polysilicon below the trench;
adopting an ICPECVD technology, exciting a plasma process by using an inductive coupling mode, and continuously growing a very thick silicon dioxide layer on the separation gate polysilicon in the groove;
removing the silicon dioxide layer on the first main surface and part of the silicon dioxide layer on the side wall of the groove by dry and wet etching to obtain a gate oxide layer positioned on the side wall of the upper part of the groove and a medium isolation cavity positioned at the lower part of the groove and formed by the thick silicon dioxide layer;
depositing conductive polysilicon on the first main surface and in the groove continuously, and etching to remove the conductive polysilicon on the first main surface to obtain control gate polysilicon covering the upper part of the groove, wherein the control gate polysilicon is positioned on the upper part of the medium isolation cavity, and the volume of the control gate polysilicon is larger than that of the separation gate polysilicon;
injecting second conductive type impurity ions into the self-aligned ions on the first main surface, and forming a second conductive type body region through high-temperature junction pushing;
step ten, selectively injecting high-concentration first conductive type impurity ions on the first main surface through the shielding of a photoetching mask, and forming a first conductive type source region through high-temperature junction pushing;
step eleven, depositing an insulating medium layer on the first main surface, and etching the insulating medium layer to obtain a metal contact hole;
step twelve, depositing metal on the insulating medium layer and in the metal contact hole, and etching the metal to obtain source metal in ohmic contact with the second conductive type body region and the first conductive type source region respectively, and simultaneously obtain gate metal in ohmic contact with the control gate polysilicon;
and step thirteen, thinning the second main surface, and depositing metal on the second main surface to obtain drain metal, wherein the drain metal is in ohmic contact with the first conductive type substrate.
Preferably, the thick silicon dioxide layer of the medium isolation cavity is prepared by adopting an ICPECVD (inductively coupled plasma enhanced chemical vapor deposition) technology, exciting a plasma process by using an inductive coupling mode, wherein the temperature of a reaction furnace is 100-200 ℃, the reaction time is 200-300 min, the pressure of the reaction chamber is 6Pa, the radio-frequency power is 400W, silane and oxygen are used as reaction gases, the silane is a mixed gas of silane and argon containing 5% of argon by volume fraction, the flow rates of the reaction gases of the silane and the oxygen are respectively 130.5ml/min and 13ml/min, and the flow rate of the diluent gas of the argon is 126 ml/min.
A method of fabricating a split-gate MOSFET device with reduced switching losses, comprising the steps of:
selecting a first conductive type substrate, and growing a first conductive type epitaxial layer on the first conductive type substrate, wherein the upper surface of the first conductive type epitaxial layer is a first main surface, and the lower surface of the first conductive type substrate is a second main surface;
under the masking of the hard mask layer window, carrying out anisotropic dry etching on the first main surface, forming a plurality of uniformly distributed grooves in the first conduction type epitaxial layer, and removing the hard mask layer window;
adopting an ICPECVD technology, exciting a plasma process in an inductive coupling mode, growing a first silicon dioxide layer on the first main surface and in the groove, then exciting the plasma process on the first silicon dioxide layer in the inductive coupling mode, continuously growing a first silicon nitride layer, and continuously growing a second silicon dioxide layer on the first silicon nitride layer;
continuously depositing conductive polysilicon on the second silicon dioxide layer, wherein the groove is filled with the conductive polysilicon;
etching the conductive polycrystalline silicon to obtain small-volume separation gate polycrystalline silicon below the groove;
adopting an ICPECVD technology, exciting a plasma process by using an inductive coupling mode, and continuously growing a third silicon dioxide layer on the small-volume separation gate polysilicon in the groove;
etching the third silicon dioxide layer on the upper part of the groove;
step eight, continuing to grow a second silicon nitride layer in the groove;
step nine, etching the second silicon nitride layer on the upper part of the groove;
step ten, continuing to grow a fourth silicon dioxide layer on the second silicon nitride layer in the groove;
removing the silicon dioxide layer on the first main surface and part of the silicon dioxide layer on the side wall of the groove by dry and wet etching to obtain a gate oxide layer positioned on the side wall of the upper part of the groove and a dielectric isolation cavity positioned at the lower part of the groove and formed by alternately arranging the silicon dioxide layer and the silicon nitride layer;
step twelve, continuously depositing conductive polysilicon on the first main surface and in the groove, and etching to remove the conductive polysilicon on the first main surface to obtain control gate polysilicon covering the upper part of the groove, wherein the control gate polysilicon is positioned on the upper part of the medium isolation cavity;
step thirteen, implanting second conductive type impurity ions into the self-aligned ions on the first main surface, and forming a second conductive type body region through high-temperature junction pushing;
step fourteen, selectively injecting high-concentration first conductive type impurity ions on the first main surface through the shielding of a photoetching mask, and forming a first conductive type source region through high-temperature junction pushing;
a fifteenth step of depositing an insulating medium layer on the first main surface, and etching the insulating medium layer to obtain a metal contact hole;
depositing metal on the insulating medium layer and in the metal contact hole, and etching the metal to obtain source metal in ohmic contact with the second conductive type body region and the first conductive type source region respectively, and simultaneously obtain gate metal in ohmic contact with the control gate polysilicon;
seventhly, thinning the second main surface, and depositing metal on the second main surface to obtain drain metal, wherein the drain metal is in ohmic contact with the first conductive type substrate.
Preferably, the silicon dioxide layer of the medium isolation cavity is prepared by adopting an ICPECVD (plasma enhanced chemical vapor deposition) technology, exciting a plasma process by using an inductive coupling mode, controlling the temperature of a reaction furnace to be 100-200 ℃, the pressure of the reaction chamber to be 6Pa, the radio-frequency power to be 400W, and adopting silane and oxygen as reaction gases, wherein the silane is a mixed gas of silane containing 5% of argon by volume and argon, the flow rates of the silane and the oxygen as the reaction gases are respectively 130.5ml/min and 13ml/min, and the flow rate of argon as a diluent gas is 126 ml/min;
the silicon nitride layer of the medium isolation cavity is prepared under the conditions that the temperature of a reaction furnace is 150-300 ℃, the pressure of the reaction chamber is 1-5 Pa, silane and nitrogen are used as reaction gases, wherein the silane is a mixed gas of silane containing 15% by volume of ammonia and ammonia, and SiH4And N2The gas flow rate ratio is 30: 15-38: 30, and the radio frequency power density is 0.05-0.25W/cm2。
Preferably, the thickness of the dielectric isolation cavity between the separation gate polysilicon and the control gate polysilicon is 4000-5000A, the thickness of the dielectric isolation cavity corresponding to the two sides of the separation gate polysilicon is 6000-7000A, and the thickness of the cavity wall of the dielectric isolation cavity corresponding to the bottom of the trench is 6000-7000A; the thickness of the gate oxide layer is 600-1200A.
Preferably, for an N-type MOSFET device structure, the first conductivity type is N-type conductivity and the second conductivity type is P-type conductivity; for a P-type MOSFET device structure, the first conductivity type is P-type conductivity and the second conductivity type is N-type conductivity.
The invention has the following advantages:
1) according to the invention, the relative overlapping area of the control gate polysilicon and the separation gate polysilicon is reduced by reducing the volume of the separation gate polysilicon (Source polysilicon), the distance between the control gate polysilicon and the separation gate polysilicon is increased (namely the thickness of the cavity of the dielectric isolation cavity is thicker), the capacitance Cgs between the drain electrode and the Source electrode can be reduced, and further the input capacitance Ciss is reduced, wherein the input capacitance Ciss is Cgs + Cgd, and the switching loss is reduced;
2) according to the invention, by reducing the volume of the polysilicon (Source poly), the relative overlapping area of the drain and the Source can be reduced, and the distance between the drain and the Source is increased (namely the thickness of the cavity of the dielectric isolation cavity at the bottom of the trench is thicker), so that the capacitance CdS between the drain and the Source can be reduced, the output capacitance Coss is Cds + Cgd, and the switching loss is reduced;
3) the dielectric isolation cavity in the manufacturing process is obtained by adopting an ICPECVD technology and exciting a plasma in an inductive coupling mode, the oxide layer and the silicon nitride layer obtained by the ICPECVD technology have higher plasma density, the purity is higher, the compactness is better, the dielectric coefficient of the dielectric isolation cavity as a capacitance medium is smaller, the capacitance Cgs between a grid electrode and a source electrode and the capacitance Cds between a source electrode and a drain electrode can be effectively reduced, the input capacitance Ciss and the output capacitance Coss are further reduced, the total charge Qg of the grid electrode is further reduced, the switching loss is reduced, meanwhile, the thickness of the cavity wall of the dielectric isolation cavity between the polycrystalline silicon of the control grid and the polycrystalline silicon of the separation grid is very thick and is far larger than that of the grid oxide layer, the polycrystalline silicon of the control grid and the polycrystalline silicon of the separation grid can be effectively isolated, the coupling capacitance between the grid electrode and the source electrode is reduced;
4) the dielectric isolation cavity can be an isolation cavity formed by alternately arranging a silicon dioxide layer and a silicon nitride layer, silicon nitride is used as a capacitance medium, although the dielectric coefficient of the silicon nitride is slightly larger than that of silicon dioxide, the dielectric coefficient of the silicon nitride and the silicon dioxide are alternately distributed, so that the dielectric coefficient of the silicon nitride and the silicon dioxide used as the capacitance medium is far smaller than that of single-layer silicon dioxide, the isolation effect of the silicon nitride and the silicon dioxide used as the capacitance medium is better, the input capacitance Ciss and the output capacitance Coss can be further reduced, the total charge Qg of a grid electrode is further reduced, and the switching loss is; the sizes of the input capacitor Ciss and the output capacitor Coss can be accurately adjusted by adjusting the number and the thickness of the silicon dioxide layer and the silicon nitride layer in the dielectric isolation cavity;
5) the cavity wall of the medium isolation cavity at the bottom of the groove is thick, the compactness is good, and the breakdown resistance at the corner of the bottom of the groove can be improved;
6) the manufacturing process of the invention is compatible with the semiconductor manufacturing technology which is widely used at present, and is beneficial to popularization and batch production.
Drawings
Fig. 1 is a structural view of a general split gate MOSFET.
Fig. 2 is a structural diagram after being processed in step one in embodiment 1 of the present invention.
FIG. 3 is a structural diagram after the treatment of step two in example 1 of the present invention.
Fig. 4 is a structural diagram after the third step of the process in embodiment 1 of the present invention.
FIG. 5 is a structural diagram after the treatment of step four in example 1 of the present invention.
Fig. 6 is a structural diagram after the process of step five in embodiment 1 of the present invention.
Fig. 7 is a structural diagram after the sixth process in example 1 of the present invention.
Fig. 8 is a structural diagram after the processing of step seven in embodiment 1 of the present invention.
Fig. 9 is a structural diagram after the processing of step eight in embodiment 1 of the present invention.
Fig. 10 is a structural diagram after processing in step nine and step ten in embodiment 1 of the present invention.
Fig. 11 is a structural diagram after processing in steps eleven to thirteen in embodiment 1 of the present invention.
Fig. 12 is a structural diagram after being subjected to the step one process in embodiment 2 of the present invention.
Fig. 13 is a structural diagram after being processed in step two in embodiment 2 of the present invention.
Fig. 14 is a structural diagram after the processing of step three in embodiment 2 of the present invention.
Fig. 15 is a structural diagram after the processing of step four in embodiment 2 of the present invention.
Fig. 16 is a structural diagram after the processing of step five in embodiment 2 of the present invention.
Fig. 17 is a structural diagram after the sixth process in embodiment 2 of the present invention.
Fig. 18 is a structural diagram after the processing of step seven in embodiment 2 of the present invention.
Fig. 19 is a structural diagram after the processing of step eight in embodiment 2 of the present invention.
Fig. 20 is a structural diagram after the processing in step nine in embodiment 2 of the present invention.
Fig. 21 is a structural diagram after the processing in step ten in embodiment 2 of the present invention.
Fig. 22 is a structural diagram after being subjected to the process of step eleven in embodiment 2 of the present invention.
Fig. 23 is a structural diagram after the process of step twelve in embodiment 2 of the present invention.
Fig. 24 is a structural diagram after being subjected to the processing of step thirteen and step fourteen in embodiment 2 of the present invention.
Fig. 25 is a structural diagram after processing in steps fifteen to seventeen in embodiment 2 of the present invention.
Fig. 26 is a graph of Qg and Vgs of example 1 and example 2 of the present invention and a conventional split-gate device.
Detailed Description
The present invention will be further described with reference to the following specific examples.
In the following embodiments, a split-gate MOSFET device and a method for manufacturing the same are provided, in which, taking an N-type as an example, the first conductivity type is an N-type, and the second conductivity type is a P-type;
example 1
A split gate MOSFET device with reduced switching loss comprises a cell region and a terminal protection region, wherein the cell region is positioned in the central region of the device, and the terminal protection region surrounds the cell region; the cell region includes a semiconductor substrate;
the semiconductor substrate comprises a first conductive type substrate 1 and a first conductive type epitaxial layer 2 which is positioned on the first conductive type substrate 1 and is adjacent to the first conductive type epitaxial layer, the upper surface of the first conductive type epitaxial layer 2 is a first main surface of the semiconductor substrate, the lower surface of the first conductive type substrate 1 is a second main surface of the semiconductor substrate, and drain metal 13 is arranged on the second main surface of the semiconductor substrate; a plurality of uniformly distributed grooves 3 are formed in the first conductive type epitaxial layer 2, the grooves 3 extend along the first conductive type epitaxial layer 2 from the first main surface to the second main surface, an upper part and a lower part are arranged in the grooves 3, the upper part comprises control gate polycrystalline silicon 9 and gate oxide layers 10 positioned on two sides of the control gate polycrystalline silicon 9, and the lower part comprises separation gate polycrystalline silicon 11 and a medium isolation cavity 12 for accommodating the separation gate polycrystalline silicon 11; the volume of the separation gate polysilicon 11 is smaller than that of the control gate polysilicon 9, and the thickness of a dielectric isolation cavity 12 between the separation gate polysilicon 11 and the control gate polysilicon 9 is larger than that of the gate oxide layer 10;
a second conductive type body region 4 is arranged between the adjacent grooves 3, the second conductive type body region 4 is arranged in the first conductive type epitaxial layer 2, a first conductive type source region 5 is arranged in the second conductive type body region 4, and the first conductive type source regions 5 are arranged on two sides of the second conductive type body region 4;
an insulating medium layer 6 is arranged on the first main surface of the semiconductor substrate, gate metal 7 and source metal 8 are arranged on the insulating medium layer 6 at intervals, the source metal 8 penetrates through the insulating medium layer 6 to be in ohmic contact with the second conduction type body region 4 and the first conduction type source region 5, and the gate metal 7 penetrates through the insulating medium layer 6 to be in ohmic contact with the control gate polysilicon 9 in the groove 3.
In this embodiment 1, the dielectric isolation cavity 12 has a single-layer structure and is a single-layer SiO2A layer;
the thickness of the gate oxide layer 10 is 600-1200A;
the thickness of the dielectric isolation cavity 12 between the separation gate polysilicon 11 and the control gate polysilicon 9 is 4000-5000A, the thickness of the dielectric isolation cavity 12 corresponding to the two sides of the separation gate polysilicon 11 is 6000-7000A, and the thickness of the cavity wall of the dielectric isolation cavity 12 corresponding to the bottom of the trench 3 is 6000-7000A.
The method of manufacturing the split-gate MOSFET device with reduced switching loss as in embodiment 1 above includes the steps of:
selecting a first conduction type substrate 1, and growing a first conduction type epitaxial layer 2 on the first conduction type substrate, wherein the upper surface of the first conduction type epitaxial layer 2 is a first main surface, and the lower surface of the first conduction type substrate 1 is a second main surface;
under the masking of the hard mask layer window, carrying out anisotropic dry etching on the first main surface, forming a plurality of uniformly distributed grooves 3 in the first conduction type epitaxial layer 2, and removing the hard mask layer window;
adopting an ICPECVD technology, exciting a plasma process by using an inductive coupling mode, and growing a thick silicon dioxide layer on the first main surface and in the groove 3;
depositing conductive polysilicon on the silicon dioxide layer, wherein the groove 3 is filled with the conductive polysilicon;
etching the conductive polysilicon to obtain small-volume separation gate polysilicon 11 below the trench 3;
adopting an ICPECVD technology and utilizing an inductive coupling mode to excite a plasma process, and continuously growing a very thick silicon dioxide layer on the separation gate polysilicon 11 in the groove 3;
removing the oxide layer on the first main surface and the silicon dioxide layer on the side wall of the groove by dry and wet etching to obtain a gate oxide layer 10 positioned on the side wall of the upper part of the groove and a medium isolation cavity 12 positioned at the lower part of the groove and formed by thick silicon dioxide layers;
SiO for preparing medium isolation cavity 122The layer conditions are that an ICPECVD technology is adopted, a plasma process is excited in an inductive coupling mode, the temperature of a reaction furnace is 100-200 ℃, the pressure of the reaction chamber is 6Pa, the radio frequency power is 400W, silane and oxygen are used as reaction gases, wherein the silane is a mixed gas of silane containing argon with the volume fraction of 5% and argon, the flow rates of the reaction gases of the silane and the oxygen are 130.5ml/min and 13ml/min respectively, and the flow rate of the diluent gas of the argon is 126 ml/min;
step eight, continuously depositing conductive polysilicon on the first main surface and in the groove 3, and etching to remove the conductive polysilicon on the first main surface to obtain control gate polysilicon 9 covering the upper part of the groove, wherein the control gate polysilicon 9 is positioned on the upper part of the medium isolation cavity 12;
step nine, implanting second conductive type impurity ions into the first main surface in a self-aligned manner, and forming a second conductive type body region 4 through high-temperature junction pushing;
step ten, selectively injecting high-concentration first conductive type impurity ions on the first main surface through the shielding of a photoetching mask, and forming a first conductive type source region 5 through high-temperature junction pushing;
step eleven, depositing an insulating medium layer 6 on the first main surface, and etching the insulating medium layer 6 to obtain a metal contact hole;
step twelve, depositing metal on the insulating medium layer 6 and in the metal contact hole, and etching the metal to obtain source metal 8 in ohmic contact with the second conductive type body region 4 and the first conductive type source region 5 respectively, and simultaneously obtain gate metal 7 in ohmic contact with the control gate polysilicon 9;
and step thirteen, thinning the second main surface, and depositing metal on the second main surface to obtain drain metal 13, wherein the drain metal 13 is in ohmic contact with the first conductive type substrate 1.
Example 2
A split gate MOSFET device with reduced switching loss comprises a cell region and a terminal protection region, wherein the cell region is positioned in the central region of the device, and the terminal protection region surrounds the cell region; the cell region includes a semiconductor substrate;
the semiconductor substrate comprises a first conductive type substrate 1 and a first conductive type epitaxial layer 2 which is positioned on the first conductive type substrate 1 and is adjacent to the first conductive type epitaxial layer, the upper surface of the first conductive type epitaxial layer 2 is a first main surface of the semiconductor substrate, the lower surface of the first conductive type substrate 1 is a second main surface of the semiconductor substrate, and drain metal 13 is arranged on the second main surface of the semiconductor substrate; a plurality of uniformly distributed grooves 3 are formed in the first conductive type epitaxial layer 2, the grooves 3 extend along the first conductive type epitaxial layer 2 from the first main surface to the second main surface, an upper part and a lower part are arranged in the grooves 3, the upper part comprises control gate polycrystalline silicon 9 and gate oxide layers 10 positioned on two sides of the control gate polycrystalline silicon 9, and the lower part comprises separation gate polycrystalline silicon 11 and a medium isolation cavity 12 for accommodating the separation gate polycrystalline silicon 11; the volume of the separation gate polysilicon 11 is smaller than that of the control gate polysilicon 9, and the thickness of a dielectric isolation cavity 12 between the separation gate polysilicon 11 and the control gate polysilicon 9 is larger than that of the gate oxide layer 10;
a second conductive type body region 4 is arranged between the adjacent grooves 3, the second conductive type body region 4 is arranged in the first conductive type epitaxial layer 2, a first conductive type source region 5 is arranged in the second conductive type body region 4, and the first conductive type source regions 5 are arranged on two sides of the second conductive type body region 4;
an insulating medium layer 6 is arranged on the first main surface of the semiconductor substrate, gate metal 7 and source metal 8 are arranged on the insulating medium layer 6 at intervals, the source metal 8 penetrates through the insulating medium layer 6 to be in ohmic contact with the second conduction type body region 4 and the first conduction type source region 5, and the gate metal 7 penetrates through the insulating medium layer 6 to be in ohmic contact with the control gate polysilicon 9 in the groove 3.
In embodiment 2, the thickness of the gate oxide layer 10 is 600 to 1200A;
the dielectric isolation cavity 12 is formed by two silicon dioxide layers, namely a first silicon dioxide layer 12.1 and a second silicon dioxide layer 12.3, wherein the thickness of each silicon dioxide layer is 1300-2400A, the thickness of each silicon nitride layer 12.2 is 1300-2400A, and a silicon nitride layer 12.2 is sandwiched between the first silicon dioxide layer 12.1 and the second silicon dioxide layer 12.3.
The method of manufacturing the split-gate MOSFET device with reduced switching loss as in embodiment 2 above includes the steps of:
selecting a first conduction type substrate 1, and growing a first conduction type epitaxial layer 2 on the first conduction type substrate, wherein the upper surface of the first conduction type epitaxial layer 2 is a first main surface, and the lower surface of the first conduction type substrate 1 is a second main surface;
under the masking of the hard mask layer window, carrying out anisotropic dry etching on the first main surface, forming a plurality of uniformly distributed grooves 3 in the first conduction type epitaxial layer 2, and removing the hard mask layer window;
adopting an ICPECVD technology, exciting a plasma process in an inductive coupling mode, growing a first silicon dioxide layer on the first main surface and in the groove, then exciting the plasma process on the first silicon dioxide layer in the inductive coupling mode, continuously growing a first silicon nitride layer, and continuously growing a second silicon dioxide layer on the first silicon nitride layer;
continuing to deposit conductive polysilicon on the second silicon dioxide layer, wherein the conductive polysilicon is filled below the groove 3;
etching the conductive polysilicon to obtain small-volume separation gate polysilicon 11 below the trench 3;
adopting an ICPECVD technology, exciting a plasma process by using an inductive coupling mode, and continuously growing a third silicon dioxide layer on the small-volume separation gate polysilicon 11 in the groove;
etching off the silicon dioxide layer on the upper part of the trench 3;
step eight, continuing to grow a second silicon nitride layer on the third silicon dioxide layer in the groove 3;
step nine, etching the silicon nitride layer on the upper part of the groove 3;
step ten, continuing to grow a fourth silicon dioxide layer on the second silicon nitride layer in the groove 3;
step eleven, removing the silicon dioxide layer, the silicon nitride layer and the silicon dioxide layer on the side wall of the groove 3 on the first main surface through dry etching and wet etching to obtain a gate oxide layer 10 on the side wall of the upper part of the groove and a dielectric isolation cavity 12 formed by alternately arranging the silicon dioxide layer and the silicon nitride layer on the lower part of the groove 3;
preparing the SiO of the dielectric isolation cavity 122The layer conditions are that an ICPECVD technology is adopted, a plasma process is excited in an inductive coupling mode, the temperature of a reaction furnace is 100-200 ℃, the pressure of the reaction chamber is 6Pa, the radio frequency power is 400W, silane and oxygen are used as reaction gases, wherein the silane is a mixed gas of silane containing argon with the volume fraction of 5% and argon, the flow rates of the reaction gases of the silane and the oxygen are 130.5ml/min and 13ml/min respectively, and the flow rate of the diluent gas of the argon is 126 ml/min;
the SiN layer of the medium isolation cavity 12 is prepared under the conditions that the temperature of a reaction furnace is 150-300 ℃, the pressure of the reaction chamber is 1-5 Pa, silane and nitrogen are used as reaction gases, wherein the silane is a mixed gas of silane containing 15% by volume of ammonia and the ammonia, and SiH4And N2The gas flow rate ratio is 30: 15-38: 30, and the radio frequency power density is 0.05-0.25W/cm2；
Step twelve, continuously depositing conductive polysilicon on the first main surface and in the trench 3, and etching to remove the conductive polysilicon on the first main surface to obtain control gate polysilicon 9 covering the upper part of the trench 3, wherein the control gate polysilicon 9 is positioned on the upper part of the dielectric isolation cavity 12;
step thirteen, implanting second conductive type impurity ions into the self-aligned ions on the first main surface, and forming a second conductive type body region 4 through high-temperature junction pushing;
fourteen, selectively injecting high-concentration first conductive type impurity ions on the first main surface through the shielding of a photoetching mask, and forming a first conductive type source region 5 through high-temperature junction pushing;
fifteen, depositing an insulating medium layer 6 on the first main surface, and etching the insulating medium layer 6 to obtain a metal contact hole;
sixthly, depositing metal on the insulating medium layer 6 and in the metal contact hole, and etching the metal to obtain source metal 8 in ohmic contact with the second conductive type body region 4 and the first conductive type source region 5 respectively, and simultaneously obtain gate metal 7 in ohmic contact with the control gate polysilicon 9;
seventhly, thinning the second main surface, and depositing metal on the second main surface to obtain drain metal 13, wherein the drain metal 13 is in ohmic contact with the first conductive type substrate 1;
the comparison of performance parameters of conventional split-gate devices with those of examples 1 and 2 of the present invention is illustrated below using a 100V 7A split-gate (SGT) as an example, as shown in table 1 and fig. 26:
TABLE 1
| Comparison (cell area same) | Ciss(pF) | Coss(pF) | Qgs(nC) | Qds(nC) | Qg(nC) |
| Conventional separation grid | 210 | 30 | 1.5 | 1 | 4.5 |
| Inventive example 1 | 203 | 26 | 1.2 | 0.93 | 4.12 |
| Inventive example 2 | 185 | 23 | 1.05 | 0.84 | 3.89 |
As can be seen from fig. 26, compared with the conventional split-gate device, the input capacitance Ciss and the output capacitance Coss in embodiment 1 of the present invention are both smaller than the conventional split-gate device, and the Qg is also smaller than the conventional split-gate device; the input capacitance Ciss and the output capacitance Coss of the embodiment 2 of the invention are smaller than those of the embodiment 1, and the Qg is also smaller than that of the embodiment 1; therefore, the embodiment 2 of the invention has the minimum Qg and the minimum switching loss, thereby greatly reducing the switching loss of the device and improving the performance of the device.
According to the invention, the relative overlapping area of the control gate polysilicon 9 and the separation gate polysilicon 11 is reduced by reducing the volume of the separation gate polysilicon (Source polysilicon), and the distance between the control gate polysilicon 9 and the separation gate polysilicon 11 is increased, namely, the capacitance Cgs between the gate and the Source is reduced, so that the input capacitance Ciss is reduced, the input capacitance Ciss is Cgs + Cgd, and the switching loss is reduced;
according to the invention, the relative overlapping area of the drain and the Source is reduced by reducing the volume of the split gate polysilicon (Source poly), and the distance between the drain and the Source is increased, namely, the capacitance Cgd between the drain and the Source is reduced, so that the output capacitance Coss is reduced, the output capacitance Coss is Cds + Cgd, and the switching loss is reduced;
according to the invention, the split gate polysilicon 11 is accommodated in the dielectric isolation cavity 12, the dielectric isolation cavity 12 is obtained by a high-density Plasma Enhanced Chemical Vapor Deposition (PECVD) (ICPECVD) process, the compactness of the dielectric isolation cavity is better than that of silicon dioxide grown by thermal oxidation in the prior art, the thickness of the cavity wall of the dielectric isolation cavity 12 is very thick and is far greater than that of the gate oxide layer 10, the control gate polysilicon 9 and the split gate polysilicon 11 can be effectively isolated, the coupling capacitance between a gate and a source is reduced, further the input capacitance Ciss is reduced, the switching loss is reduced, the problem of overlarge IGSS electric leakage is solved, and the breakdown resistance at the corner of the bottom of the trench can be improved;
in the invention, the dielectric isolation cavity 12 can be set to be in a structure that a silicon dioxide layer and a silicon nitride layer are alternately distributed, the alternating frequency of the silicon dioxide layer and the silicon nitride layer is not less than 1, and the sizes of the input capacitor Ciss and the output capacitor Coss can be further adjusted by adjusting the alternating frequency of the silicon oxide and the silicon nitride and adjusting the thicknesses of the silicon oxide layer and the silicon nitride layer.
Claims (10)
1. A split gate MOSFET device with reduced switching loss comprises a cell region and a terminal protection region, wherein the cell region is positioned in the central region of the device, and the terminal protection region surrounds the cell region; the cell area comprises a semiconductor substrate, the semiconductor substrate comprises a first conduction type substrate (1) and a first conduction type epitaxial layer (2) which is located on the first conduction type substrate (1) and is adjacent to the first conduction type substrate, the upper surface of the first conduction type epitaxial layer (2) is a first main surface of the semiconductor substrate, and the lower surface of the first conduction type substrate (1) is a second main surface of the semiconductor substrate, and the cell area is characterized in that:
a plurality of grooves (3) which are uniformly distributed are formed in the first conductive type epitaxial layer (2), the grooves (3) extend along the first conductive type epitaxial layer (2) from the first main surface to the second main surface, an upper part and a lower part are arranged in the grooves (3), the upper part comprises a control gate polycrystalline silicon (9) and gate oxide layers (10) positioned on two sides of the control gate polycrystalline silicon (9), and the lower part comprises a separation gate polycrystalline silicon (11) and a medium isolation cavity (12) for containing the separation gate polycrystalline silicon (11); the volume of the separation gate polysilicon (11) is smaller than that of the control gate polysilicon (9), and the thickness of a dielectric isolation cavity (12) between the separation gate polysilicon (11) and the control gate polysilicon (9) is larger than that of the gate oxide layer (10).
2. The split-gate MOSFET device with reduced switching losses of claim 1, wherein: a second conductive type body region (4) is arranged between the adjacent grooves (3), the second conductive type body region (4) is arranged in the first conductive type epitaxial layer (2), a first conductive type source region (5) is arranged in the second conductive type body region (4), and the first conductive type source region (5) is arranged on two sides of the second conductive type body region (4).
3. The split-gate MOSFET device with reduced switching losses of claim 2, wherein: a drain metal (13) is provided on the second main surface of the semiconductor substrate; an insulating medium layer (6) is arranged on a first main surface of the semiconductor substrate, grid metal (7) and source metal (8) are arranged on the insulating medium layer (6) at intervals, the source metal (8) penetrates through the insulating medium layer (6) to be in ohmic contact with the second conduction type body region (4) and the first conduction type source region (5), and the grid metal (7) penetrates through the insulating medium layer (6) to be in ohmic contact with the control grid polysilicon (9) in the groove (3).
4. The split-gate MOSFET device with reduced switching losses of claim 1, wherein: the medium isolation cavity (12) is of a single-layer structure, and the medium isolation cavity (12) is of a single-layer SiO2A layer or single layer of SiN; or the medium isolation cavity (12) is of a multilayer structure, and the medium isolation cavity (12) is made of SiO2A structure in which layers and SiN layers are alternately distributed.
5. A method of fabricating a split-gate MOSFET device with reduced switching losses, comprising the steps of:
selecting a first conduction type substrate (1), growing a first conduction type epitaxial layer (2) on the first conduction type substrate, wherein the upper surface of the first conduction type epitaxial layer (2) is a first main surface, and the lower surface of the first conduction type substrate (1) is a second main surface;
under the masking of the hard mask layer window, carrying out anisotropic dry etching on the first main surface, forming a plurality of uniformly distributed grooves (3) in the first conduction type epitaxial layer (2), and removing the hard mask layer window;
adopting an ICPECVD technology, exciting a plasma process by using an inductive coupling mode, and growing a thick silicon dioxide layer on the first main surface and in the groove (3);
depositing conductive polysilicon on the thick silicon dioxide layer, wherein the groove (3) is filled with the conductive polysilicon;
etching the conductive polysilicon and the thick silicon dioxide layer to obtain small-volume separation gate polysilicon (11) below the trench (3);
adopting an ICPECVD technology, exciting a plasma process by using an inductive coupling mode, and continuously growing a very thick silicon dioxide layer on the separation gate polysilicon (11) in the groove (3);
removing the silicon dioxide layer on the first main surface and part of the silicon dioxide layer on the side wall of the groove by dry and wet etching to obtain a gate oxide layer (10) positioned on the side wall of the upper part of the groove and a medium isolation cavity (12) positioned at the lower part of the groove and formed by the thick silicon dioxide layer;
step eight, continuously depositing conductive polysilicon on the first main surface and in the groove (3), etching and removing the conductive polysilicon on the first main surface to obtain control gate polysilicon (9) covering the upper part of the groove, wherein the control gate polysilicon (9) is positioned on the upper part of the medium isolation cavity (12), and the volume of the control gate polysilicon (9) is larger than that of the separation gate polysilicon (11);
step nine, implanting second conductive type impurity ions on the first main surface in a self-aligned manner, and forming a second conductive type body region (4) through high-temperature junction pushing;
step ten, selectively injecting high-concentration first conductive type impurity ions on the first main surface through the shielding of a photoetching mask, and forming a first conductive type source region (5) through high-temperature junction pushing;
step eleven, depositing an insulating medium layer (6) on the first main surface, and etching the insulating medium layer (6) to obtain a metal contact hole;
step twelve, depositing metal on the insulating medium layer (6) and in the metal contact hole, and etching the metal to obtain source metal (8) in ohmic contact with the second conductive type body region (4) and the first conductive type source region (5) respectively, and simultaneously obtain gate metal (7) in ohmic contact with the control gate polysilicon (9);
and step thirteen, thinning the second main surface, and depositing metal on the second main surface to obtain drain metal (13), wherein the drain metal (13) is in ohmic contact with the first conduction type substrate (1).
6. The method of making a split-gate MOSFET device with reduced switching losses of claim 5, wherein: the thick silicon dioxide layer of the medium isolation cavity (12) is prepared by adopting an ICPECVD technology, exciting a plasma process by utilizing an inductive coupling mode, controlling the temperature of a reaction furnace to be 100-200 ℃, the reaction time to be 200-300 min, the pressure of the reaction chamber to be 6Pa, the radio frequency power to be 400W, and adopting silane and oxygen as reaction gases, wherein the silane is a mixed gas of silane and argon containing 5% of argon by volume fraction, the flow rates of the reaction gases of the silane and the oxygen are respectively 130.5ml/min and 13ml/min, and the flow rate of the diluent gas of the argon is 126 ml/min.
7. A method of fabricating a split-gate MOSFET device with reduced switching losses, comprising the steps of:
selecting a first conduction type substrate (1), and growing a first conduction type epitaxial layer (2) on the first conduction type substrate (1), wherein the upper surface of the first conduction type epitaxial layer (2) is a first main surface, and the lower surface of the first conduction type substrate (1) is a second main surface;
under the masking of the hard mask layer window, carrying out anisotropic dry etching on the first main surface, forming a plurality of uniformly distributed grooves (3) in the first conduction type epitaxial layer (2), and removing the hard mask layer window;
adopting an ICPECVD technology, exciting a plasma process in an inductive coupling mode, growing a first silicon dioxide layer on the first main surface and in the groove, then exciting the plasma process on the first silicon dioxide layer in the inductive coupling mode, continuously growing a first silicon nitride layer, and continuously growing a second silicon dioxide layer on the first silicon nitride layer;
step four, continuously depositing conductive polysilicon on the second silicon dioxide layer, wherein the groove (3) is filled with the conductive polysilicon;
etching the conductive polysilicon to obtain small-volume separation gate polysilicon (11) below the trench (3);
adopting an ICPECVD technology, exciting a plasma process by using an inductive coupling mode, and continuously growing a third silicon dioxide layer on the small-volume separation gate polysilicon (11) in the groove;
etching the third silicon dioxide layer on the upper part of the groove (3);
step eight, continuing to grow a second silicon nitride layer in the groove (3);
step nine, etching the second silicon nitride layer on the upper part of the groove (3);
step ten, continuing to grow a fourth silicon dioxide layer on the second silicon nitride layer in the groove (3);
eleven, removing the silicon dioxide layer on the first main surface and a part of the silicon dioxide layer on the side wall of the groove (3) through dry and wet etching to obtain a gate oxide layer (10) on the side wall of the upper part of the groove (3) and a dielectric isolation cavity (12) formed by alternately arranging the silicon dioxide layer and the silicon nitride layer on the lower part of the groove (3);
step twelve, continuously depositing conductive polysilicon on the first main surface and in the trench (3), and etching to remove the conductive polysilicon on the first main surface to obtain control gate polysilicon (9) covering the upper part of the trench (3), wherein the control gate polysilicon (9) is positioned on the upper part of the dielectric isolation cavity (12), and the volume of the control gate polysilicon (9) is larger than that of the separation gate polysilicon (11);
step thirteen, implanting second conductive type impurity ions on the first main surface by self-aligned ions, and forming a second conductive type body region (4) by high-temperature junction pushing;
fourteen, selectively injecting high-concentration first conductive type impurity ions on the first main surface through the shielding of a photoetching mask, and forming a first conductive type source region (5) through high-temperature junction pushing;
fifteen, depositing an insulating medium layer (6) on the first main surface, and etching the insulating medium layer (6) to obtain a metal contact hole;
sixthly, depositing metal on the insulating medium layer (6) and in the metal contact hole, and etching the metal to obtain source metal (8) in ohmic contact with the second conductive type body region (4) and the first conductive type source region (5) respectively, and simultaneously obtain gate metal (7) in ohmic contact with the control gate polysilicon (9);
seventhly, thinning the second main surface, and depositing metal on the second main surface to obtain drain metal (13), wherein the drain metal (13) is in ohmic contact with the first conduction type substrate (1).
8. The method of making a split-gate MOSFET device with reduced switching losses of claim 7, wherein: the silicon dioxide layer of the medium isolation cavity (12) is prepared by adopting an ICPECVD technology, exciting a plasma process by using an inductive coupling mode, controlling the temperature of a reaction furnace to be 100-200 ℃, the pressure of the reaction chamber to be 6Pa, the radio-frequency power to be 400W, and adopting silane and oxygen as reaction gases, wherein the silane is a mixed gas of silane containing 5% of argon by volume fraction and argon, the flow rates of the reaction gases of silane and oxygen are respectively 130.5ml/min and 13ml/min, and the flow rate of diluent gas argon is 126 ml/min;
the silicon nitride layer of the medium isolation cavity (12) is prepared under the conditions that the temperature of the reaction furnace is 150-300 ℃, the pressure of the reaction chamber is 1-5 Pa, silane and nitrogen are used as reaction gases, wherein the silane is a mixed gas of silane containing 15% by volume of ammonia and ammonia, and SiH4And N2The gas flow rate ratio is 30: 15-38: 30, and the radio frequency power density is 0.05-0.25W/cm2。
9. The split-gate MOSFET device with reduced switching losses and the method of making the same as claimed in claim 1, 5 or 7, wherein: the thickness of a dielectric isolation cavity (12) between the separation gate polysilicon (11) and the control gate polysilicon (9) is 4000-5000A, the thickness of the dielectric isolation cavity (12) corresponding to the two sides of the separation gate polysilicon (11) is 6000-7000A, and the thickness of the cavity wall of the dielectric isolation cavity (12) corresponding to the bottom of the trench (3) is 6000-7000A; the thickness of the gate oxide layer (10) is 600-1200A.
10. The split-gate MOSFET device with reduced switching losses and the method of making the same as claimed in claim 1, 5 or 7, wherein: for an N-type MOSFET device structure, the first conductivity type is N-type conductivity and the second conductivity type is P-type conductivity; for a P-type MOSFET device structure, the first conductivity type is P-type conductivity and the second conductivity type is N-type conductivity.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113078067A (en) * | 2021-03-30 | 2021-07-06 | 电子科技大学 | Manufacturing method of trench separation gate device |
| CN113644028A (en) * | 2021-08-11 | 2021-11-12 | 重庆万国半导体科技有限公司 | Split gate power device and manufacturing method thereof |
| WO2022205727A1 (en) * | 2021-03-30 | 2022-10-06 | 无锡华润上华科技有限公司 | Semiconductor device having split gate structure and manufacturing method therefor |
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2020
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113078067A (en) * | 2021-03-30 | 2021-07-06 | 电子科技大学 | Manufacturing method of trench separation gate device |
| WO2022205727A1 (en) * | 2021-03-30 | 2022-10-06 | 无锡华润上华科技有限公司 | Semiconductor device having split gate structure and manufacturing method therefor |
| CN113644028A (en) * | 2021-08-11 | 2021-11-12 | 重庆万国半导体科技有限公司 | Split gate power device and manufacturing method thereof |
| CN113644028B (en) * | 2021-08-11 | 2023-10-03 | 重庆万国半导体科技有限公司 | Split gate power device and manufacturing method thereof |
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