CN111428195A - Subtraction function approximate calculation device based on random calculation - Google Patents

Subtraction function approximate calculation device based on random calculation Download PDF

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CN111428195A
CN111428195A CN202010234266.8A CN202010234266A CN111428195A CN 111428195 A CN111428195 A CN 111428195A CN 202010234266 A CN202010234266 A CN 202010234266A CN 111428195 A CN111428195 A CN 111428195A
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random
bit stream
unit
random number
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潘红兵
郑沐晗
秦子迪
邱禹欧
董虹希
王宇宣
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Nanjing University
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Abstract

The invention discloses a subtracting function approximate calculation device based on random calculation. The device comprises an input shifting unit, a special value generating unit, a random number generating unit, a logic gate unit and an output counting unit, wherein the input shifting unit obtains an integer part p and a decimal part q obtained after an input independent variable x is shifted to the left by m bits, and the special value generating unit respectively generates lambda and the decimal part q by a logical mapping method
Figure DDA0002430442910000011
In approximation, three random number generating units respectively generate λ,
Figure DDA0002430442910000012
And q is converted into a random bit stream, the logic gate unit carries out bitwise logic operation on the random bit stream through the NAND gate and the AND gate and outputs a corresponding result bit stream, and the output counting unit is used for counting the number of 1 in the bit stream and converting the number into a binary real number for output. Method for device based on random calculation and segment approximationThe method can realize approximate calculation of the subtraction function of input and output in the interval [0, 1], and greatly reduce the power consumption and area overhead of a hardware framework while keeping high precision.

Description

Subtraction function approximate calculation device based on random calculation
Technical Field
The invention relates to the field of design of very large scale integrated circuits, in particular to a hardware device for calculating a subtraction function with high precision and low hardware overhead.
Background
The basic idea of random computation is to convert real numbers lying on the interval [0,1) into a random bit stream by means of a random number generator SNG, the probability of a 1 occurring in the bit stream representing the magnitude of the value. Given a kbit binary number B, the SNG generates a kbit random number R in each clock cycle and compares the size of the random number R with B to obtain 1bit in the random bit stream. After N clock cycles a random bit stream of length N is obtained, with a probability of 1 per bit of p (x) B/2k. Complex arithmetic functions can be mapped to simple bitwise logical operations using random representations.
The realization of multiplication requires very high hardware cost in the aspects of area AND power consumption, AND the multiplication can be realized by using an AND gate AND in unipolar random calculation (x is more than or equal to 0 AND less than 1) or using an XOR gate XNOR in bipolar random calculation (x is more than or equal to 1 AND less than 1). NOT can be used for realizing (1-x) operation in unipolar calculation AND (-x) operation in bipolar calculation.NAND gate can be used for realizing (1-ax) operation, wherein a ∈ [0, 1] the simple logic operations greatly reduce the area AND power consumption overhead of hardware design.
For example, the Cos function is a common trigonometric function, the value range of the Cos function is [ -1,1], and in the interval of [0,1), the Cos function is a monotone decreasing function.
Disclosure of Invention
The invention aims to provide a hardware device for reducing function approximate calculation based on random calculation, which realizes the purposes of high calculation precision, less power consumption and smaller area.
The technical scheme adopted by the invention is as follows:
a subtracting function approximate calculation device based on random calculation comprises an input shift unit, a special value generation unit, a random number generation unit, a logic gate unit and an output counting unit; the input shift unit is used for changing the multiplication operation x to 2mConverting into a shift operation, and extracting an integer part p and a decimal part q generated after an independent variable x is shifted left by m bits, wherein m is the number of sections of the independent variable x on an interval [0, 1); the special value generation unit is used for logically mapping the values of the integer part p to respectively obtain a special value lambda (f) (ph) and a special value
Figure BDA0002430442890000021
Wherein h is 2-m(ii) a The random number generation unit is used for generating a special value lambda,
Figure BDA0002430442890000022
And the fractional part q is converted into random bit streams respectively; the logic gate unit is used for generating
Figure BDA0002430442890000023
And the random bit stream of the fractional part q is represented by performing a bitwise nand operation
Figure BDA0002430442890000024
A bit stream of (a); then will be
Figure BDA0002430442890000025
Bit stream and lambda bit stream are bitwise AND-operated to obtain representation
Figure BDA0002430442890000026
A bit stream of (a); the counting unit is used for calculating
Figure BDA0002430442890000027
The corresponding binary real value is the output calculation result of the number of 1 in the bit stream.
Further, the random number generation unit comprises a linear feedback shift register and a comparator, wherein the linear feedback shift register generates a pseudo random number y in each clock cycle, the comparator compares the pseudo random number y with input binary data z, and if z is larger than y, the random number generation unit outputs 1; if z < y, the random number generation unit outputs 0.
Further, the logic gate unit comprises a NAND gate and an AND gate, wherein the input of the NAND gate is a special value
Figure BDA0002430442890000028
And fractional part q are respectively obtained by two random bit streams through random number generating units, and the output of the two random bit streams is representation
Figure BDA0002430442890000029
A bit stream of (a); the input of the AND gate is a random bit stream and representation obtained by a random number generation unit from lambda (f) (ph)
Figure BDA00024304428900000210
The output of which is a representation
Figure BDA00024304428900000211
The bit stream of (a).
The device for calculating the approximation value of the subtraction function, disclosed by the invention, combines truncation Taylor expansion and piecewise approximation calculation, uses combinational logic mapping and logic gate operation, and avoids the consumption of a large number of lookup tables and multiplier resources, so that the hardware has smaller occupied area and lower power consumption under the condition of keeping the precision of the result of the quasi-total calculation ideal, and has remarkable advantages on a key path, and the device is suitable for the calculation of a continuous and slightly unipolar subtraction function with any input and output positioned in an interval [0,1 ].
Drawings
FIG. 1 is an architectural diagram of the apparatus of the present invention;
FIG. 2 is a schematic diagram of a linear shift feedback register L FSR;
fig. 3 is a schematic diagram of the random number generation unit SNG.
Detailed Description
The invention is described in further detail below with reference to the figures and the detailed description.
This embodiment approximates the subtraction function using the following formula:
Figure BDA00024304428900000212
where x is a function argument, x ∈ [0,1), f (x) where x is x0Is developed, and is delta x-x0. Dividing [0,1) into S-segment subintervals, where S-2mThe length of the subinterval is h 2-mEach segment interval may be represented as being [ α ]i-1,αi) Where i is 1,2, …, S. On subintervals, the truncated taylor expansion is used to determine an approximate linear function, and equation (1) can be approximated as:
f*(x)＝f(x0)+f′(x0)·Δx＝f(x0)+f′(x0)·(x-x0) (2)
the value of the subinterval index i may be determined by the following equation:
Figure BDA0002430442890000031
wherein
Figure BDA0002430442890000032
Is that
Figure BDA0002430442890000033
The integer part of (2) is denoted by p.
Let x0＝αi-1α will bei-1＝(i-1)×h、αiI × h and
Figure BDA0002430442890000034
the bringing into (2) can yield:
Figure BDA0002430442890000035
since i ═ p +1, equation (4) can be converted to:
Figure BDA0002430442890000036
according to equations (4) (5), the following variables are defined:
λ＝f(ph) (6)
Figure BDA0002430442890000037
Figure BDA0002430442890000038
then equation (5) can be written as:
Figure BDA0002430442890000039
since f (x) is a decreasing function over [0, 1], q is
Figure BDA00024304428900000310
The fractional part of (A), therefore 0 < lambda < 1,
Figure BDA00024304428900000311
0 < q < 1, so equation (9) can be computed randomly with a single polarity.
In the apparatus for approximate calculation of a subtraction function based on random calculation according to this embodiment, the value range of the input x is [0, 1], and the value range of the output function result is [0, 1). The overall hardware architecture diagram is shown in fig. 1, and mainly includes five modules working in the following orderRespectively an input shift unit, two special value generating units
Figure BDA00024304428900000312
Three random number generating units (SNG), a logic gate unit and an output counting unit (Counter). The input shift unit takes the high m bits of the kbit binary input argument as the value of p, takes the low (k-m) bits as the value of q, and sets the multiplication operation x to 2mIt is converted into a shift operation (x < m), m being the number of segments of x over the interval [0,1 ]. The special value generation unit maps each bit of p into combinational logic in a logic mapping mode to obtain lambda (f), (ph) sum in binary representationThe value of each bit, thereby obtaining the sum of
Figure BDA0002430442890000042
An approximation of (d). A random number generation unit for generating a random number,
Figure BDA0002430442890000043
And q is converted to length 2kOf the random bit stream. Logic gate unit for calculating
Figure BDA0002430442890000044
The unit realizes two times of multiplication and one time of addition operation by adopting one NAND gate and one AND gate, avoids the use of a multiplier and an adder, and greatly reduces the power consumption, the area and the time delay of a hardware architecture. The counting unit is used for counting
Figure BDA0002430442890000045
The number of 1's in the bit stream is converted to a binary output. The function and the specific implementation process of each unit are explained in detail as follows:
as shown in FIG. 1, the input x in this embodiment is a fixed point number of 10 bits, x ∈ [0,1), 10 bits are both fractional parts, at [0, 1]]The number of the sub-intervals divided up is S-2mThe length of the subinterval being
Figure BDA0002430442890000046
First, in the input shift unit, calculate
Figure BDA0002430442890000047
And
Figure BDA0002430442890000048
i.e. p and q are each
Figure BDA0002430442890000049
The integer part and the fractional part of (c). And also
Figure BDA00024304428900000410
In a hardware implementation, the multiplication may be replaced by a shift operation, so the high m bits of the input x may be assigned to p and the low (10-m) bits to q.
The data after the above processing is 10bit fixed point number without sign bit. The special value generation unit obtains lambda sum according to p through a logical mapping mode
Figure BDA00024304428900000411
An approximation of (d). According to λ and
Figure BDA00024304428900000412
the truth table of mbit of each bit and p in binary representation decimal is arranged into a logic function expression which is mapped into a combinational logic consisting of a series of AND gates, OR gates and NOT gates to generate lambda sum
Figure BDA00024304428900000413
Approximate the corresponding bits of the unit so that the unit generates λ sum quickly
Figure BDA00024304428900000418
The value simultaneously occupies little hardware resource. In this example, take λ (i) and
Figure BDA00024304428900000414
of fractional partThe upper 10 bits are used as the output of the special value generating unit, and when i is 0,1,2 … 7, take Cos function and m is 8 as an example, λ (i) and λ (i) are added
Figure BDA00024304428900000415
The values are listed below:
Figure BDA00024304428900000416
in this example, take λ (i) and
Figure BDA00024304428900000417
the upper 10 bits of the fractional part are taken as the output of the special value generating unit. 10 bits λ (i) and when k is 0,1,2 … 7
Figure BDA0002430442890000051
The expression of the logic function corresponding to each bit of 3 bits of m is as follows: wherein A ═ m [2 ]]、B＝m[1]、C＝m[0]Three bits each representing the value of m,
Figure BDA0002430442890000052
three bits respectively representing m values, n]And
Figure BDA0002430442890000053
respectively represent lambda and
Figure BDA0002430442890000054
the nth bit of (1).
Figure BDA0002430442890000055
As shown in FIG. 2, the random number generation unit includes a linear shift feedback register L FSR and a comparator, the initial state is first set for the linear shift feedback register, the previous state output is reused as input at each clock cycle, k registers can generate kbit binary pseudo-random number y, passing through 2kOne cycle later, the present embodiment generates a 10bit pseudo-random number y with 10bi input per clock cycle L FSRthe binary number x of t is compared with the value, if z is more than y, 1 is output, and if z is less than y, 0 is output; through 210After 1024 clock cycles, a random bit stream of length 1024 is generated. Three random number generating units are respectively used for generating lambda,
Figure BDA0002430442890000056
And q corresponding random bit streams.
The logic gate unit consists of a NAND gate and an AND gate, and the input of the NAND gate is
Figure BDA0002430442890000057
And 1bit at the same position in the q random bit stream, the output is
Figure BDA0002430442890000058
1bit in the bitstream; the inputs of the AND gate are respectively a lambda random bit stream and the output of the NAND gate; over 1024 cycles, the output of the AND gate is representative
Figure BDA0002430442890000059
A bit stream of length 1024.
Output counting unit for statistical representation
Figure BDA00024304428900000510
And is converted into a binary output. Judging the 1bit number generated by the logic gate unit in each clock period: if the value is 1, adding 1 to the value in the counter; if it is 0, the value in the counter remains unchanged. The output result is between [0,1), and the 10-bit binary fixed point number corresponding to the counter value represents the decimal part of the output result.
The present embodiment takes the robot arm control of a tandem robot as an example to illustrate how the present device is applied in practical applications. The mechanical arm is a main execution part of the series robot, the flexibility degree of the mechanical arm plays a crucial role in the working capacity of the robot, and a large amount of Cos function operation is needed when the moving angle of the mechanical arm is calculated. The subtracting function approximate calculation device based on random calculation is applied to a robot control chip, so that the power consumption expense can be reduced, and the calculation precision can be improved.

Claims (3)

1. A subtracting function approximate calculation device based on random calculation comprises an input shift unit, a special value generation unit, a random number generation unit, a logic gate unit and an output counting unit,
the input shift unit is used for changing the multiplication operation x to 2mConverting into a shift operation, and extracting an integer part p and a decimal part q generated after an independent variable x is shifted left by m bits, wherein m is the number of sections of the independent variable x on an interval [0, 1);
the special value generation unit is used for logically mapping the values of the integer part p to respectively obtain a special value lambda (f) (ph) and a special value
Figure FDA0002430442880000011
Wherein h is 2-m；
The random number generation unit is used for generating a special value lambda,
Figure FDA0002430442880000012
And the fractional part q is converted into random bit streams respectively;
the logic gate unit is used for generating
Figure FDA0002430442880000013
And the random bit stream of the fractional part q is represented by performing a bitwise nand operation
Figure FDA0002430442880000014
A bit stream of (a); then will be
Figure FDA0002430442880000015
Bit stream and lambda bit stream are bitwise AND-operated to obtain representation
Figure FDA0002430442880000016
A bit stream of (a);
the counting unit is used for calculating
Figure FDA0002430442880000017
The corresponding binary real value is the output calculation result of the number of 1 in the bit stream.
2. The apparatus according to claim 1, wherein the random number generation unit comprises a linear feedback shift register for generating a pseudo random number y in each clock cycle, and a comparator for comparing the pseudo random number y with an input binary data z, and if z > y, the random number generation unit outputs 1; if z < y, the random number generation unit outputs 0.
3. The device of claim 1, wherein the logic gate unit comprises a nand gate and an and gate, and the input of the nand gate is a special value
Figure FDA0002430442880000018
And fractional part q are respectively obtained by two random bit streams through random number generating units, and the output of the two random bit streams is representation
Figure FDA0002430442880000019
A bit stream of (a); the input of the AND gate is a random bit stream and representation obtained by a random number generation unit from lambda (f) (ph)
Figure FDA00024304428800000110
The output of which is a representation
Figure FDA00024304428800000111
The bit stream of (a).
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113312862A (en) * 2021-06-04 2021-08-27 上海交通大学 LFSR-based random circuit hardware overhead minimization design method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104038770A (en) * 2014-06-05 2014-09-10 中国科学技术大学 Discrete cosine transform (DCT) implementation method and system based on randomized computation
CN110879697A (en) * 2019-10-29 2020-03-13 南京大学 Device for approximately calculating tanh function

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104038770A (en) * 2014-06-05 2014-09-10 中国科学技术大学 Discrete cosine transform (DCT) implementation method and system based on randomized computation
CN110879697A (en) * 2019-10-29 2020-03-13 南京大学 Device for approximately calculating tanh function

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ZIDI QIN 等: "A Universal Approximation Method and Optimized Hardware Architectures for Arithmetic Functions Based on Stochastic Computing", 《IEEE ACCESS》 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113312862A (en) * 2021-06-04 2021-08-27 上海交通大学 LFSR-based random circuit hardware overhead minimization design method
CN113312862B (en) * 2021-06-04 2022-04-05 上海交通大学 LFSR-based random circuit hardware overhead minimization design method

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Application publication date: 20200717