CN111416649A - Digital beam forming method based on zero intermediate frequency architecture - Google Patents
Digital beam forming method based on zero intermediate frequency architecture Download PDFInfo
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- CN111416649A CN111416649A CN202010443458.XA CN202010443458A CN111416649A CN 111416649 A CN111416649 A CN 111416649A CN 202010443458 A CN202010443458 A CN 202010443458A CN 111416649 A CN111416649 A CN 111416649A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
- H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
- H04B7/06—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
- H04B7/0613—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission
- H04B7/0615—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission of weighted versions of same signal
- H04B7/0617—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission of weighted versions of same signal for beam forming
Abstract
The invention discloses a digital beam forming method based on a zero intermediate frequency architecture, which mainly solves the problems of low precision and poor flexibility of the existing beam forming. The zero intermediate frequency architecture comprises an FPGA, a radio frequency transceiver and a radio frequency front end module. The implementation scheme is as follows: initializing the operating environment; the FPGA calculates the weight of DBF formed by digital wave beams, calculates the transmitted waveform data and sends the data to the radio frequency transceiver to generate radio frequency analog signals; the radio frequency analog signal is amplified and then transmitted through an antenna array to form a transmitting beam; the antenna array receives electromagnetic waves in the space, and after low-noise amplification, the electromagnetic waves are output by a corresponding radio frequency transceiver as baseband digital signals and are sent to the FPGA; the FPGA synthesizes these baseband digital signals into a receive beam. The invention improves the resolution, real-time performance and flexibility of beam forming, each antenna unit can be flexibly separated and combined into a new sub-array, and the invention can be applied to communication or radar to realize digital beam forming.
Description
Technical Field
The invention belongs to the technical field of electronic information, and particularly relates to a digital beam forming method based on a zero intermediate frequency architecture. The method can be used for communication or radar systems on airborne, missile-borne and satellite platforms.
Background
The phased array technology controls the direction and shape of a beam in space, namely beam forming, by changing the phase and amplitude of signals transmitted and received by each antenna unit of an antenna array. Compared with the traditional mechanical scanning antenna, the phased array antenna has the advantages of high scanning speed, multi-target tracking capability, high resolution, strong anti-interference capability and the like.
The currently common phased array technology is an active phased array implemented based on an analog circuit, where each up-converted signal is divided into multiple signals by a power divider, the phases and amplitudes of the signals are changed by a phase shifter and an attenuator, and the signals are amplified and transmitted to a space from respective antenna units. The active phased array realized by the analog circuit mode has the following disadvantages:
firstly, the phase shifter and the attenuator at the front end of radio frequency are 5-7 bit precision, although the requirements of some civil and military fields can be met, the precision is not enough in the anti-interference radar and communication equipment with higher performance.
Secondly, the integration level is low, the system receiver and the system transmitter are generally in a super heterodyne architecture, a large number of inductance-capacitance devices are needed to filter out intermediate frequency clutter signals, and the integration in a chip is difficult, so that the system volume is large.
And thirdly, the multi-beam forming flexibility is poor, in a multi-receiving multi-transmitting MIMO radar and multi-receiving multi-transmitting MIMO communication system, the number of main lobes of beams is limited by the number of channels of an analog-to-digital converter and a digital-to-analog converter of the system, each transmitting channel and each receiving channel correspond to a plurality of specific antenna units, the antenna units cannot be multiplexed among the channels, and the multi-beam forming system is difficult to adapt to a complex and variable space environment.
Disclosure of Invention
The invention aims to provide a digital beam forming method based on a zero intermediate frequency architecture aiming at the defects of the prior art so as to improve the phase precision and amplitude precision of beam control, reduce the system volume and realize flexible adaptation to a complex and changeable space environment through the multiplexing of an antenna unit.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a digital beam forming method based on zero intermediate frequency architecture, the said zero intermediate frequency architecture includes three parts of FPGA, radio frequency transceiver and radio frequency front end module, the FPGA is used for the control of the digital signal processing and interface circuit; the radio frequency transceiver is used for performing baseband digital signal FIR filtering, digital-to-analog conversion, analog-to-digital conversion, baseband analog signal low-pass filtering, orthogonal up-down frequency conversion and program control amplification, and each antenna unit corresponds to a receiving channel and a transmitting channel of the radio frequency transceiver; the radio frequency front end module is connected with an antenna array and used for switching a receiving channel and a transmitting channel and amplifying signals, and is characterized by comprising the following implementation steps:
(1) initializing the operating environment: the method comprises the steps of carrying out software configuration on a clock distributor, software configuration on a radio frequency transceiver and multi-channel amplitude-phase calibration of a radio frequency front-end module;
(2) generating a transmission beam:
(2a) the FPGA automatically calculates the weight of the DBF formed by the digital wave beams according to the direction angle, calculates the transmitted waveform data according to the weight, and sends the data to the radio frequency transceiver to generate a radio frequency analog signal;
(2b) amplifying the radio frequency analog signal, and transmitting the amplified radio frequency analog signal through an antenna array to form a transmitting beam in space;
(3) synthesizing a receiving beam:
(3a) the antenna array receives electromagnetic waves from the space, and outputs baseband digital signals through the radio frequency transceiver corresponding to the antenna unit after the electromagnetic waves are amplified by the low noise of the radio frequency front end module; these digital baseband signals are sent from the radio frequency transceiver to the FPGA through the JESD204B high speed serial data link;
(3b) and the FPGA synthesizes the received baseband digital signals into a receiving beam.
Compared with the prior art, the invention has the following advantages:
first, the present invention controls the beam shape by adjusting the baseband digital signal of the rf transceiver, and the amplitude and phase adjustment accuracy of each channel is determined by the performance of the rf transceiver, which is very advantageous in resolution, real-time performance, and flexibility compared to the phase shifter and attenuator used in the conventional method.
Secondly, the invention adopts a zero intermediate frequency architecture, generates and receives radio frequency analog signals through a radio frequency transceiver, realizes up-down frequency conversion, analog-digital conversion and digital-analog conversion from a base band to radio frequency, does not need an additional intermediate frequency signal processing circuit, and greatly reduces the system volume and power consumption.
Thirdly, each antenna unit corresponds to a receiving channel and a transmitting channel of the radio frequency transceiver, so that the antenna units are mutually independent, and the damage of any receiving channel or transmitting channel can not affect other channels, therefore, the antenna units can be flexibly separated and combined into a new subarray.
Drawings
FIG. 1 is a block diagram of a zero intermediate frequency architecture system for use with the present invention;
fig. 2 is a flow chart of the implementation of the present invention.
Detailed Description
The invention is described in detail below with reference to the following figures and examples:
referring to fig. 1, the zero intermediate frequency architecture system used in the present invention mainly comprises three parts, wherein the first part is an FPGA, the second part is a radio frequency transceiver, and the third part is a radio frequency front end module.
The FPGA is used for controlling a digital signal processing and interface circuit, carrying out software configuration on the radio frequency transceiver through an SPI interface, and carrying out receiving and sending of baseband digital signals on the radio frequency transceiver through a JESD204B high-speed serial data link;
the radio frequency transceiver can be selected from AD9371, ADRV9009, ADRV9026 and the like of ADI (analog to digital converter) company of the Asia-Deno semiconductor, and is used for carrying out FIR (finite Impulse response) filtering, digital-to-analog conversion, analog-to-digital conversion, low-pass filtering, orthogonal up-down frequency conversion and program-controlled amplification on baseband digital signals, and each antenna unit corresponds to one receiving channel and one transmitting channel of the radio frequency transceiver;
and the radio frequency front-end module is connected with the antenna array and the radio frequency transceiver and is used for switching a receiving channel and a transmitting channel and amplifying signals.
Referring to fig. 2, the implementation steps of this example include the following:
step 1, initializing the operating environment.
1.1) carrying out software configuration on the clock distributor:
the clock distributor, which may also be referred to as a clock generator, may use a clock distributor such as CDCM6208, L MK03318 or L MK04805 from Texas instruments TI, or other company suitable clock distributors.
The clocks that the clock distributor needs to output include the following:
a baseband global clock G L OB L E _ C L K provided for the FPGA,
A GTH high-speed transceiving interface reference clock GTH _ REFC L K provided for the FPGA,
A driving clock DEV _ C L K provided for the radio frequency transceiver,
And a system reference clock SYSREF _ C L K of the JESD204B high-speed serial data link provided for the FPGA and the radio frequency transceiver.
The 4 clocks are determined by the system sampling rate and the JESD204B high-speed serial data link rate, so that the optimal frequency can be flexibly selected. If the number of output clocks of a single clock distributor is not enough to provide the number of input clocks of all relevant FPGAs and radio frequency transceivers of the system, a clock buffer is needed to expand the number of clocks, and the clock buffer is used for copying one-way clock into multiple-way clocks with the same frequency and phase.
The software configuration of the clock distributor in the embodiment can provide the FPGA and the radio frequency transceiver of the system with the homologous clock which is necessary for the operation of the digital circuit in the chip and the digital interface between the chips.
1.2) carrying out software configuration on a radio frequency transceiver:
the main contents of the configuration at least comprise the configuration of an on-chip clock phase-locked loop P LL, the configuration of an inter-chip synchronous function, the configuration of a local oscillator, the configuration of a sampling rate of a transmitting-receiving channel and the configuration of an attenuation value of the transmitting-receiving channel, wherein:
the on-chip clock phase-locked loop P LL is configured for generating a digital circuit operation clock, an interface clock, a sampling clock and a radio frequency local oscillator clock of the radio frequency transceiver;
the inter-chip synchronization function configuration is used for setting the JESD204B high-speed serial data transmission protocol into a multi-chip synchronization function so as to keep the phases of baseband sampling clocks of the transmitting and receiving channels of the multi-chip radio frequency transceiver consistent;
local oscillator configuration, including clock source selection and frequency selection, wherein if the clock performance requirement of the radio frequency local oscillator is not high, the radio frequency local oscillator generated in the radio frequency transceiver can be selected to simplify the circuit design; if the requirement on the clock performance of the radio frequency local oscillator is higher, a local oscillator clock source with higher performance can be generated through an external circuit and then input into the radio frequency transceiver;
the receiving and transmitting channel sampling rate configuration is used for setting the sampling rates of the analog-to-digital converter and the digital-to-analog converter of the receiving channel and the transmitting channel and needs to be matched with a baseband clock of the FPGA;
and the receiving and transmitting channel attenuation value configuration is used for setting the radio frequency signal amplitude of the receiving channel and the transmitting channel so that the radio frequency transceiver is in the best signal-to-noise ratio in the receiving and transmitting states.
The initialization software configuration of the RF transceiver in this example can make the RF transceiver operate in the multi-channel synchronous mode to realize the digital array control.
1.3) carrying out multichannel amplitude-phase calibration on the radio frequency front end:
and calibrating the multichannel amplitude phase of the radio frequency front end, wherein the calibration content comprises the amplitude phase calibration of the receiving multichannel and the amplitude phase calibration of the transmitting multichannel. Because the local oscillator clock in the radio frequency transceiver needs to be subjected to frequency division by the frequency divider and then subjected to up-down frequency conversion, the phase of the local oscillator clock is randomly changed after the frequency division, and the amplitude-phase error between each receiving channel and each transmitting channel is inconsistent due to the production manufacturing error of the radio frequency front-end module.
The amplitude and phase calibration thought of the transmitting channel and the receiving channel is that amplitude and phase errors between each channel and a reference channel are calculated, compensation is carried out in an FPGA through software, and error compensation coefficients are calculated through the following formula:
where k is the channel number of the transmit channel or the receive channel, k is 1,2, 3.
Error compensation coefficient for the k channel, Hk(f) Amplitude-frequency response of system function for k channel, where Xk(f) Frequency spectrum of signal outputted for k channel, Xk(f) After the waveform of the specific frequency of the kth channel is collected, FFT is carried out in FPGA to obtain the waveform.
In the embodiment, the multichannel amplitude-phase calibration of the radio frequency front end can realize channel equalization for each transmitting channel and each receiving channel of the system.
And 2, generating a transmitting beam.
The specific implementation of this step is as follows:
2.1) calculating the weight of the digital beam forming DBF:
the FPGA automatically calculates the weight of the DBF formed by the digital wave beam according to the direction angle, the calculation method of the DBF weight is not limited to an algorithm, and common calculation criteria comprise a Minimum Mean Square Error (MMSE) criterion, a maximum signal-to-noise ratio (MSNR) criterion, a linear constraint minimum variance L CMV criterion and the likekW of thekForming weights, W, of DBF for kth channel digital beamkThe meaning of the modulus is the k channel signal amplitude, WkThe meaning of the proportional value of the imaginary part and the real part is the phase value of the kth channel signal; the transmit beamforming and the receive beamforming of the same direction angle share the weight W of the same group of digital beamforming DBFk；
2.2) calculating the emission waveform data:
the FPGA calculates the transmitted waveform data according to the weight of the DBF formed by the digital beam, and the calculation formula is as follows:
where k is the channel number of the transmit channel, k is 1,2,3k(t) is the transmitted waveform data of the kth channel, WkWeights for the DBF are formed for the kth channel digital beam,
for the error compensation coefficient of the kth transmission channel, s (t) is baseband data, where s (t) may be a single frequency waveform signal for directional diagram test, or a QPSK modulation signal for communication, or a chirp signal for radar target detection, and the like, and a sampling clock of the baseband data needs to be matched with a digital-to-analog conversion sampling clock of a radio frequency transceiver, which is selected but not limited to a single frequency waveform signal in this example;
2.3) transmitting the transmitted waveform data to a radio frequency transceiver to generate a radio frequency analog signal:
the FPGA is connected with the radio frequency transceiver through a JESD204B high-speed serial data link, an IP core related to the JESD204B is configured in the FPGA, the transmitted waveform data is input to an IP core interface related to the JESD204B according to a specific data format of the JESD204B and is transmitted through a GTH high-speed transceiving interface of the FPGA;
after receiving the transmitted waveform data transmitted from the JESD204B interface, the radio frequency transceiver filters the data in the chip by baseband digital FIR filtering, then converts the data into an analog signal by a digital-to-analog converter, then sequentially realizes baseband analog low-pass filtering, orthogonal up-conversion and program-controlled amplification in the chip, and finally outputs a radio frequency analog signal on a transmission channel pin;
2.4) after amplifying the radio frequency analog signal, transmitting and forming a beam by the antenna array:
in the transmitting mode, each transmitting channel of the radio frequency transceiver is connected with the input end of the corresponding transmitting channel of the radio frequency front-end module. After generating a radio frequency transmitting signal, the radio frequency transceiver enters a transmitting channel of a radio frequency front end module, amplifies the signal by a power amplifier of the radio frequency front end module, and transmits the signal to an antenna unit by a radio frequency switch;
and finally, the radio frequency transmitting signals of all the channels are transmitted to the space through the antenna array to form transmitting beams.
And 3, synthesizing a receiving beam.
The specific implementation of this step is as follows:
3.1) the antenna array receives electromagnetic waves from the space and the electromagnetic waves are amplified by the radio frequency front end module in a low noise mode:
in a receiving mode, a radio frequency switch of a radio frequency front-end module connects each antenna unit to a receiving channel, the antenna receives electromagnetic signals in space and converts the electromagnetic signals into radio frequency analog signals in a current form, and because the amplitude of the radio frequency analog signals at the moment is small, in order to improve the receiving sensitivity of a system, the signals need to be amplified to a proper size through a low noise amplifier and then received by a radio frequency transceiver;
3.2) the radio frequency transceiver receives the radio frequency analog signal and outputs a baseband digital signal:
each radio frequency transceiver corresponding to each antenna unit receives a radio frequency receiving signal from a radio frequency front end, and then program control amplification, orthogonal down conversion, baseband analog low-pass filtering, analog-to-digital conversion and baseband digital FIR filtering are sequentially carried out in a chip to become a baseband digital signal; finally, the baseband digital signals are sent to the FPGA through a JESD204B high-speed serial data link; the FPGA receives the baseband digital signals through a GTH high-speed transceiving interface;
3.3) the FPGA synthesizes the received baseband digital signals into a receiving beam:
wherein y isr(t) is the result of the synthesis of the receive beam, k is the channel number of the receive channel, k is 1,2,3kForming weights, x, of DBF for kth channel digital beamk(t) baseband digital signals for the kth receive channel received by the FPGA,
the error compensation coefficient for the k-th receive channel.
The foregoing description is only an example of the present invention and is not intended to limit the invention, so that it will be apparent to those skilled in the art that various changes and modifications in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims (9)
1. A digital beam forming method based on zero intermediate frequency architecture, the said zero intermediate frequency architecture includes three parts of FPGA, radio frequency transceiver and radio frequency front end module, the FPGA is used for the control of the digital signal processing and interface circuit; the radio frequency transceiver is used for performing baseband digital FIR filtering, digital-to-analog conversion, analog-to-digital conversion, baseband analog signal low-pass filtering, orthogonal up-down frequency conversion and program control amplification, and each antenna unit corresponds to a receiving channel and a transmitting channel of the radio frequency transceiver; the radio frequency front end module is connected with an antenna array and used for switching a receiving channel and a transmitting channel and amplifying signals, and is characterized by comprising the following implementation steps:
(1) initializing the operating environment: the method comprises the steps of carrying out software configuration on a clock distributor, software configuration on a radio frequency transceiver and multi-channel amplitude-phase calibration of a radio frequency front-end module;
(2) generating a transmission beam:
(2a) the FPGA automatically calculates the weight of the DBF formed by the digital wave beams according to the direction angle, calculates the transmitted waveform data according to the weight, and sends the data to the radio frequency transceiver to generate a radio frequency analog signal;
(2b) amplifying the radio frequency analog signal, and transmitting the amplified radio frequency analog signal through an antenna array to form a transmitting beam in space;
(3) synthesizing a receiving beam:
(3a) the antenna array receives electromagnetic waves from the space, and outputs baseband digital signals through the radio frequency transceiver corresponding to the antenna unit after the electromagnetic waves are amplified by the low noise of the radio frequency front end module; these digital baseband signals are sent from the radio frequency transceiver to the FPGA through the JESD204B high speed serial data link;
(3b) and the FPGA synthesizes the received baseband digital signals into a receiving beam.
2. The method of claim 1, wherein the software configuration of the clock distributor in (1) comprises the following clocks:
a baseband global clock G L OB L E _ C L K provided for the FPGA;
a GTH high-speed transceiving interface reference clock GTH _ REFC L K provided for the FPGA;
a driving clock DEV _ C L K provided to the radio frequency transceiver;
the JESD204B high-speed serial data link system reference clock SYSREF _ C L K is provided to the FPGA and the radio frequency transceiver.
3. The method of claim 1, wherein the software configuration of the RF transceiver in (1) is performed by writing the RF transceiver register in the FPGA through the SPI interface, and the main contents of the configuration at least include an on-chip clock phase-locked loop P LL configuration, an inter-chip synchronization function configuration, a local oscillator configuration, a transceiving channel sampling rate configuration, and a transceiving channel attenuation value configuration.
4. The method of claim 1, wherein in (1), the multi-channel amplitude-phase calibration of the radio frequency front end is performed by performing amplitude-phase calibration on each channel according to the following error compensation coefficient formula:
where k is the channel number of the transmit channel or the receive channel, k is 1,2, 3.
Error compensation coefficient for the k channel, Hk(f) Amplitude-frequency response of system function for k channel, where Xk(f) Frequency spectrum of signal outputted for k channel, Xk(f) After the waveform of the specific frequency of the kth channel is collected, FFT is carried out in FPGA to obtain the waveform.
5. The method of claim 1, wherein the FPGA in (2a) automatically calculates the DBF weight according to the direction angle, and the calculation method is determined according to the specific requirement, and the calculation result is represented as W by complex numberkW of thekForming weights, W, of DBF for kth channel digital beamkThe meaning of the modulus is the k channel signal amplitude, WkThe meaning of the proportional value of the imaginary part and the real part is the phase value of the kth channel signal; the transmit beamforming and the receive beamforming of the same direction angle share the weight W of the same group of digital beamforming DBFk。
6. The method of claim 1, wherein the transmit waveform data is calculated according to the weights of the digital beam forming DBF in (2a), and the formula is as follows:
where k is the channel number of the transmit channel, k is 1,2,3k(t) is the transmitted waveform data of the kth channel, WkWeights for the k-th channel digital beam forming DBF, s (t) are baseband data,
the error compensation coefficient for the k-th transmit channel.
7. The method of claim 1, wherein the transmitting waveform data in (2a) is transmitted to the rf transceiver to generate the rf analog signal, and the transmitting waveform data is transmitted to the rf transceiver in the transmitting mode, and then is subjected to the baseband digital FIR filtering, the digital-to-analog conversion, the baseband analog low-pass filtering, the quadrature up-conversion and the programmable amplification to form the rf analog signal, and the transmitting waveform data is transmitted from the FPGA to the rf transceiver through the JESD204B high-speed serial data link.
8. The method of claim 1, wherein the outputting of the baseband digital signal through the rf transceiver corresponding to the antenna unit in (3a) is that, in the receiving mode, the rf transceiver performs programmable amplification, quadrature down-conversion, baseband analog low-pass filtering, analog-to-digital conversion, and baseband digital FIR filtering on the received rf analog signal in sequence to obtain the digital baseband signal.
9. The method of claim 1, wherein the FPGA in (3b) synthesizes the received baseband digital signals into a receive beam by the following formula:
wherein y isr(t) is the result of the synthesis of the receive beam, k is the channel number of the receive channel, k is 1,2,3kForming weights, x, of DBF for kth channel digital beamk(t) is the baseband digital signal of the kth receiving channel received by the FPGA,
the error compensation coefficient for the k-th receive channel.
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| CN113422632A (en) * | 2021-05-25 | 2021-09-21 | 航天科工空间工程发展有限公司 | Satellite communication system |
| CN113644920A (en) * | 2021-06-16 | 2021-11-12 | 北京协同创新研究院 | Microwave multi-path receiving and transmitting system for brain imaging |
| CN113644920B (en) * | 2021-06-16 | 2022-10-14 | 北京协同创新研究院 | Microwave multi-channel receiving and transmitting system for brain imaging |
| CN115276678A (en) * | 2022-05-25 | 2022-11-01 | 北京理工大学 | Reconfigurable phase consistency array transmitting system |
| CN115276678B (en) * | 2022-05-25 | 2023-09-01 | 北京理工大学 | Reconfigurable phase consistency array transmitting system |
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