CN111404504A - RS485 bus differential signal amplifier - Google Patents
RS485 bus differential signal amplifier Download PDFInfo
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- CN111404504A CN111404504A CN202010491963.1A CN202010491963A CN111404504A CN 111404504 A CN111404504 A CN 111404504A CN 202010491963 A CN202010491963 A CN 202010491963A CN 111404504 A CN111404504 A CN 111404504A
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Abstract
The invention discloses an RS485 bus differential signal amplifier which is characterized by comprising a first bus interface, a second bus interface, a first RS485 conversion module, a second RS485 conversion module and a signal processing module, wherein the first bus interface is connected with a differential signal port of the first RS485 conversion module, a level signal port of the first RS485 conversion module is connected with an input end of the signal processing module, an output end of the signal processing module is connected with a level signal port of the second RS485 conversion module, the second bus interface is connected with a differential signal port of the second RS485 conversion module, the signal processing module is used for receiving a level signal and controlling the transceiving states of the first RS485 conversion module and the second RS485 conversion module according to the transmission direction of the level signal, the amplifier converts the differential signal into a TT L level signal, then performs a series of phase inversion processing on the TT L level signal, and finally restores the TT L level signal into the differential signal, so that the attenuated differential signal is amplified and the differential signal is accurately judged.
Description
Technical Field
The invention relates to a signal amplifier, in particular to an RS485 bus differential signal amplifier.
Background
The RS485 bus is one of the communication commonly used in the field of industrial communication at present, and is frequently used in intelligent instruments, intelligent home furnishing and industrial control. In the RS485 communication network, a master-slave communication mode is generally adopted, that is, one master computer has multiple slave computers. The differential line technology is adopted for signal transmission to carry out communication, namely, the signal difference between two lines is utilized to transmit a digital signal 0 or 1, and for RS485, the two lines are A and B. Generally, when the voltage of A-B is greater than or equal to 0.2V, a signal 1 is transmitted on the bus; when the voltage of the A-B is less than or equal to-0.2V, a signal 0 is transmitted on the bus; and a-B is greater than-0.2 and less than 0.2, the bus signal cannot be determined to be either a 1 or a 0; the voltage between AB in the idle state is high. Its advantages are simple wiring, long transmission distance and high anti-interference power.
In theory, tens or hundreds of slave machines can be mounted on the RS485 bus, and in theory, the transmission distance can reach hundreds of meters to kilometers, so that the distance requirement required by most control quantities is met. However, in actual engineering use, the actual value and the theoretical value are far from each other due to the material of the wire and the field situation of actual engineering wiring. The signal on the bus is transmitted from the host computer over a long distance and is greatly attenuated when the impedance of the wire rod affects the tail end, so that the voltage difference between A, B is too small and is between an interval which is larger than-0.2 and smaller than 0.2, the signal transmission is not normal in bus communication, and the signal transmitted from the host computer to the slave computer over a long distance is affected by the impedance factor of the wire rod to be abnormal in the signal received on the host computer.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide the RS485 bus differential signal amplifier, which can avoid the situation that differential signals cannot be accurately judged due to signal attenuation of the RS485 bus and ensure the accuracy of remote communication of the RS485 bus.
In order to achieve the purpose, the invention provides the following technical scheme:
an RS485 bus differential signal amplifier comprises a first bus interface, a second bus interface, a first RS485 conversion module, a second RS485 conversion module and a signal processing module, the first bus interface is connected with a differential signal port of a first RS485 conversion module, a level signal port of the first RS485 conversion module is connected with an input end of a signal processing module, the output end of the signal processing module is connected with the level signal port of the second RS485 conversion module, the second bus interface is connected with a differential signal port of a second RS485 conversion module, the first RS485 conversion module and the second RS485 conversion module are used for converting differential signals into level signals or converting the level signals into differential signals, the signal processing module is used for receiving the level signal and controlling the receiving and sending states of the first RS485 conversion module and the second RS485 conversion module according to the transmission direction of the level signal.
As a preferable scheme: the signal processing module comprises a first phase inverter, a second phase inverter, a first isolation module and a second isolation module, wherein the first phase inverter comprises a first phase inversion unit, a second phase inversion unit, a third phase inversion unit, a fourth phase inversion unit, a fifth phase inversion unit and a sixth phase inversion unit which are independent of each other, the second phase inverter comprises a seventh phase inversion unit, an eighth phase inversion unit, a ninth phase inversion unit, a tenth phase inversion unit, an eleventh phase inversion unit and a twelfth phase inversion unit which are independent of each other, the output end of the first phase inversion unit is connected with the input end of the second phase inversion unit, the output end of the second phase inversion unit is connected with the transmitting end of the first RS485 conversion module, the input end of the third phase inversion unit is connected with the receiving end of the first RS485 conversion module, the output end of the third phase inversion unit is connected with the input end of the first isolation module, the output end of the sixth phase inversion unit is connected with the input end of the fifth, the output end of the fourth inverting unit is connected with the enabling end of the first RS485 converting module, the output end of the twelfth inverting unit is connected with the output end of the first isolating module, the output end of the twelfth inverting unit is connected with the input end of the seventh inverting unit, the output end of the seventh inverting unit is connected with the transmitting end of the second RS485 converting module, the input end of the ninth inverting unit is connected with the receiving end of the second RS485 converting module, the output end of the ninth inverting unit is connected with the input end of the second isolating module, the output end of the second isolating module is connected with the input end of the first inverting unit and the input end of the sixth inverting unit, the input end of the eleventh inverting unit is connected with the output end of the first isolating module, the output end of the eleventh inverting unit is connected with the input end of the tenth inverting unit, and the output end of the tenth inverting unit is connected with the input end of the eighth inverting unit, and the output end of the eighth inverting unit is connected with the enabling end of the second RS485 conversion module.
As a preferable scheme: the first RS485 conversion module adopts a chip U4 with the model number of SN75176, pin No. 5 of U4 is grounded, pin No. 6 of U4 is connected with port No. 2 of first bus interface J1, pin No. 7 of U4 is connected with port No. 3 of J1, pin No. 8 of U4 is connected with power VCC, pin No. 6 of U4 is connected with power VCC through resistance R2, power VCC is connected with port No. 1 of J1, pin No. 7 of U4 is grounded through resistance R6, port No. 4 of J1 is grounded, pin No. 1 of U4 is connected with power VCC through resistance R9.
Preferably, the first inverter is a T LL inverter which comprises a chip U2, a U2 is 74HC04, a pin 1 of the U2 is connected with a power supply VCC through a resistor R1, a pin 2 of the U2 is connected with a pin 3 thereof, a pin 7 of the U2 is grounded, a pin 9 of the U2 is connected with a pin 10 thereof through a resistor R4, a pin 11 of the U2 is connected with a pin 12 thereof, a pin 13 of the U2 is connected with a pin 1 thereof, a pin 4 of the U2 is connected with a pin 4 of the U4, and a pin 8 of the U2 is connected with a pin 2 and a pin 3 of the U4.
Preferably, the first isolation module adopts an isolation optocoupler chip U7, the model of U7 is HCP L-0601, pin 8 of U7 is connected with power VCC1, pin 5 and pin 3 of U7 are both grounded, pin 6 of U7 is connected with power VCC1 through a resistor R12, and pin 2 of U7 is connected with pin 6 of U2 through a resistor R11.
Preferably, the second isolation module adopts an isolation optocoupler chip U6, the model of U6 is HCP L-0601, the No. 3 pin and the No. 5 pin of U6 are grounded, the No. 8 pin of U3 is connected with a power supply VCC, and the No. 6 pin of U6 is connected with the No. 1 pin and the No. 13 pin of U2.
Preferably, the second inverter adopts a TT L inverter which comprises a chip U3, a U3 with the model number 74HC04, a pin 1 of U3 is connected with a pin 12 thereof, a pin 2 of U3 is connected with a pin 4 of U5, a pin 3 of U3 is connected with a pin 8 thereof through a resistor R10, a pin 4 of U3 is connected with a pin 2 of U5, a pin 5 of U3 is connected with a pin 1 of U5, a pin 6 of U3 is connected with a pin 2 of U6 through a resistor R5, a pin 7 of U3 is grounded, a pin 9 of U3 is connected with a pin 10 thereof, a pin 11 of U3 and a pin 13 are both connected with a pin 6 of U7, and a pin 14 of U3 is connected with a power supply VCC 1.
As a preferable scheme: the second RS485 conversion module adopts a chip U5 with model number SN75176, pin 1 of U5 is connected to a power supply VCC1 through a resistor R8, pin 5 of U5 is grounded, pin 6 of U5 is connected to port 2 of the second bus interface J2, pin 7 of U5 is connected to port 3 of J2, pin 8 of U5 is connected to the power supply VCC1, pin 6 of U5 is connected to the power supply VCC1 through a resistor R3, port 1 of J2 is connected to the power supply VCC1, pin 7 of U5 is grounded through a resistor R7, and port 4 of J2 is grounded.
As a preferable scheme: the LED module also comprises a diode D1, wherein the anode of D1 is connected with the No. 9 pin of U2, and the cathode of D1 is connected with the No. 10 pin of U2.
As a preferable scheme: the LED lamp also comprises a diode D2, wherein the anode of D2 is connected with the No. 3 pin of U3, and the cathode of D2 is connected with the No. 8 pin of U3.
Compared with the prior art, the amplifier has the advantages that when the amplifier works, the first RS485 conversion module converts the differential signal into the TT L level signal, the signal processing module performs the series of inverse processing on the TT L level signal, and the second RS485 conversion module restores the TT L level signal into the differential signal, so that the amplitude of the restored two paths of signals is increased, the weakened differential signal is amplified, the difference value of the two paths of amplified signals cannot be changed from-0.2V to A-B to 0.2V, and the differential signal can be accurately judged to be 0 or 1.
Drawings
FIG. 1 is a schematic diagram of signal attenuation of an RS485 bus;
FIG. 2 is a schematic circuit diagram of an RS485 bus differential signal amplifier;
FIG. 3 is a circuit schematic of a signal processing module;
FIG. 4 is a specific circuit diagram of an RS485 bus differential signal amplifier;
FIG. 5 is a functional table of an RS485 conversion chip;
FIG. 6 is a diagram illustrating the transition between the differential signal and the TT L level signal;
FIG. 7 is a schematic diagram of the internal circuit of the inverter TT L.
Detailed Description
Referring to fig. 2, an RS485 bus differential signal amplifier includes a first bus interface, a second bus interface, a first RS485 conversion module, a second RS485 conversion module, and a signal processing module, wherein the first bus interface is connected to a differential signal port of the first RS485 conversion module, a level signal port of the first RS485 conversion module is connected to an input terminal of the signal processing module, an output terminal of the signal processing module is connected to a level signal port of the second RS485 conversion module, and the second bus interface is connected to a differential signal port of the second RS485 conversion module.
The first bus interface and the second bus interface are used for connecting the amplifier into an RS485 bus line; the first RS485 conversion module and the second RS485 conversion module are used for converting the differential signal into a level signal or converting the level signal into the differential signal; the signal processing module is used for receiving the level signal and controlling the receiving and sending states of the first RS485 conversion module and the second RS485 conversion module according to the transmission direction of the level signal.
Referring to fig. 2 and 3, the signal processing module in the present embodiment includes a first inverter, a second inverter, a first isolation module, and a second isolation module. The first inverter comprises a first inverting unit, a second inverting unit, a third inverting unit, a fourth inverting unit, a fifth inverting unit and a sixth inverting unit which are independent of each other, and the second inverter comprises a seventh inverting unit, an eighth inverting unit, a ninth inverting unit, a tenth inverting unit, an eleventh inverting unit and a twelfth inverting unit which are independent of each other.
The output end of the first inverting unit is connected with the input end of the second inverting unit, the output end of the second inverting unit is connected with the transmitting end of the first RS485 conversion module, the input end of the third inverting unit is connected with the receiving end of the first RS485 conversion module, the output end of the third inverting unit is connected with the input end of the first isolation module, the output end of the sixth inverting unit is connected with the input end of the fifth inverting unit, the output end of the fifth inverting unit is connected with the input end of the fourth inverting unit, and the output end of the fourth inverting unit is connected with the enabling end of the first RS485 conversion module.
The output end of the twelfth inverting unit is connected with the output end of the first isolating module, the output end of the twelfth inverting unit is connected with the input end of the seventh inverting unit, the output end of the seventh inverting unit is connected with the transmitting end of the second RS485 converting module, the input end of the ninth inverting unit is connected with the receiving end of the second RS485 converting module, the output end of the ninth inverting unit is connected with the input end of the second isolating module, the output end of the second isolating module is connected with the input end of the first inverting unit and the input end of the sixth inverting unit, the input end of the eleventh inverting unit is connected with the output end of the first isolating module, the output end of the eleventh inverting unit is connected with the input end of the tenth inverting unit, the output end of the tenth inverting unit is connected with the input end of the eighth inverting unit, and the output end of the eighth inverting unit is connected with the enabling end of the second RS485 converting module.
Referring to fig. 4, the first RS485 conversion module is a chip U4 with model SN75176, pin 5 of U4 is grounded, pin 6 of U4 is connected to port 2 of the first bus interface J1, pin 7 of U4 is connected to port 3 of J1, pin 8 of U4 is connected to VCC, pin 6 of U4 is connected to VCC through a resistor R2, pin 1 of J1 is connected to VCC, pin 7 of U4 is grounded through a resistor R6, port 4 of J1 is grounded, and pin 1 of U4 is connected to VCC through a resistor R9 (i.e., the aforementioned first pull-up resistor).
The first inverter is a T LL inverter, which includes a chip U2, U2 with the internal circuit of the chip 74HC04, 74HC04 as shown in fig. 7, which includes six independent inverters, just as can be used in this embodiment.
U2's pin number 1 passes through resistance R1 and connects the power VCC, U2's pin number 2 is connected with its pin number 3, U2's pin number 7 ground connection, U2's pin number 9 passes through resistance R4 and connects its pin number 10, U2's pin number 11 is connected with its pin number 12, U2's pin number 13 is connected with its pin number 1, U2's pin number 4 is connected with U4's pin number 4, U2's pin number 8 is connected with U4's pin number 2 and pin number 3.
The first isolation module adopts an isolation optocoupler chip U7, the model of U7 is HCP L-0601, the No. 8 pin of U7 is connected with the No. 5 pin and the No. 3 pin of power supplies VCC1 and U7 and are grounded, the No. 6 pin of U7 is connected with the power supply VCC1 through a resistor R12, and the No. 2 pin of U7 is connected with the No. 6 pin of U2 through a resistor R11.
The second isolation module adopts an isolation optocoupler chip U6, the model of U6 is HCP L-0601, the No. 3 pin and the No. 5 pin of U6 are grounded, and the No. 8 pin of U3 is connected with the No. 6 pin of a power supply VCC.U 6 and the No. 1 pin and the No. 13 pin of U2.
The second inverter adopts a TT L inverter, which comprises a chip U3, a U3 with the model number 74HC04, a pin 1 of U3 is connected with a pin 12 thereof, a pin 2 of U3 is connected with a pin 4 of U5, a pin 3 of U3 is connected with a pin 8 thereof through a resistor R10, a pin 4 of U3 is connected with a pin 2 of U5, a pin 5 of U3 is connected with a pin 1 of U5, a pin 6 of U3 is connected with a pin 2 of U6 through a resistor R5, a pin 7 of U3 is grounded, a pin 9 of U3 is connected with a pin 10 thereof, a pin 11 and a pin 13 of U3 are both connected with a pin 6 of U7, and a pin 14 of U3 is connected with a power supply VCC 1.
The second RS485 conversion module adopts a chip U5 with model number SN75176, pin 1 of U5 is connected to a power supply VCC1 through a resistor R8 (i.e., the aforementioned second pull-up resistor), pin 5 of U5 is grounded, pin 6 of U5 is connected to port 2 of the second bus interface J2, pin 7 of U5 is connected to port 3 of J2, pin 8 of U5 is connected to a power supply VCC1, pin 6 of U5 is connected to a power supply VCC1 through a resistor R3, port 1 of J2 is connected to a power supply VCC1, pin 7 of U5 is grounded through a resistor R7, and port 4 of J2 is grounded.
The power supply module comprises a voltage stabilizing chip U1, the model number of U1 is IB 0505L S-1W, the pin 1 of U1 is input with a DC5V power supply VCC, the pin 2 of U1 is grounded, the pin 4 of U1 is grounded, and the pin 6 of U1 is output with a DV3.3V power supply VCC 1.
Fig. 7 is a circuit diagram of the inside of the TT L inverter in the present embodiment, and the TT L inverter includes six independent sets of inverting units inside.
The problem of signal attenuation in the RS485 transmission process is solved, and amplification needs to simultaneously meet three conditions:
1. the amplifier is arranged on the bus at the attenuation position of the signal at the long-distance end, and can convert the attenuated differential signal into a TT L signal and then convert the TT L signal into an unattenuated differential signal.
2. After the amplifier is connected to the bus, both sides of the amplifier are in a receiving state in the idle state of the bus.
3. When the bus of the front end of the amplifier is 1 or 0, the bus passing through the back end of the amplifier is also 0 or 1, and the amplifier does not irradiate interference on the bus signal.
The scheme can simultaneously meet the three conditions, and the analysis and specific work are as follows:
for ease of explanation, a combination of chip number and pin number is used to replace a pin of a chip. For example, pin number 5 of the U2 chip is denoted by U2.5, and so on.
When the bus is in an idle state, that is, no signal is transmitted on the bus, since the pull-up resistor R8 makes the 5 th pin U2.5=1 of the inverter U2, U2.6=0, and U2.6 outputs a low level to U7.2, at this time, the output signal of the output pin U7.6 of the optocoupler U7 is determined to be 1 by the pull-up resistor R12, U7.6 outputs 1 to U3.11 and U3.13, and U3.13=1, and U3.12= U3.1=0, so that U3.2= U5.4=1, that is, the data transmission pin of the RS485 conversion chip U5 is always at a high level. Since U3.11=1 and U3.10= U3.9=0, U3.8= U3.3=1 and U3.4=0, U3.4=0 makes the enable terminals U5.2 and U5.3 of the RS485 conversion chip low, so that U5 is always in the receiving state, that is, the output terminal of the amplifier is in the receiving state when the bus is idle.
In the same analysis, the pull-up resistor R8 causes the inverter U3.5=1, U3.6=0, and the input of U3.6 to the optocoupler U6.2 to be at a low level, and the output U6.6 of the optocoupler U6 is determined to be 1 by the pull-up resistor R1, so that the inverter U2.1= U2.13= 1. Since U2.1=0 and U2.2= U2.3=1, U2.4= U4.4=1, i.e. the data transmission pin of the RS485 conversion chip U4 is always high. When U2.6A =1, U2.6Y = U2.5A =0, U2.5A =0, U2.5Y = U2.4A =1, and U2.4Y =0 and U2.4Y =0 make the enable terminals U4.2 and U4.3 of the RS485 conversion chip U4 low, so that the RS485 conversion chip U4 is always in a receiving state, that is, the input terminal of the amplifier is in a receiving state when the bus is idle.
Therefore, after the amplifier is connected to the bus, the two sides of the amplifier are in a receiving state in the idle state of the bus, and the requirement of bidirectional communication of the RS485 bus is met.
When the amplifier works, namely when signals exist on a bus, weak differential signals are transmitted to an RS485 conversion chip U4 through J1, the U4 converts the differential signals between A, B into TT L signals, and the TT L signals are converted into the differential signals through a series of inversions by the RS485 conversion chip U5.
When the digital signal received by the input end of the amplifier is 0, i.e. the RS485 conversion chip U4.1=0, U4.1= U2.5=0, and since U2.5=0, U2.6= U7.2=1, the output U7.6 of the high-speed optical coupler U7 is low, i.e. U7.6=0, and since U7.6=0, U7.6= U3.11= U3.13= 0. Since U3.11=0, U3.10= U3.9=1, so that U3.8= U3.3=0, U3.4=1 with U3.3=0, U3.4 connects the enable pins U5.2 and U5.3 of the RS485 converter U5, and makes U5.2= U5.3=1, the enable pin of the RS485 converter chip U5 is high, so that the chip is in a transmitting state. And U3.13=0, so that U3.12= U3.1=1, and U3.1=1 is U3.2=0, and U3.2 is connected to the data transmission pin U5.4 of the RS485 conversion chip U5, i.e., U5.4= 0. The enabling pin of the RS485 chip U5 is at high level, and the data sending pin is at low level, so that the RS485 conversion chip U5 sends out 0, namely the digital signal sent out by the output end of the amplifier is 0.
When the input end of the amplifier receives a digital signal of 1, that is, the RS485 conversion chip U4.1=1, U4.1= U2.5=1, and since U2.5=1, U2.6= U7.2=0, the output U7.6 of the high-speed optical coupler U7 is high, that is, U7.6=1, and since U7.6=1, U7.6= U3.11= U3.13= 1. Since U3.11=1, then U3.10= U3.9=0, so that U3.8= U3.3=1, U3.3=1 makes U3.4=0, U3.4 connects the enable pins U5.2 and U5.3 of the RS485 converter U5, making U5.2= U5.3= 0. As can be seen from the data manual of the RS485 conversion chip (see fig. 5), when the enable terminal of the chip is at a low level, no matter whether the data signal of the data transmission pin is 0 or 1 RS485 bus A, B is at a high impedance, since the RS485 bus a is pulled up to VCC by the resistor R3 and the bus B is pulled down to GND by the pull-down resistor R7, a-B > =0.2V, so that the signal 1 is transmitted on the bus.
Thus, the condition that the bus passing through the rear end of the amplifier is 0 or 1 when the bus of the front end of the amplifier is 0 or 1 is satisfied, and the amplifier does not disturb the bus signal.
Fig. 1 is a waveform diagram of a differential signal on an RS485 bus, and it can be known from fig. 1 that a differential signal sent from an RS485 host is attenuated after long-distance transmission, and a situation that-0.2V < a-B <0.2V may occur, and at this time, the differential signal cannot be accurately judged through a signal difference value, as shown in fig. 6, a first RS485 conversion module converts the differential signal into a TT L level signal, a signal processing module performs the aforementioned series of inverse processing on the TT L level signal, and finally a second RS485 conversion module reduces the TT L level signal into the differential signal, and amplitudes of the reduced two paths of signals become large, so that amplification of the attenuated differential signal is achieved, and a difference value of the amplified signal does not occur a situation that-0.2V < a-B <0.2V, so that it can be accurately judged whether the differential signal is 0 or 1.
The TT L inverter used in the example is 74HC04, the RS485 conversion chip is SN75176, and the high-speed optical coupler can be SP3485 or MAX485.
Referring to fig. 4, the amplifier in this embodiment further includes clamping diodes D1 and D2, where the anode of D1 is connected to pin No. 9 of U2, and the cathode of D1 is connected to pin No. 10 of U2. The positive pole of D2 is connected with pin No. 3 of U3, and the negative pole of D2 is connected with pin No. 8 of U3. The clamp diodes D1 and D2 can suppress negative interference pulses that may occur at the input terminal, and prevent the current of the emitter inside the inverter from becoming excessive when the input voltage is negative, thereby playing a role of protection.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may occur to those skilled in the art without departing from the principle of the invention, and are considered to be within the scope of the invention.
Claims (10)
1. The RS485 bus differential signal amplifier is characterized in that: including first bus interface, second bus interface, first RS485 conversion module, second RS485 conversion module and signal processing module, first bus interface is connected with the differential signal port of first RS485 conversion module, the level signal port of first RS485 conversion module is connected with signal processing module's input, signal processing module's output and second RS485 conversion module's level signal port are connected, the second bus interface is connected with the differential signal port of second RS485 conversion module, first RS485 conversion module and second RS485 conversion module are used for converting differential signal into level signal or converting level signal into differential signal, signal processing module is used for accepting level signal and controls the receiving and dispatching state of first RS485 conversion module and second RS485 conversion module according to level signal's direction of transmission.
2. The RS485 bus differential signal amplifier of claim 1, wherein: the signal processing module comprises a first pull-up resistor, a second pull-up resistor, a first inverter, a second inverter, a first isolation module and a second isolation module, wherein the first inverter comprises a first inversion unit, a second inversion unit, a third inversion unit, a fourth inversion unit, a fifth inversion unit and a sixth inversion unit which are independent of each other, the second inverter comprises a seventh inversion unit, an eighth inversion unit, a ninth inversion unit, a tenth inversion unit, an eleventh inversion unit and a twelfth inversion unit which are independent of each other, the output end of the first inversion unit is connected with the input end of the second inversion unit, the output end of the second inversion unit is connected with the transmitting end of the first RS485 conversion module, the input end of the third inversion unit is connected with the receiving end of the first RS485 conversion module, the output end of the third inversion unit is connected with the input end of the first isolation module, the first pull-up resistor is connected with the input end of the third inverter, and the output end of the sixth inversion unit is connected with the input end of the fifth, the output end of the fifth inverting unit is connected with the input end of the fourth inverting unit, the output end of the fourth inverting unit is connected with the enable end of the first RS485 conversion module, the output end of the twelfth inverting unit is connected with the output end of the first isolation module, the output end of the twelfth inverting unit is connected with the input end of the seventh inverting unit, the output end of the seventh inverting unit is connected with the transmitting end of the second RS485 conversion module, the input end of the ninth inverting unit is connected with the receiving end of the second RS485 conversion module, the output end of the ninth inverting unit is connected with the input end of the second isolation module, the second pull-up resistor is connected with the input end of the ninth inverter, the output end of the second isolation module is connected with the input end of the first inverting unit and the input end of the sixth inverting unit, and the input end of the eleventh inverting unit is connected with the output end of the first isolation module, the output end of the eleventh inverting unit is connected with the input end of the tenth inverting unit, the output end of the tenth inverting unit is connected with the input end of the eighth inverting unit, and the output end of the eighth inverting unit is connected with the enabling end of the second RS485 converting module.
3. The RS485 bus differential signal amplifier of claim 2, wherein: the first RS485 conversion module adopts a chip U4 with the model number of SN75176, pin No. 5 of U4 is grounded, pin No. 6 of U4 is connected with port No. 2 of first bus interface J1, pin No. 7 of U4 is connected with port No. 3 of J1, pin No. 8 of U4 is connected with power VCC, pin No. 6 of U4 is connected with power VCC through resistance R2, power VCC is connected with port No. 1 of J1, pin No. 7 of U4 is grounded through resistance R6, port No. 4 of J1 is grounded, pin No. 1 of U4 is connected with power VCC through resistance R9.
4. The RS485 bus differential signal amplifier as claimed in claim 3, wherein the first inverter is a T LL inverter, which includes a chip U2, U2 is 74HC04, pin 1 of U2 is connected to VCC through resistor R1, pin 2 of U2 is connected to pin 3 thereof, pin 7 of U2 is grounded, pin 9 of U2 is connected to pin 10 thereof through resistor R4, pin 11 of U2 is connected to pin 12 thereof, pin 13 of U2 is connected to pin 1 thereof, pin 4 of U2 is connected to pin 4 of U4, and pin 8 of U2 is connected to pin 2 and pin 3 of U4.
5. The RS485 bus differential signal amplifier as claimed in claim 4, wherein the first isolation module is an isolation optocoupler chip U7, the type of U7 is HCP L-0601, pin 8 of U7 is connected to VCC1, pin 5 and pin 3 of U7 are grounded, pin 6 of U7 is connected to VCC1 through resistor R12, and pin 2 of U7 is connected to pin 6 of U2 through resistor R11.
6. The RS485 bus differential signal amplifier as claimed in claim 5, wherein the second isolation module uses an isolation optocoupler chip U6, the type of U6 is HCP L-0601, pin 3 and pin 5 of U6 are grounded, pin 8 of U3 is connected to VCC, and pin 6 of U6 is connected to pin 1 and pin 13 of U2.
7. The RS485 bus differential signal amplifier as claimed in claim 6, wherein the second inverter is TT L inverter, which includes a chip U3, U3 with model 74HC04, pin 1 of U3 connected with pin 12 thereof, pin 2 of U3 connected with pin 4 of U5, pin 3 of U3 connected with pin 8 thereof through a resistor R10, pin 4 of U3 connected with pin 2 of U5, pin 5 of U3 connected with pin 1 of U5, pin 6 of U3 connected with pin 2 of U6 through a resistor R5, pin 7 of U3 grounded, pin 9 of U3 connected with pin 10 thereof, pin 11 and pin 13 of U3 both connected with pin 6 of U7, and pin 14 of U3 connected with power VCC 1.
8. The RS485 bus differential signal amplifier of claim 7, wherein: the second RS485 conversion module adopts a chip U5 with model number SN75176, pin 1 of U5 is connected to a power supply VCC1 through a resistor R8, pin 5 of U5 is grounded, pin 6 of U5 is connected to port 2 of the second bus interface J2, pin 7 of U5 is connected to port 3 of J2, pin 8 of U5 is connected to the power supply VCC1, pin 6 of U5 is connected to the power supply VCC1 through a resistor R3, port 1 of J2 is connected to the power supply VCC1, pin 7 of U5 is grounded through a resistor R7, and port 4 of J2 is grounded.
9. The RS485 bus differential signal amplifier of claim 4, wherein: the LED module also comprises a diode D1, wherein the anode of D1 is connected with the No. 9 pin of U2, and the cathode of D1 is connected with the No. 10 pin of U2.
10. The RS485 bus differential signal amplifier of claim 7, wherein: the LED lamp also comprises a diode D2, wherein the anode of D2 is connected with the No. 3 pin of U3, and the cathode of D2 is connected with the No. 8 pin of U3.
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