CN111403465A - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
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- CN111403465A CN111403465A CN202010238328.2A CN202010238328A CN111403465A CN 111403465 A CN111403465 A CN 111403465A CN 202010238328 A CN202010238328 A CN 202010238328A CN 111403465 A CN111403465 A CN 111403465A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electroluminescent Light Sources (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention discloses an array substrate, a display panel and a display device. The array substrate comprises a substrate and a driving circuit layer positioned on the substrate, wherein pixel driving circuits are arranged in the driving circuit layer, and each pixel driving circuit comprises a driving transistor and a data writing transistor; a grid signal transmission structure for transmitting electric signals on the grid of the driving transistor is arranged in the driving circuit layer, a first scanning signal line is also arranged in the driving circuit layer corresponding to a row of pixel driving circuits, and the first scanning signal line is electrically connected with the data writing transistor; the vertical projection of the first scanning signal line on the substrate is not overlapped with the vertical projection of the grid signal transmission structure on the substrate, so that the parasitic capacitance between the first scanning signal line and the grid signal transmission structure can be reduced, the light-emitting brightness difference of the grid source voltage of the driving transistor in different pixel driving circuits in the array substrate caused by the parasitic capacitance can be further reduced, and the light-emitting uniformity of the display panel is improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to an array substrate, a display panel and a display device.
Background
Because parasitic capacitance exists between a gate signal transmission structure of a driving transistor in each pixel driving circuit and a scanning signal line connected with a data writing transistor, the gate potential of the driving transistor in each pixel driving circuit is different due to the coupling effect of the parasitic capacitance, so that the uniformity ratio of the O L ED display panel is poor.
Disclosure of Invention
The invention provides an array substrate, a display panel and a display device, which aim to improve the uniformity of the display panel.
In a first aspect, an embodiment of the present invention provides an array substrate, including:
the pixel driving circuit comprises a substrate and a driving circuit layer positioned on the substrate, wherein pixel driving circuits are arranged in the driving circuit layer, and each pixel driving circuit comprises a driving transistor and a data writing transistor;
a gate signal transmission structure for transmitting an electric signal on a gate of the driving transistor is arranged in the driving circuit layer, a first scanning signal line is further arranged in the driving circuit layer corresponding to one row of the pixel driving circuits, and the first scanning signal line is electrically connected with the data writing transistor;
the vertical projection of the first scanning signal line on the substrate does not overlap with the vertical projection of the gate signal transmission structure on the substrate.
Optionally, the gate signal transmission structure is electrically connected to the gate of the driving transistor, and the gate signal transmission structure and the source and drain of the driving transistor are fabricated in the same layer.
Optionally, in a direction perpendicular to the array substrate, the pixel driving circuit further includes a metal structure located between the gate of the driving transistor and the gate signal transmission structure, a power signal line for supplying a high-level power signal to the pixel driving circuit is further disposed in the driving line layer, and the metal structure is electrically connected to the power signal line;
the metal structure covers the first region of the grid electrode of the driving transistor and exposes the second region of the grid electrode of the driving transistor, and the grid electrode signal transmission structure is electrically connected with the grid electrode of the driving transistor positioned in the second region.
Optionally, the pixel driving circuit further includes a first initialization transistor, the first initialization transistor is configured to provide a reference signal to the gate of the driving transistor, a first end of the first initialization transistor is electrically connected to the reference signal line, and a second end of the first initialization transistor is electrically connected to the gate signal transmission structure.
Optionally, the first scanning signal line and the reference signal line extend along a first direction, and the gate signal transmission structure extends along a second direction; wherein the first direction intersects the second direction;
the gate signal transmission structure is located between the first scanning signal line and the reference signal line along a direction parallel to the array substrate.
Optionally, each of the pixel driving circuits further includes at least one light emission control transistor, where the light emission control transistor is used to control on/off of a driving current branch in the pixel driving circuit;
a second scanning signal line and an enabling signal line are further arranged in the driving circuit layer corresponding to one row of the pixel driving circuits, the second scanning signal line is electrically connected with the first initialization transistor, and the enabling signal line is electrically connected with the light-emitting control transistor;
the first scanning signal line, the second scanning signal line and the enable signal line all extend along the first direction, and the first scanning signal line, the enable signal line and the second scanning signal line are sequentially arranged along the second direction.
Optionally, the driving transistor is located between the corresponding enable signal line and the first scan signal line in a direction parallel to the array substrate.
Optionally, the reference signal line is located on a side of the enable signal line away from the first scan signal line in a direction parallel to the array substrate.
In a second aspect, an embodiment of the present invention further provides a display panel, including the array substrate provided in any embodiment of the present invention, where the display panel further includes a plurality of light emitting units located on a side of the driving circuit layer away from the substrate, the pixel driving circuits are arranged in one-to-one correspondence with the light emitting units, and the pixel driving circuits are configured to provide driving currents to the corresponding light emitting units to drive the corresponding light emitting units to emit light.
In a third aspect, an embodiment of the present invention further provides a display device, including the display panel provided in the embodiment of the present invention.
According to the technical scheme of the embodiment of the invention, the grid signal transmission structure for transmitting the electric signal on the grid of the driving transistor is arranged in the driving circuit layer, the first scanning signal line is electrically connected with the data writing transistor, and the parasitic capacitance between the first scanning signal line and the grid signal transmission structure can be reduced by arranging that the vertical projection of the first scanning signal line on the substrate is not overlapped with the vertical projection of the grid signal transmission structure on the substrate. When the data writing phase is finished, the level change of the first scanning signal line is coupled to the potential change of the grid signal transmission structure through the parasitic capacitance, so that the variation of the grid source voltage of the driving transistor can be reduced, the variation of the driving current formed by the driving transistor relative to the driving current corresponding to the data voltage of the data writing phase is reduced in the light emitting phase, the light emitting brightness of the light emitting device of the pixel driving circuit in the light emitting phase is approximately equal to the light emitting brightness of the light emitting device corresponding to the data voltage written by the pixel driving circuit in the data writing phase, and the light emitting brightness difference of the grid source voltage of the driving transistor in different pixel driving circuits in the array substrate caused by the parasitic capacitance is reduced. After the array substrate forms the display panel, the light-emitting brightness difference of light-emitting devices in different pixel driving circuits in the display panel is further reduced, and the light-emitting uniformity of the display panel is improved.
Drawings
Fig. 1 is a schematic structural diagram of a conventional pixel driving circuit;
FIG. 2 is a schematic diagram of a conventional pixel driving circuit;
fig. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present invention;
fig. 5 is a schematic cross-sectional structure view of an array substrate according to an embodiment of the invention;
fig. 6 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Fig. 1 is a schematic structural diagram of a conventional pixel driving circuit. As shown in fig. 1, the pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor Cst, and a light emitting device D1. The working process of the pixel driving circuit comprises an initialization phase, a data writing phase and a light emitting phase. In the initialization stage, the first Scan signal line Scan1 receives a low level to control the first transistor T1 and the second transistor T2 to be turned on, the initialization voltage received from the initialization voltage signal line Vref is written to the gate of the seventh transistor T7 and the anode of the light emitting device D1, respectively, the gate of the seventh transistor T7 and the anode of the light emitting device D1 are initialized, and the initialization voltage received from the initialization voltage signal line Vref turns on the seventh transistor T7. In the data writing phase, the second Scan signal line Scan2 inputs a low level to control the third transistor T3 and the sixth transistor T6 to be turned on, the data voltage input by the data voltage signal line Vdata is written to the gate of the seventh transistor T7 through the third transistor T3, the seventh transistor T7 and the sixth transistor T6, and the gate writing voltage of the seventh transistor T7 is the sum of the data voltage input by the data voltage signal line Vdata and the threshold voltage of the seventh transistor T7. In the light emitting stage, the light emission control signal line E1 inputs a low level to control the fourth transistor T4 and the fifth transistor T5 to be turned on, and the fourth transistor T4, the fifth transistor T5 and the seventh transistor T7 form a driving current path to supply a driving current to the light emitting device D1, so that the light emitting device D1 emits light. Fig. 2 is a schematic structural diagram of a conventional pixel driving circuit. As shown in fig. 2, the gate of the first transistor T1 is electrically connected to the first Scan signal line Scan1, the source of the first transistor T1 is electrically connected to the first trace 101 through a via, and the first trace 101 is electrically connected to the initialization voltage signal line Vref through a via, so that the source of the first transistor T1 is electrically connected to the initialization signal line. The drain of the first transistor T1 is in contact with the second trace 102, the second trace 102 is electrically connected to the third trace 103 through a via, and the third trace 103 is electrically connected to the gate of the seventh transistor T7 through a via, so that the drain of the first transistor T1 is electrically connected to the gate of the seventh transistor T7. With continued reference to fig. 2, the third trace 103 overlaps the second Scan signal line Scan2 to form a parasitic capacitor C1. In the operation of the pixel driving circuit, at the time of entering the data writing phase, the second Scan signal line Scan2 changes from a high level to a low level, and the data voltage is written to the gate of the seventh transistor T7 through the third transistor T3, the seventh transistor T7, and the sixth transistor T6. At the end of the data writing phase, the second Scan signal line Scan2 changes from low level to high level, the voltage level of the end of the parasitic capacitor C1 on the second Scan line Scan2 is pulled high, and the voltage level of the end of the parasitic capacitor C1 on the third trace 103 is also pulled high due to the coupling effect of the parasitic capacitor C1. And the third trace 103 is electrically connected to the gate of the seventh transistor T7, so that the high potential on the third trace 103 is transmitted to the gate of the seventh transistor T7, so that the gate voltage of the seventh transistor T7 is pulled high, and thus the gate-source voltage of the seventh transistor T7 is reduced relative to the gate-source voltage during the data writing phase. The driving current provided by the seventh transistor T7 is positively correlated to the gate-source voltage of the seventh transistor T7, and when the light-emitting phase is entered, since the gate-source voltage of the seventh transistor T7 changes, the driving current formed by the seventh transistor T7 also changes with respect to the corresponding driving current when the gate-source voltage of the seventh transistor T7 does not change, so that the light-emitting luminance of the light-emitting device is different from the corresponding light-emitting luminance when the gate-source voltage of the seventh transistor T7 does not change. In the display panel, the different gate-source voltage variations of the seventh transistor T7 in different pixel driving circuits result in different driving currents output by the seventh transistor T7 in different pixel driving circuits, and further result in different light-emitting device light-emitting luminances in different pixel driving circuits in the display panel, and the light-emitting uniformity ratio of the display panel is poor.
In view of the above technical problems, an embodiment of the present invention provides an array substrate. Fig. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present invention, and fig. 4 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present invention. As shown in fig. 3 and 4, the array substrate includes a substrate 110 and a driving line layer on the substrate 110, in which pixel driving circuits are disposed, each pixel driving circuit including a driving transistor M1 and a data writing transistor M2; a gate signal transmission structure 120 for transmitting a gate power-on signal of the driving transistor M1 is arranged in the driving circuit layer, a first scanning signal line S1 is further arranged in the driving circuit layer corresponding to a row of pixel driving circuits, and the first scanning signal line S1 is electrically connected with the data writing transistor M2; the vertical projection of the first scanning signal line S1 on the substrate 110 does not overlap the vertical projection of the gate signal transfer structure 120 on the substrate 110.
Specifically, the array substrate comprises a plurality of pixel driving circuits, each pixel driving circuit corresponds to a light emitting device O L ED. in a display panel, the gate signal transmission structure 120 can be a metal signal line, the gate signal transmission structure 120 is a gate transmission signal of a driving transistor M1, in an initialization phase of the pixel driving circuit, the gate signal output structure 120 transmits an initialization signal to the gate of the driving transistor M1, so that gate initialization of the driving transistor M1 is realized, in a data writing phase of the pixel driving circuit, a first scanning signal level output by a first scanning signal line S1 changes, a data writing transistor M2 is controlled to be turned on, a data signal VDATA on the data signal line is written to the source of the driving transistor M1, when the data writing phase is ended, a first scanning signal level output by the first scanning signal line S1 changes again, a data writing transistor M2 is controlled to be turned off, when a vertical projection of the first scanning signal line S1 on the substrate 110 and a vertical projection of the gate signal transmission structure 120 on the substrate 110 do not overlap, a vertical projection of the gate signal transmission structure 120 on the substrate 110, a parasitic voltage of the first scanning signal line S462 and a gate signal transmission structure 120 change, so that a gate signal level of the gate signal transmission voltage of the gate signal transmission structure is reduced, and a parasitic voltage of the gate signal transmission transistor M1 is reduced, so that a parasitic voltage of the gate signal transmission transistor M1 is reduced, and a pixel driving transistor M1 in the pixel driving circuit, so that a parasitic voltage of the driving circuit is reduced in the driving circuit, and a pixel driving circuit, so that a pixel driving circuit is reduced in a pixel driving circuit, and a pixel driving circuit is reduced in a pixel driving circuit, so that a pixel driving circuit, a pixel driving circuit is formed in a pixel driving circuit, a pixel driving circuit with.
Fig. 5 is a schematic cross-sectional structure diagram of an array substrate according to an embodiment of the invention. Referring to fig. 3 to 5, the gate signal transmission structure 120 is electrically connected to the gate G1 of the driving transistor M1, and the gate signal transmission structure 120 and the source/drain SD1 of the driving transistor M1 are fabricated at the same layer.
Specifically, the gate signal transmission structure 120 may be fabricated on the same layer as the source/drain SD1 of the driving transistor M1, so that a process flow of a mask may be omitted during the fabrication of the array substrate, and the array substrate is light and thin. When the gate signal transmission structure 120 and the source drain SD1 of the driving transistor M1 are fabricated in the same layer, the gate signal transmission structure 120 and the gate G1 of the driving transistor M1 are in different layers, so that the gate signal transmission structure 120 and the gate G1 of the driving transistor M1 can be electrically connected through a via hole.
With continuing reference to fig. 3 to 5, in a direction perpendicular to the array substrate, the pixel driving circuit further includes a metal structure 130 located between the gate of the driving transistor M1 and the gate signal transmission structure 120, a power signal line VDD for providing a high-level power signal to the pixel driving circuit is further disposed in the driving line layer, and the metal structure 130 is electrically connected to the power signal line VDD; the metal structure 130 covers the first region 131 of the gate of the driving transistor M1 and exposes the second region 132 of the gate of the driving transistor M1, and the gate signal transmission structure 120 is electrically connected to the gate of the driving transistor M1 in the second region 132.
Specifically, an orthogonal projection of the metal structure 130 in the direction perpendicular to the array substrate has an overlap with an orthogonal projection of the gate of the driving transistor M1 in the direction perpendicular to the array substrate, and a capacitance Cd may be formed as a storage capacitance in the pixel driving circuit. The metal structure 130 is electrically connected to the power signal line VDD, and one end of the storage capacitor can be connected to the power signal line VDD.
In addition, the gate signal transmission structure 120 is disposed on the same layer as the source/drain SD1 of the driving transistor M1, so that the gate signal transmission structure 120 is disposed on a side of the gate G1 of the driving transistor M1 away from the substrate 110. When the metal structure 130 is disposed between the gate G1 of the driving transistor M1 and the gate signal transmission structure 120, the gate signal transmission structure 120 needs to be electrically connected to the gate of the driving transistor M1 through the metal structure 130. Therefore, when the metal structure 130 is formed, the metal structure 130 can be directly formed to cover the first region 131 of the driving transistor M1 and expose the second region 132 of the gate of the driving transistor M1, and the gate signal transmission structure 120 is electrically connected to the gate of the driving transistor M1 located in the second region 132, so that the process flow of drilling the metal structure 130 is reduced.
It should be noted that, between different metal layers, an insulating layer 140 is further included to avoid short circuit between adjacent metal layers. For example, an interlayer insulating layer is present between the layer where the gate signal transmitting structure 120 is located and the layer where the metal structure 130 is located, and a gate insulating layer is present between the metal structure 130 and the layer where the gate of the driving transistor M1 is located.
With continued reference to fig. 3 to 5, the pixel driving circuit further includes a first initialization transistor M3, the first initialization transistor M3 is configured to provide a reference signal to the gate of the driving transistor M1, a first terminal of the first initialization transistor M3 is electrically connected to the reference signal line Vf, and a second terminal of the first initialization transistor M3 is electrically connected to the gate signal transmission structure 120.
Specifically, as shown in fig. 3 to 5, the pixel driving circuit further includes a reference signal line Vf. The layer where the reference signal line Vf is located may be disposed between the layer where the gate G1 of the driving transistor M1 is located and the layer where the gate signal transmitting structure 120 is located. The reference signal line Vf is electrically connected to the first end of the first initialization transistor M3 through a partial trace of the film where the gate signal transmission structure 120 is located, and the second end of the first initialization transistor M3 is electrically connected to the gate signal transmission structure 120 through a via hole, so that the reference voltage on the reference signal line Vf can be transmitted to the gate of the driving transistor M1 through the first initialization transistor M3 and the gate signal transmission structure 120.
With continued reference to fig. 3 and 4, the first scan signal line S1 and the reference signal line Vf extend in the first direction X, and the gate signal transfer structure 120 extends in the second direction Y; wherein the first direction X intersects the second direction Y; the gate signal transmitting structure 120 is located between the first scan signal line S1 and the reference signal line Vf along a direction parallel to the array substrate.
Specifically, the first scan signal line S1 may be disposed at the same layer as the gate of the driving transistor M1, and the reference signal line Vf may be disposed at a different layer from the first scan signal line S1. The orthographic projections of the first scanning signal line S1 and the reference signal line Vf in the direction perpendicular to the substrate 110 are as little as possible overlapped, thereby reducing the parasitic capacitance between the first scanning signal line S1 and the reference signal line Vf. In addition, the gate signal transmitting structure 120 is located between the first scan signal line S1 and the reference signal line Vf, and extends along the second direction Y, so as to facilitate transmission of the reference signal output by the reference signal line Vf to the gate of the driving transistor M1.
With continued reference to fig. 3 and 4, each pixel driving circuit further includes at least one light emission control transistor for controlling on/off of a driving current branch in the pixel driving circuit; a second scanning signal line S2 and an enabling signal line EM are further arranged in the driving circuit layer corresponding to one row of pixel driving circuits, the second scanning signal line S2 is electrically connected with the first initialization transistor M3, and the enabling signal line EM is electrically connected with the light-emitting control transistor; the first scanning signal line S1, the second scanning signal line S2, and the enable signal line EM each extend in the first direction X, and the first scanning signal line S1, the enable signal line EM, and the second scanning signal line S2 are arranged in this order in the second direction Y.
Specifically, as shown in fig. 3 and 4, the pixel driving circuit includes two light emission control transistors, namely a first light emission control transistor M4 and a second light emission control transistor M5., a source of the first light emission control transistor M4 is electrically connected to the power signal line VDD through a via hole, and a drain of the first light emission control transistor M4 is electrically connected to a source of the driving transistor M1, a source of the second light emission control transistor M5 is electrically connected to a drain of the driving transistor M1, and a drain of the second light emission control transistor M5 is electrically connected to an anode (not shown in fig. 3) of the light emitting device O L ED, and the enable signal line EM controls on or off of the first light emission control transistor M4 and the second light emission control transistor M5, thereby controlling on/off of the driving current branch in the pixel driving circuit.
In addition, the first scan signal line S1, the second scan signal line S2, and the enable signal line EM all extend in the first direction X, the first scan signal line S1, the enable signal line EM, and the second scan signal line S2 are sequentially arranged in the second direction Y, and the gate signal transmission structure 120 is located between the first scan signal line S1 and the reference signal line Vf, so that a vertical projection of the first scan signal line S1 on the substrate 110 may not overlap a vertical projection of the gate signal transmission structure 120 on the substrate 110, and a parasitic capacitance between the first scan signal line S1 and the gate signal transmission structure 120 is small. Meanwhile, a region between the reference signal line Vf and the second scan signal line S2, and between adjacent data signal lines VDATA includes one pixel driving circuit.
With continued reference to fig. 3 and 4, the pixel driving circuit may further include a compensation transistor M6, a source of the compensation transistor M6 is electrically connected to the gate of the driving transistor M1, and a drain of the compensation transistor M6 is electrically connected to a drain of the driving transistor M1. in the data writing phase, the first scan signal line S1 controls the compensation transistor M6 to be turned on, the data voltage inputted from the data signal line VDATA is written to the gate of the driving transistor M1 through the data writing transistor M2, the driving transistor M1 and the compensation transistor M6. in addition, the pixel driving circuit may further include a second initialization transistor M7, a source of the second initialization transistor M7 is electrically connected to the reference signal line Vf, a drain of the second initialization transistor M7 may be electrically connected to an anode (not shown in fig. 3) of the light emitting device O L ED, and the first initialization transistor M3 initializes the gate of the driving transistor M465 while initializing the second initialization transistor M L initializes the gate of the light emitting device M L.
With continued reference to fig. 3 and 4, the driving transistor M1 is positioned between the corresponding enable signal line EM and the first scan signal line S1 in a direction parallel to the array substrate.
Specifically, in one pixel driving circuit, the driving transistor M1 is disposed between the enable signal line EM and the first scan signal line S1, and the first emission control transistor M4, the second emission control transistor M5, the data writing transistor M2 and the compensation transistor M6 can be disposed around the driving transistor M1, so that the pixel driving circuit has a simple layout and a compact structure, and is advantageous for reducing the area of the substrate 110 occupied by the pixel driving circuit.
With continued reference to fig. 3 and 4, the reference signal line Vf is located at a side of the enable signal line EM away from the first scan signal line S1 in a direction parallel to the array substrate.
Specifically, when the reference signal line Vf is located at a side of the enable signal line EM away from the first scan signal line S1, the first initialization transistor M3 and other transistors in the pixel driving circuit are more compact, which is beneficial to the layout of the pixel driving circuit.
In addition, when the reference signal line Vf is located at a side of the enable signal line EM away from the first scan signal line S1, an orthogonal projection of the gate signal transmitting structure 120 on the substrate 110 overlaps an orthogonal projection of the enable signal line EM on the substrate 110, forming a parasitic capacitance. When the data writing phase of the pixel driving circuit is finished, the potential of the enable signal line EM does not change, that is, the potential of one end of the parasitic capacitor on the enable signal line EM does not change, and the potential of one end of the parasitic capacitor on the gate signal transmission structure 120 does not change, so that the change of the gate-source voltage of the driving transistor M1 is avoided, and the light emitting uniformity of the display panel is ensured.
The embodiment of the invention also provides a display panel. Fig. 6 is a schematic structural diagram of a display panel according to an embodiment of the present invention. As shown in fig. 6, the display panel 10 includes an array substrate 11 according to any embodiment of the present invention. The display panel 10 further includes a plurality of light emitting units 12 located on a side of the driving circuit layer away from the substrate, and the pixel driving circuits are disposed in one-to-one correspondence with the light emitting units 12, and are configured to provide driving currents to the corresponding light emitting units 12 to drive the corresponding light emitting units 12 to emit light.
Specifically, the display panel 10 includes the array substrate 11 provided in any embodiment of the present invention, and therefore has the same beneficial effects as the array substrate provided in any embodiment of the present invention, and the details are not repeated herein. The display panel can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame and the like.
Fig. 7 is a schematic structural diagram of a display device according to an embodiment of the present invention. As shown in fig. 7, the display device 20 includes a display panel 21 provided in any embodiment of the present invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. An array substrate, comprising:
the pixel driving circuit comprises a substrate and a driving circuit layer positioned on the substrate, wherein pixel driving circuits are arranged in the driving circuit layer, and each pixel driving circuit comprises a driving transistor and a data writing transistor;
a gate signal transmission structure for transmitting an electric signal on a gate of the driving transistor is arranged in the driving circuit layer, a first scanning signal line is further arranged in the driving circuit layer corresponding to one row of the pixel driving circuits, and the first scanning signal line is electrically connected with the data writing transistor;
the vertical projection of the first scanning signal line on the substrate does not overlap with the vertical projection of the gate signal transmission structure on the substrate.
2. The array substrate of claim 1, wherein the gate signal transmission structure is electrically connected to the gate of the driving transistor, and the gate signal transmission structure and the source and drain of the driving transistor are fabricated in the same layer.
3. The array substrate of claim 2, wherein the pixel driving circuit further comprises a metal structure between the gate of the driving transistor and the gate signal transmission structure in a direction perpendicular to the array substrate, wherein a power signal line for supplying a high-level power signal to the pixel driving circuit is further disposed in the driving line layer, and the metal structure is electrically connected to the power signal line;
the metal structure covers the first region of the grid electrode of the driving transistor and exposes the second region of the grid electrode of the driving transistor, and the grid electrode signal transmission structure is electrically connected with the grid electrode of the driving transistor positioned in the second region.
4. The array substrate of claim 2, wherein the pixel driving circuit further comprises a first initialization transistor, the first initialization transistor is configured to provide a reference signal to the gate of the driving transistor, a first terminal of the first initialization transistor is electrically connected to the reference signal line, and a second terminal of the first initialization transistor is electrically connected to the gate signal transmission structure.
5. The array substrate of claim 4, wherein the first scan signal line and the reference signal line extend in a first direction, and the gate signal transmission structure extends in a second direction; wherein the first direction intersects the second direction;
the gate signal transmission structure is located between the first scanning signal line and the reference signal line along a direction parallel to the array substrate.
6. The array substrate of claim 5, wherein each of the pixel driving circuits further comprises at least one emission control transistor for controlling on/off of a driving current branch in the pixel driving circuit;
a second scanning signal line and an enabling signal line are further arranged in the driving circuit layer corresponding to one row of the pixel driving circuits, the second scanning signal line is electrically connected with the first initialization transistor, and the enabling signal line is electrically connected with the light-emitting control transistor;
the first scanning signal line, the second scanning signal line and the enable signal line all extend along the first direction, and the first scanning signal line, the enable signal line and the second scanning signal line are sequentially arranged along the second direction.
7. The array substrate of claim 6, wherein the driving transistor is located between the corresponding enable signal line and the first scan signal line in a direction parallel to the array substrate.
8. The array substrate of claim 6 or 7, wherein the reference signal line is located on a side of the enable signal line away from the first scan signal line in a direction parallel to the array substrate.
9. A display panel, comprising the array substrate according to any one of claims 1 to 8, wherein the display panel further comprises a plurality of light emitting units located on a side of the driving circuit layer away from the substrate, the pixel driving circuits are disposed in one-to-one correspondence with the light emitting units, and the pixel driving circuits are configured to provide driving currents to the corresponding light emitting units to drive the corresponding light emitting units to emit light.
10. A display device characterized by comprising the display panel according to claim 9.
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