CN111403406B - Three-dimensional memory and preparation method thereof - Google Patents
Three-dimensional memory and preparation method thereof Download PDFInfo
- Publication number
- CN111403406B CN111403406B CN202010175101.8A CN202010175101A CN111403406B CN 111403406 B CN111403406 B CN 111403406B CN 202010175101 A CN202010175101 A CN 202010175101A CN 111403406 B CN111403406 B CN 111403406B
- Authority
- CN
- China
- Prior art keywords
- area
- core
- region
- sub
- line gap
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The invention provides a three-dimensional memory and a preparation method thereof, and belongs to the field of semiconductor memory design and manufacture. The first storage area of the three-dimensional memory comprises a first core area and a first step area, the second storage area comprises a second core area and a second step area, the first core area and the second core area are adjacently arranged along a first direction and are mutually isolated, the first step area and the second step area are adjacently arranged along a second direction and are mutually isolated, and the first step area is provided with a first step widening part extending to the inside of the second core area along the first direction; the second step region has a second step widening portion extending reversely to the inside of the first core region in the first direction. According to the invention, through novel grid line Gap (GLS) design, the step area of the block storage area is provided with the step widening part extending into the core area of the adjacent block storage area, so that the width of the step area of the single block storage area is increased, the increase of the partition number is facilitated, and the design difficulty of a memory architecture can be reduced.
Description
Technical Field
The invention belongs to the field of semiconductor memory design and manufacture, and particularly relates to a three-dimensional memory and a preparation method thereof.
Background
With the development of planar flash memories, the production process of semiconductors has made tremendous progress. But in recent years, the development of planar flash memory has met with various challenges: physical limits, current development technology limits, stored electron density limits, and the like. In this context, to address the difficulties encountered with planar flash memories and the pursuit of lower unit memory cell manufacturing costs, three-dimensional memory structures have evolved that can enable each memory die in a memory device to have a greater number of memory cells.
In non-volatile memories, such as NAND memories, one way to increase memory density is by using vertical memory arrays, i.e. 3D NAND memories, whereas CTF (Charge Trap Flash ) type 3D NAND memories are currently more advanced and very promising memory technologies.
A 3D NAND memory will typically include one or more chip (plane) memory areas. Symmetrical connection regions for the extraction gates are usually provided on both sides of the chip memory region. Typically, the attachment region has a stepped (pair-Step) shape. The slice memory area and the linking area are typically divided into a plurality of blocks to form a plurality of Block memory areas (blocks).
In the existing 3D NAND memory, the area occupied by the step area of each block of memory area is only one block of memory area, so that the architecture design of steps is limited.
Disclosure of Invention
In view of the above-described drawbacks of the prior art, an object of the present invention is to provide a three-dimensional memory and a method for manufacturing the same for solving the problem of the step area of the block memory area in the prior art.
To achieve the above and other related objects, the present invention provides a three-dimensional memory including a first block memory area including a first core area and a first step area located in the middle of the first core area, and a second block memory area including a second core area and a second step area located in the middle of the second core area, the first core area and the second core area being adjacently arranged in a first direction and being isolated from each other, the first step area and the second step area being adjacently arranged in a second direction and being isolated from each other, wherein the first step area has a first step widening portion extending into the second core area in the first direction, the first step widening portion being isolated from the second core area by a first gate line gap; the second step region has a second step widening portion extending in a first direction reversely into the first core region, the second step widening portion being isolated from the first core region by a second gate line gap.
Optionally, the first core area includes a first sub-core area and a second sub-core area located at two ends of the first step area and the second step area, the first sub-core area is connected with the first step area, the second core area includes a third sub-core area and a fourth sub-core area located at two ends of the first step area and the second step area, and the fourth sub-core area is connected with the second step area; the first storage area further comprises a first bridging wall which is simultaneously positioned on one side of the first step area, which is far away from the first step widening part, and one side of the second step area, which is close to the second step widening part, wherein the first bridging wall is connected with the first step area, the first sub-core area and the second sub-core area, the second storage area further comprises a second bridging wall which is simultaneously positioned on one side of the first step area, which is close to the first step widening part, and one side of the second step area, which is far away from the second step widening part, and the second bridging wall is connected with the second step area, the third sub-core area and the fourth sub-core area.
Optionally, the first sub-core area and the third sub-core area are isolated by a first inter-block gate line gap, the first inter-block gate line gap is connected with the first gate line gap, the second sub-core area and the fourth sub-core area are isolated by a second inter-block gate line gap, and the second inter-block gate line gap is connected with the second gate line gap.
Optionally, the first step widening part extends to be adjacent to the second bridging wall and is isolated from the second bridging wall by a third gate line gap, the first gate line gap is connected with the third gate line gap, the second step widening part extends to be adjacent to the first bridging wall and is isolated from the first bridging wall by a fourth gate line gap, and the fourth gate line gap is connected with the second gate line gap.
Optionally, the first core area and the second core area each include a plurality of finger storage areas, and each finger storage area is isolated by an inter-finger gate line gap.
Optionally, the width of the first step widening portion extending to the inside of the second core region is an integer multiple of the width of the finger storage region.
Optionally, the width of the first bridging wall and the second bridging wall is between the width of 0.5 finger storage areas and the width of 2 finger storage areas.
Optionally, steps of the first step region and the second step region decrease in sequence from the respective corresponding core regions toward the isolation belt between the first step region and the second step region, and are cut off at the isolation belt.
Optionally, the first direction and the second direction are perpendicular to each other.
Optionally, the first core region and the second core region include a stack structure and a channel storage structure array penetrating the stack structure, and the channel storage structure includes a channel hole penetrating the stack structure and a memory film and a channel layer located in the channel hole.
The invention also provides a preparation method of the three-dimensional memory, which comprises the following steps: providing a substrate, and forming a stacking structure on the substrate; forming a first block storage area and a second block storage area in the stacked structure, wherein the first block storage area comprises a first core area and a first step area positioned in the middle of the first core area, the second block storage area comprises a second core area and a second step area positioned in the middle of the second core area, the first core area and the second core area are adjacently arranged along a first direction and are mutually isolated, the first step area and the second step area are adjacently arranged along a second direction and are mutually isolated, the first step area is provided with a first step widening part extending to the inside of the second core area along the first direction, and the first step widening part is isolated from the second core area through a first grid line gap; the second step region has a second step widening portion extending in a first direction reversely into the first core region, the second step widening portion being isolated from the first core region by a second gate line gap.
Optionally, the first core area includes a first sub-core area and a second sub-core area located at two ends of the first step area and the second step area, the first sub-core area is connected with the first step area, the second core area includes a third sub-core area and a fourth sub-core area located at two ends of the first step area and the second step area, and the fourth sub-core area is connected with the second step area; the first storage area further comprises a first bridging wall which is simultaneously positioned on one side of the first step area, which is far away from the first step widening part, and one side of the second step area, which is close to the second step widening part, wherein the first bridging wall is connected with the first step area, the first sub-core area and the second sub-core area, the second storage area further comprises a second bridging wall which is simultaneously positioned on one side of the first step area, which is close to the first step widening part, and one side of the second step area, which is far away from the second step widening part, and the second bridging wall is connected with the second step area, the third sub-core area and the fourth sub-core area.
Optionally, the first sub-core area and the third sub-core area are isolated by a first inter-block gate line gap, the first inter-block gate line gap is connected with the first gate line gap, the second sub-core area and the fourth sub-core area are isolated by a second inter-block gate line gap, and the second inter-block gate line gap is connected with the second gate line gap.
Optionally, the first step widening part extends to be adjacent to the second bridging wall and is isolated from the second bridging wall by a third gate line gap, the first gate line gap is connected with the third gate line gap, the second step widening part extends to be adjacent to the first bridging wall and is isolated from the first bridging wall by a fourth gate line gap, and the fourth gate line gap is connected with the second gate line gap.
Optionally, the first core area and the second core area each include a plurality of finger storage areas, each finger storage area is isolated by an inter-finger gate line gap, the width of the first step widening part extending to the inside of the second core area is an integer multiple of the width of the finger storage area, the width of the first bridging wall is between 0.5 of the width of the finger storage area and 2 of the width of the finger storage area, and the width of the second bridging wall is between 0.5 of the width of the finger storage area and 2 of the width of the finger storage area.
Optionally, steps of the first step region and the second step region decrease in sequence from the respective corresponding core regions toward the isolation belt between the first step region and the second step region, and are cut off at the isolation belt.
As described above, the three-dimensional memory and the method for manufacturing the same of the present invention have the following advantageous effects:
the invention achieves an increase in the width of the stepped region of a single block storage region in a first direction (e.g., the Y direction) by a novel gate line Gap (GLS) design such that the stepped region of the block storage region has a step widening that extends into the core region of an adjacent block storage region.
The width of the step area of the single block storage area in the Y direction is increased, the increase of the number of the partitions is facilitated, meanwhile, the bridge wall has larger design width, and the area of the step contact area can be reduced due to the increase of the width of the bridge wall, so that the design difficulty of the framework of the three-dimensional memory is reduced.
Drawings
Fig. 1 is a schematic layout structure of a three-dimensional memory.
Fig. 2 is a schematic diagram of a three-dimensional memory according to the present invention.
Fig. 3 is a schematic diagram of a layout structure of the three-dimensional memory according to the present invention.
Fig. 4 is a schematic diagram showing another layout structure of the three-dimensional memory according to the present invention.
Description of element reference numerals
11. 12 storage areas
111. Core area
112. Step area
113. Bridging wall
21. First block storage area
211. First sub-core region
212. Second sub-core region
213. A first step region
214. First step widening part
215. First bridging wall
22. A second block storage area
221. Third sub-core region
222. Fourth sub-core region
223. A second step region
224. Second step widening part
225. Second bridging wall
241. First grid line gap
242. First inter-block gate line gap
243. Second inter-block gate line gap
244. Third grid line gap
245. Second grid line gap
246. Fourth gate line gap
247. Isolation belt
248. Inter-finger gate line gap
23. Finger storage area
31. A third storage area
32. Fourth block storage area
41. 42, 43, 44 block memory area
414. First step widening part
424. Second step widening part
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
As described in detail in the embodiments of the present invention, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present.
In the context of this application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Fig. 1 is a schematic diagram of a three-dimensional memory (3D NAND) structure, which includes a plurality of block memory areas 11, 12, each block memory area includes a core area 111 and a step area 112, the step area 112 is disposed in the middle of the core area 111, and the step area 112 is matched with a bridge wall 113, so that the step area 112 is simultaneously connected to the core areas 111 at both ends thereof. In the three-dimensional memory, the area occupied by the step area of each block of memory area is only an area of one block of memory area, for example, one block of memory area of the three-dimensional memory comprises 3 finger memory areas, the width of the step area can only be designed to be not more than the width of 3 finger memory areas, and the bridge wall also needs to occupy a finger memory area with a certain width, so that the width of the step area in the Y direction is limited, and the structural design of steps and the design of the bridge wall are limited.
The present invention provides a three-dimensional memory, which enables an increase in the width of a step region of a single block storage region in a first direction (e.g., Y direction) by a novel gate line Gap (GLS) design such that the step region of the block storage region has a step widening portion extending into a core region of an adjacent block storage region.
As shown in fig. 2 to 3, the present embodiment provides a three-dimensional memory including a plurality of Block memory areas (blocks), for example, as shown in fig. 3, the three-dimensional memory may include a first Block memory area 21, a second Block memory area 22, a third Block memory area, and a fourth Block memory area, and of course, in an actual device design, the three-dimensional memory may include more Block memory areas, such as 8 Block memory areas, 16 Block memory areas, or more, and is not limited to the examples shown in the drawings herein.
For more convenience in describing in detail, in this embodiment, taking two block storage areas as an example, as shown in fig. 2, the three-dimensional memory includes a first block storage area 21 and a second block storage area 22, the first block storage area 21 and the second block storage area 22 are isolated from each other, the first block storage area 21 includes a first core area and a first step area 213 located in the middle of the first core area, the second block storage area includes a second core area and a second step area 223 located in the middle of the second core area, the first core area and the second core area are adjacently arranged along a first direction and are isolated from each other, the first step area 213 and the second step area 223 are adjacently arranged along a second direction and are isolated from each other, wherein the first step area 213 has a first step widening 214 extending into the second core area along the first direction, and the first widening 214 is isolated from the second core area by a first gate line gap 241; the second step region 223 has a second step widening portion 224 extending reversely into the first core region along the first direction, the second step widening portion 224 is isolated from the first core region by a second gate line gap 245, specifically, as shown in fig. 2, the first step widening portion 214 and the second step widening portion 224 are arranged in a staggered manner. The first direction and the second direction are preferably perpendicular to each other, for example, as shown in fig. 2, the first direction may be selected as a Y direction, and the second direction may be selected as an X direction.
As shown in fig. 2, the first core region includes a first sub-core region 211 and a second sub-core region 212 located at two ends of the first step region 213 and the second step region 223, the first sub-core region 211 is connected to the first step region 213, the second core region includes a third sub-core region 221 and a fourth sub-core region 222 located at two ends of the first step region 213 and the second step region 223, and the fourth sub-core region is connected to the second step region 223; the first block storage area 21 further includes a first bridge wall 215 located on a side of the first step area 213 away from the first step widening portion 214, and on a side of the second step area 223 close to the second step widening portion 224, the first bridge wall 215 connects the first step area 213, the first sub-core area 211 and the second sub-core area 212, the second block storage area 22 further includes a second bridge wall 225 located on a side of the first step area 213 close to the first step widening portion 214, and on a side of the second step area 223 away from the second step widening portion 224, and the second bridge wall 225 connects the second step area 223, the third sub-core area 221 and the fourth sub-core area 222. Of course, the layout of the first sub-core region 211, the second sub-core region 212, the third sub-core region 221, the fourth sub-core region 222, the first step region 213 and the second step region 223 is not limited to the above-listed examples, and for example, the first step region 213 may be connected to the second sub-core region 212, and may be connected to the first sub-core region 211 through the first bridge wall 215, and similarly, the second step region 223 may be connected to the third sub-core region 221, and may be connected to the third sub-core region through the second bridge wall 225, and the structure thereof may be schematically shown with reference to the structures of the third storage region and the fourth storage region in fig. 3.
As shown in fig. 2, the first sub-core region 211 and the third sub-core region 221 are separated by a first inter-block gate line gap 242, the first inter-block gate line gap 242 is connected to the first gate line gap 241, the second sub-core region 212 and the fourth sub-core region 222 are separated by a second inter-block gate line gap 243, and the second inter-block gate line gap 243 is connected to the second gate line gap 245.
As shown in fig. 2, the first step widening portion 214 extends to be adjacent to the second bridging wall 225 and is isolated from the second bridging wall 225 by a third gate line gap 244, the first gate line gap 241 is connected to the third gate line gap 244, the second step widening portion 224 extends to be adjacent to the first bridging wall 215 and is isolated from the first bridging wall 215 by a fourth gate line gap 246, and the fourth gate line gap 246 is connected to the second gate line gap 245.
As shown in fig. 2, the steps of the first step region 213 and the second step region 223 are sequentially lowered from the core regions corresponding to the steps toward the isolation strips 247 between the first step region 213 and the second step region 223, and the isolation strips 247 are cut, for example, after the steps are sequentially lowered, the substrate surface below the step regions is exposed at the isolation strips 247, so that the cut isolation of the first step region 213 and the second step region 223 is realized.
Specifically, as shown in fig. 2, for the first block storage area 21 and the second block storage area 22, the main isolation structure of the present embodiment includes a first inter-block gate line gap 242, a first gate line gap 241, a third gate line gap 244, an isolation belt 247, a fourth gate line gap 246, a second gate line gap 245, and a second inter-block gate line gap 243 that are sequentially connected, where the first inter-block gate line gap 242 extends along a second direction (X direction) for isolating the first sub-core area 211 and the third sub-core area 221, the first gate line gap 241 extends along a first direction (Y direction) for isolating the first step area 213 from the third sub-core area 221, the third gate line gap 244 extends along a second direction (X direction) for isolating the first step area 213 from the second bridging wall 225, the isolation belt 247 extends along a first direction (Y direction) for isolating the first step area 213 from the second sub-core area 211, the second step area 246 extends along a second direction (Y direction) from the second gate line 223 from the second bridging wall 223, and the second sub-core area 212 extends along a second direction (Y direction) from the second step area 223 to the second bridging wall 223. According to the invention, through novel grid line Gap (GLS) design, the step area of the block storage area is provided with the step widening part extending into the core area of the adjacent block storage area, so that the step area width of the single block storage area in the first direction (for example, Y direction) is increased, the increase of the partition number is facilitated, and the design difficulty of the framework of the three-dimensional memory is reduced. The gate gap may be filled with only an insulating layer, or an array common source (Array Common Source, ACS) may be provided in the gate gap to provide a common source for the memory array. An insulating layer may be disposed between the array common source and the gate line gap sidewall.
The first core region and the second core region each include a plurality of finger storage regions 23, and each finger storage region 23 is isolated by an inter-finger gate line gap 248, at this time, in order to more effectively use the device region, the width of the first step widening portion 214 extending into the second core region is an integer multiple of the width of the finger storage region 23. In addition, due to the widening of the entire stepped region, the width of the first bridging wall 215 of the present embodiment may be designed to be between 0.5 and 2 of the finger storage regions 23, and the width of the second bridging wall 225 may be designed to be between 0.5 and 2 of the finger storage regions 23. The width of the step area of the single block storage area in the Y direction is increased, so that the bridge wall has larger design width, and the area of the step contact area can be reduced by increasing the width of the bridge wall, thereby reducing the design difficulty of the framework of the three-dimensional memory.
In a specific embodiment, as shown in fig. 2, the first core area and the second core area each include 3 finger storage areas 23, including bridge walls, the first step area 213 and the second step area 223 extend into adjacent core areas in addition to occupying the widths of the 3 finger storage areas 23 of the corresponding core areas, and occupy the widths of 2 finger storage areas 23 additionally, that is, the first step widening portion 214 and the second step widening portion 224 have the widths of 2 finger storage areas 23, and the area occupied by each of the first step area 213 and the second step area 223 is the width of 5 finger storage areas 23, where each of the first bridge wall 215 and the second bridge wall 225 occupies the width of one finger storage area 23.
In another specific embodiment, as shown in fig. 4, the three-dimensional memory includes 4 block memory areas 41, 42, 43, 44, each core area includes 2 finger memory areas, including bridge walls, the first step area 213 and the second step area 223 extend into adjacent core areas in addition to occupying the widths of 2 finger memory areas of the corresponding core areas, and occupy the widths of 1 finger memory area additionally, that is, the first step widening portion 414 and the second step widening portion 424 have the widths of 1 finger memory area, and the area occupied by each of the first step area 213 and the second step area 223 is the width of 3 finger memory areas, wherein the first bridge wall 215 and the second bridge wall 225 occupy the width of one finger memory area.
According to the idea of the present invention, the three-dimensional memory can be applied to a scene in which 1 block memory area includes only 1 finger memory area, or a scene in which 1 block memory area includes 4 or more finger memory areas, not limited to the above-listed examples.
In this embodiment, the three-dimensional memory may be a 3D NAND memory, wherein the first core region and the second core region include a stacked structure on a substrate and a channel memory structure array penetrating through the stacked structure, and the channel memory structure includes a channel hole penetrating through the stacked structure and a memory film and a channel layer located in the channel hole.
In the present embodiment, the substrate is typically a silicon-containing substrate such as Si, SOI (silicon on insulator), siGe, siC, or the like, but is not limited to the above-exemplified examples. Peripheral devices such as field effect transistors, capacitors, inductors, and/or diodes may be provided on the substrate as desired, and may be used as various functional devices of the memory device such as buffers, amplifiers, decoders, etc. The stacked structure comprises a stack of sacrificial dielectric layers and gate dielectric layers, for example, the stacked structure comprises alternately stacked silicon nitride layers and silicon oxide layers. The sacrificial dielectric layer is removed in a subsequent process and replaced with a gate layer at a corresponding location, which may be a material such as polysilicon, copper, aluminum, tungsten, titanium nitride, tantalum nitride, etc., but is not limited to the examples listed herein.
In this embodiment, the memory film includes a blocking layer, a charge trapping layer and a tunneling layer, where the blocking layer is located on a surface of a sidewall of the channel hole, the charge trapping layer is located on a surface of the blocking layer, and the tunneling layer is located on a surface of the charge trapping layer. For example, the material of the blocking layer may be silicon dioxide, the material of the charge trapping layer may be silicon nitride, and the material of the tunneling layer may be silicon dioxide. An exemplary material for the channel layer is polysilicon. It will be appreciated that other materials may be selected for these layers. For example, the material of the barrier layer may include a high-K oxide layer; the material of the channel layer may include semiconductor materials such as monocrystalline silicon, monocrystalline germanium, siGe, siC, siGeC, siGeH, and the like.
As shown in fig. 2 and 3, the present embodiment further provides a method for preparing a three-dimensional memory, including the steps of:
firstly, step 1) is performed, a substrate is provided, and a stacked structure is formed on the substrate.
In the present embodiment, the substrate is typically a silicon-containing substrate such as Si, SOI (silicon on insulator), siGe, siC, or the like, but is not limited to the above-exemplified examples. Peripheral devices such as field effect transistors, capacitors, inductors, and/or diodes may be provided on the substrate as desired, and may be used as various functional devices of the memory device such as buffers, amplifiers, decoders, etc. The stacked structure comprises a stack of sacrificial dielectric layers and gate dielectric layers, for example, the stacked structure comprises alternately stacked silicon nitride layers and silicon oxide layers. The sacrificial dielectric layer is removed in a subsequent process and replaced with a gate layer at a corresponding location, which may be a material such as polysilicon, copper, aluminum, tungsten, titanium nitride, tantalum nitride, etc., but is not limited to the examples listed herein.
Then step 2) is performed, forming a first block storage area 21 and a second block storage area 22 in the stacked structure, wherein the first block storage area 21 comprises a first core area and a first step area 213 positioned in the middle of the first core area, the second block storage area comprises a second core area and a second step area 223 positioned in the middle of the second core area, the first core area and the second core area are adjacently arranged along a first direction and are mutually isolated, the first step area 213 and the second step area 223 are adjacently arranged along a second direction and are mutually isolated, and the first step area 213 is provided with a first step widening part 214 extending into the second core area along the first direction, and the first step widening part 214 is isolated from the second core area through a first grid line gap 241; the second step region 223 has a second step widening 224 extending in the first direction back into the first core region, the second step widening 224 being isolated from the first core region by a second gate line gap 245.
The first core region includes a first sub-core region 211 and a second sub-core region 212 located at two ends of the first step region 213 and the second step region 223, the first sub-core region 211 is connected to the first step region 213, the second core region includes a third sub-core region 221 and a fourth sub-core region 222 located at two ends of the first step region 213 and the second step region 223, and the fourth sub-core region is connected to the second step region 223; the first block storage area 21 further includes a first bridge wall 215 located on a side of the first step area 213 away from the first step widening portion 214, and on a side of the second step area 223 close to the second step widening portion 224, the first bridge wall 215 connects the first step area 213, the first sub-core area 211 and the second sub-core area 212, the second block storage area 22 further includes a second bridge wall 225 located on a side of the first step area 213 close to the first step widening portion 214, and on a side of the second step area 223 away from the second step widening portion 224, and the second bridge wall 225 connects the second step area 223, the third sub-core area 221 and the fourth sub-core area 222. The first sub-core region 211 and the third sub-core region 221 are separated by a first inter-block gate line gap 242, the first inter-block gate line gap 242 is connected to the first gate line gap 241, the second sub-core region 212 and the fourth sub-core region 222 are separated by a second inter-block gate line gap 243, and the second inter-block gate line gap 243 is connected to the second gate line gap 245. The first step widening 214 extends to be adjacent to the second bridging wall 225 and is isolated from the second bridging wall 225 by a third gate line gap 244, the first gate line gap 241 is connected to the third gate line gap 244, the second step widening 224 extends to be adjacent to the first bridging wall 215 and is isolated from the first bridging wall 215 by a fourth gate line gap 246, and the fourth gate line gap 246 is connected to the second gate line gap 245.
In this embodiment, forming the first core region and the second core region includes: a stacked structure is formed on a substrate, and an array of channel storage structures is formed in the stacked structure that extend through the stacked structure, the channel storage structures including a channel hole extending through the stacked structure and a memory film and a channel layer located in the channel hole. The memory film comprises a blocking layer, a charge trapping layer and a tunneling layer, wherein the blocking layer is positioned on the surface of the side wall of the channel hole, the charge trapping layer is positioned on the surface of the blocking layer, and the tunneling layer is positioned on the surface of the charge trapping layer. For example, the material of the blocking layer may be silicon dioxide, the material of the charge trapping layer may be silicon nitride, and the material of the tunneling layer may be silicon dioxide. An exemplary material for the channel layer is polysilicon. It will be appreciated that other materials may be selected for these layers. For example, the material of the barrier layer may include a high-K oxide layer; the material of the channel layer may include semiconductor materials such as monocrystalline silicon, monocrystalline germanium, siGe, siC, siGeC, siGeH, and the like.
In the process of forming the channel hole structure, the first inter-block gate line gap 242, the first gate line gap 241, the third gate line gap 244, the fourth gate line gap 246, the second gate line gap 245 and the second inter-block gate line gap 243 may be simultaneously formed in the stacked structure, wherein the first inter-block gate line gap 242 extends along a second direction (X direction) for isolating the first sub-core region 211 and the third sub-core region 221, the first gate line gap 241 extends along a first direction (Y direction) for isolating the first step region 213 and the third sub-core region 221, the third gate line gap 244 extends along a second direction (X direction) for isolating the first step region 213 and the second bridging wall 225, the fourth gate line gap 246 extends along a second direction (X direction) for isolating the second step region 223 and the first bridging wall 215, the second gate line gap 246 extends along a second direction (Y direction) for isolating the second sub-core region 212 and the second sub-core region 245.
In the above process, a plurality of inter-finger gate gaps 248 may be formed in the stacked structure at the same time, so as to isolate a plurality of finger storage areas in both the first core area and the second core area. At this time, in order to more effectively use the device region, the width of the first step widening portion 214 extending into the second core region is an integer multiple of the width of the finger storage region. In addition, due to the widening of the entire step area, the width of the first bridging wall 215 of the present embodiment may be designed to be between 0.5 and 2 of the finger storage areas 23, and the width of the second bridging wall 225 may be designed to be between 0.5 and 2 of the finger storage areas 23. The width of the step area of the single block storage area in the Y direction is increased, so that the bridge wall has larger design width, and the area of the step contact area can be reduced by increasing the width of the bridge wall, thereby reducing the design difficulty of the framework of the three-dimensional memory.
In a specific embodiment, as shown in fig. 2, the first core area and the second core area each include 3 finger storage areas, including bridge walls, the first step area 213 and the second step area 223 extend into adjacent core areas except for the widths of the 3 finger storage areas of the corresponding core areas, and occupy 2 additional widths of the finger storage areas, that is, the first step widening portion 214 and the second step widening portion 224 have widths of 2 finger storage areas, and the area occupied by each of the first step area 213 and the second step area 223 is 5 widths of the finger storage areas, where each of the first bridge wall 215 and the second bridge wall 225 occupies one width of the finger storage area.
In another embodiment, as shown in fig. 4, the first core area and the second core area each include 2 finger storage areas, including bridge walls, the first step area 213 and the second step area 223 extend into adjacent core areas except for the widths of the 2 finger storage areas of the corresponding core areas, and occupy the widths of 1 finger storage area additionally, that is, the first step widening portion 214 and the second step widening portion 224 have the widths of 1 finger storage area, and the areas occupied by the first step area 213 and the second step area 223 are each the widths of 3 finger storage areas, wherein the first bridge wall 215 and the second bridge wall 225 each occupy the width of one finger storage area.
According to the idea of the present invention, the three-dimensional memory can be applied to a scene in which 1 block memory area includes only 1 finger memory area, or a scene in which 1 block memory area includes 4 or more finger memory areas, not limited to the above-listed examples.
Next, the first step region 213 and the second step region 223 are formed by a step etching process, and steps of the first step region 213 and the second step region 223 are sequentially reduced from the respective corresponding core regions toward the isolation region 247 between the first step region 213 and the second step region 223, and are cut off at the isolation region 247. The isolation belt 247 extends in a first direction (Y direction) for isolating the first step region 213 from the second step region 223.
As described above, the three-dimensional memory and the method for manufacturing the same of the present invention have the following advantageous effects:
the invention achieves an increase in the width of the stepped region of a single block storage region in a first direction (e.g., the Y direction) by a novel gate line Gap (GLS) design such that the stepped region of the block storage region has a step widening that extends into the core region of an adjacent block storage region.
The width of the step area of the single block storage area in the Y direction is increased, the increase of the number of the partitions is facilitated, meanwhile, the bridge wall has larger design width, and the area of the step contact area can be reduced due to the increase of the width of the bridge wall, so that the design difficulty of the framework of the three-dimensional memory is reduced.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (16)
1. The three-dimensional memory is characterized by comprising a first block storage area and a second block storage area, wherein the first block storage area comprises a first core area and a first step area positioned in the middle of the first core area, the second block storage area comprises a second core area and a second step area positioned in the middle of the second core area, the first core area and the second core area are adjacently arranged along a first direction and are mutually isolated, the first step area and the second step area are adjacently arranged along a second direction and are mutually isolated, the first step area is provided with a first step widening part extending into the second core area along the first direction, and the first step widening part is isolated from the second core area through a first grid line gap; the second step region has a second step widening portion extending in a first direction reversely into the first core region, the second step widening portion being isolated from the first core region by a second gate line gap.
2. The three-dimensional memory of claim 1, wherein: the first core region comprises a first sub-core region and a second sub-core region which are positioned at two ends of the first step region and the second step region, the first sub-core region is connected with the first step region, the second core region comprises a third sub-core region and a fourth sub-core region which are positioned at two ends of the first step region and the second step region, and the fourth sub-core region is connected with the second step region; the first storage area further comprises a first bridging wall which is simultaneously positioned on one side of the first step area, which is far away from the first step widening part, and one side of the second step area, which is close to the second step widening part, wherein the first bridging wall is connected with the first step area, the first sub-core area and the second sub-core area, the second storage area further comprises a second bridging wall which is simultaneously positioned on one side of the first step area, which is close to the first step widening part, and one side of the second step area, which is far away from the second step widening part, and the second bridging wall is connected with the second step area, the third sub-core area and the fourth sub-core area.
3. The three-dimensional memory of claim 2, wherein: the first sub-core area and the third sub-core area are isolated through a first inter-block gate line gap, the first inter-block gate line gap is connected with the first gate line gap, the second sub-core area and the fourth sub-core area are isolated through a second inter-block gate line gap, and the second inter-block gate line gap is connected with the second gate line gap.
4. A three-dimensional memory according to claim 3, wherein: the first step widening part extends to be adjacent to the second bridging wall and is isolated from the second bridging wall through a third grid line gap, the first grid line gap is connected with the third grid line gap, the second step widening part extends to be adjacent to the first bridging wall and is isolated from the first bridging wall through a fourth grid line gap, and the fourth grid line gap is connected with the second grid line gap.
5. The three-dimensional memory of claim 2, wherein: the first core area and the second core area comprise a plurality of finger storage areas, and the finger storage areas are isolated through inter-finger gate line gaps.
6. The three-dimensional memory of claim 5, wherein: the width of the first step widening part extending to the inside of the second core region is an integer multiple of the width of the finger storage region.
7. The three-dimensional memory of claim 5, wherein: the width of the first bridging wall and the second bridging wall is between the width of 0.5 finger storage areas and the width of 2 finger storage areas.
8. The three-dimensional memory of claim 1, wherein: the steps of the first step area and the second step area are sequentially reduced from the core area corresponding to each step area to the isolation belt between the first step area and the second step area, and the isolation belt is cut off.
9. The three-dimensional memory of claim 1, wherein: the first direction and the second direction are perpendicular to each other.
10. The three-dimensional memory of claim 1, wherein: the first core region and the second core region comprise a stacked structure and a channel storage structure array penetrating through the stacked structure, wherein the channel storage structure comprises a channel hole penetrating through the stacked structure, a memory film and a channel layer located in the channel hole.
11. A method for preparing a three-dimensional memory, comprising the steps of:
providing a substrate, and forming a stacking structure on the substrate;
forming a first block storage area and a second block storage area in the stacked structure, wherein the first block storage area comprises a first core area and a first step area positioned in the middle of the first core area, the second block storage area comprises a second core area and a second step area positioned in the middle of the second core area, the first core area and the second core area are adjacently arranged along a first direction and are mutually isolated, the first step area and the second step area are adjacently arranged along a second direction and are mutually isolated, the first step area is provided with a first step widening part extending to the inside of the second core area along the first direction, and the first step widening part is isolated from the second core area through a first grid line gap; the second step region has a second step widening portion extending in a first direction reversely into the first core region, the second step widening portion being isolated from the first core region by a second gate line gap.
12. The method for preparing the three-dimensional memory according to claim 11, wherein: the first core region comprises a first sub-core region and a second sub-core region which are positioned at two ends of the first step region and the second step region, the first sub-core region is connected with the first step region, the second core region comprises a third sub-core region and a fourth sub-core region which are positioned at two ends of the first step region and the second step region, and the fourth sub-core region is connected with the second step region; the first storage area further comprises a first bridging wall which is simultaneously positioned on one side of the first step area, which is far away from the first step widening part, and one side of the second step area, which is close to the second step widening part, wherein the first bridging wall is connected with the first step area, the first sub-core area and the second sub-core area, the second storage area further comprises a second bridging wall which is simultaneously positioned on one side of the first step area, which is close to the first step widening part, and one side of the second step area, which is far away from the second step widening part, and the second bridging wall is connected with the second step area, the third sub-core area and the fourth sub-core area.
13. The method for preparing the three-dimensional memory according to claim 12, wherein: the first sub-core area and the third sub-core area are isolated through a first inter-block gate line gap, the first inter-block gate line gap is connected with the first gate line gap, the second sub-core area and the fourth sub-core area are isolated through a second inter-block gate line gap, and the second inter-block gate line gap is connected with the second gate line gap.
14. The method for preparing the three-dimensional memory according to claim 13, wherein: the first step widening part extends to be adjacent to the second bridging wall and is isolated from the second bridging wall through a third grid line gap, the first grid line gap is connected with the third grid line gap, the second step widening part extends to be adjacent to the first bridging wall and is isolated from the first bridging wall through a fourth grid line gap, and the fourth grid line gap is connected with the second grid line gap.
15. The method for preparing the three-dimensional memory according to claim 12, wherein: the first core area and the second core area both comprise a plurality of finger storage areas, the finger storage areas are isolated through inter-finger gate line gaps, the width of a first step widening part extending to the inside of the second core area is an integral multiple of the width of the finger storage areas, the width of a first bridging wall is between 0.5 of the width of the finger storage areas and 2 of the width of the finger storage areas, and the width of a second bridging wall is between 0.5 of the width of the finger storage areas and 2 of the width of the finger storage areas.
16. The method for preparing the three-dimensional memory according to claim 11, wherein: the steps of the first step area and the second step area are sequentially reduced from the core area corresponding to each step area to the isolation belt between the first step area and the second step area, and the isolation belt is cut off.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010175101.8A CN111403406B (en) | 2020-03-13 | 2020-03-13 | Three-dimensional memory and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010175101.8A CN111403406B (en) | 2020-03-13 | 2020-03-13 | Three-dimensional memory and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111403406A CN111403406A (en) | 2020-07-10 |
| CN111403406B true CN111403406B (en) | 2023-05-05 |
Family
ID=71413423
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010175101.8A Active CN111403406B (en) | 2020-03-13 | 2020-03-13 | Three-dimensional memory and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111403406B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111968986A (en) * | 2020-08-11 | 2020-11-20 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
| CN112185976B (en) * | 2020-09-17 | 2022-01-25 | 长江存储科技有限责任公司 | Manufacturing method of three-dimensional memory and three-dimensional memory |
| CN112331667B (en) * | 2020-11-10 | 2021-09-28 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106920796A (en) * | 2017-03-08 | 2017-07-04 | 长江存储科技有限责任公司 | A kind of 3D nand memories part and its manufacture method |
| CN106920794A (en) * | 2017-03-08 | 2017-07-04 | 长江存储科技有限责任公司 | A kind of 3D nand memories part and its manufacture method |
| CN109346471A (en) * | 2018-11-13 | 2019-02-15 | 长江存储科技有限责任公司 | Form the method and three-dimensional storage of three-dimensional storage |
| CN110114881A (en) * | 2017-03-08 | 2019-08-09 | 长江存储科技有限责任公司 | Three-dimensional storage part runs through array contacts structure |
| CN110752214A (en) * | 2019-10-28 | 2020-02-04 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
| CN110828470A (en) * | 2019-10-25 | 2020-02-21 | 长江存储科技有限责任公司 | 3D memory device and method of manufacturing the same |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101843580B1 (en) * | 2011-08-16 | 2018-03-30 | 에스케이하이닉스 주식회사 | 3d structured non-volatile memory device and method for manufacturing the same |
| CN106910746B (en) * | 2017-03-08 | 2018-06-19 | 长江存储科技有限责任公司 | A kind of 3D nand memories part and its manufacturing method, packaging method |
| CN107731846B (en) * | 2017-08-31 | 2019-01-01 | 长江存储科技有限责任公司 | Improve the three-dimensional storage forming method of channel through-hole homogeneity |
| CN107863351B (en) * | 2017-11-21 | 2019-03-19 | 长江存储科技有限责任公司 | A kind of production method and 3D nand flash memory of high stacking number 3D nand flash memory |
-
2020
- 2020-03-13 CN CN202010175101.8A patent/CN111403406B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106920796A (en) * | 2017-03-08 | 2017-07-04 | 长江存储科技有限责任公司 | A kind of 3D nand memories part and its manufacture method |
| CN106920794A (en) * | 2017-03-08 | 2017-07-04 | 长江存储科技有限责任公司 | A kind of 3D nand memories part and its manufacture method |
| CN110114881A (en) * | 2017-03-08 | 2019-08-09 | 长江存储科技有限责任公司 | Three-dimensional storage part runs through array contacts structure |
| CN109346471A (en) * | 2018-11-13 | 2019-02-15 | 长江存储科技有限责任公司 | Form the method and three-dimensional storage of three-dimensional storage |
| CN110828470A (en) * | 2019-10-25 | 2020-02-21 | 长江存储科技有限责任公司 | 3D memory device and method of manufacturing the same |
| CN110752214A (en) * | 2019-10-28 | 2020-02-04 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111403406A (en) | 2020-07-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111403406B (en) | Three-dimensional memory and preparation method thereof | |
| CN111279465B (en) | Three-dimensional NAND memory device and method of forming the same | |
| KR101787041B1 (en) | Methods for forming semiconductor devices having etch stopping layers, and methods for fabricating semiconductor devices | |
| KR101110355B1 (en) | 3d stacked array having cut-off gate line and fabrication method thereof | |
| CN109727995A (en) | Form the method and three-dimensional storage of three-dimensional storage | |
| US20150214239A1 (en) | Three dimensional non-volatile memory with charge storage node isolation | |
| CN106206600B (en) | Memory device and its manufacturing method and electronic equipment including the memory device | |
| US20140227840A1 (en) | 3d non-volatile memory device and method for fabricating the same | |
| CN108511454B (en) | 3D NAND memory and preparation method thereof | |
| WO2009119527A1 (en) | Semiconductor memory and method for manufacturing the same | |
| CN106298679A (en) | Memory device and manufacture method thereof and include the electronic equipment of this memory device | |
| CN111968987B (en) | Three-dimensional memory and method for manufacturing the same | |
| CN111403390B (en) | Semiconductor structure, manufacturing method thereof and three-dimensional memory device | |
| CN110808253A (en) | Three-dimensional memory structure and preparation method thereof | |
| TWI772958B (en) | Three-dimensional memory device and manufacturing method thereof | |
| CN112185967B (en) | Three-dimensional memory and manufacturing method thereof | |
| CN111968986A (en) | Three-dimensional memory and manufacturing method thereof | |
| US8951881B2 (en) | Methods of fabricating nonvolatile memory devices including voids between active regions and related devices | |
| CN111668228B (en) | 3D NAND memory and forming method thereof | |
| US20220005828A1 (en) | Vertical memory devices | |
| CN111341780B (en) | 3D NAND memory and manufacturing method thereof | |
| CN114664837A (en) | Memory device | |
| TWI832643B (en) | Memory device and method for manufacturing the same | |
| CN114080680B (en) | Three-dimensional memory and manufacturing method thereof | |
| CN108538849B (en) | Three-dimensional stacked flash memory structure and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |