CN111403308A - Automatic control method and automatic control system for thermal budget - Google Patents

Automatic control method and automatic control system for thermal budget Download PDF

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Publication number
CN111403308A
CN111403308A CN202010233890.6A CN202010233890A CN111403308A CN 111403308 A CN111403308 A CN 111403308A CN 202010233890 A CN202010233890 A CN 202010233890A CN 111403308 A CN111403308 A CN 111403308A
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side wall
thermal budget
thickness
annular region
deviation
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李中华
冷江华
田明
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10Measuring as part of the manufacturing process
    • H01L22/12Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67098Apparatus for thermal treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

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Abstract

The invention discloses an automatic control method of thermal budget, which comprises the steps of setting a target value of the thickness of a side wall, a qualified interval and a thermal budget tolerance interval; calculating the average thickness value of the side wall and the deviation between the thickness value of the side wall in the annular region of different side walls and the target thickness value of the side wall; judging whether the first deviation between the average side wall thickness value and the target side wall thickness value is within the qualified side wall thickness interval or not, and if not, scrapping the silicon wafer; judging whether a second deviation between the side wall thickness value in the side wall annular region and the side wall thickness target value is within a thermal budget tolerance interval or not; if the second deviation is within the thermal budget tolerance interval, keeping the thermal budget temperature; decreasing the thermal budget temperature if the second deviation is negative; if the second deviation is a positive increase in thermal budget temperature; and performing rapid thermal annealing according to the adjusted thermal budget temperature of each side wall annular region. The invention also discloses an automatic control system for the thermal budget. The invention can realize the uniformity of the performance of the silicon chip device, thereby improving the yield of products on a large scale.

Description

Automatic control method and automatic control system for thermal budget
Technical Field
The invention relates to the field of integrated circuit manufacturing, in particular to a thermal budget control method for a rapid thermal annealing SMT RTA process of an integrated circuit stress memory technology.
Background
The SMT RTA temperature adjustment method of the existing 40nm/28nm product is shown in figure 1 and comprises the following steps: the whole chip leakage current of the product chip is firstly measured, and the large leakage current corresponds to the high SMT RTA temperature. Then comparing the distribution graph in the leakage current chip of the chip with the distribution graph in the resistance chip of the blocking control chip for monitoring the SMT RTA temperature change, wherein the low resistance of the blocking control chip represents that the SMTRTA temperature is high. And judging whether the resistance on the control blocking sheet is relatively low at the place where the leakage current of the product sheet is relatively large or whether the resistance on the control blocking sheet is relatively high at the place where the leakage current of the product sheet is relatively small. If the distribution in the leakage current chip and the distribution in the resistor chip are corresponding, which indicates that the temperature distribution of the SMT RTA influences the distribution of the leakage current in the product chip, the thermal budget of different areas in the product chip needs to be adjusted, namely, the temperature of different annular areas of the SMT RTA heating lamp set is manually adjusted. The method for manually adjusting the SMT RTA temperature based on the product chip leakage current result belongs to post remedy, is similar to sheep killing, is only suitable for improving the device performance of subsequent batches of products, does not have any remedial measure for the current products, and does not have timeliness. In addition, the conventional SMTRTA adjusting method can only aim at the whole batch of products and cannot dynamically adjust different silicon wafers in the same batch, so that the uniformity of device performance among wafers cannot be improved.
Stress Memorization Technique (SMT) is a Stress engineering that is developed below 90nm logic technology nodes and aims at increasing the speed of NMOS devices.
Rapid Thermal Annealing (RTA) is a conventional technique in semiconductor processing and is generally used to activate doping elements in semiconductor materials and restore the amorphous structure resulting from ion implantation to a complete lattice structure.
Disclosure of Invention
In this summary, a series of simplified form concepts are introduced that are simplifications of the prior art in this field, which will be described in further detail in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
The invention aims to solve the technical problem of providing a SMTRTA process for the rapid thermal annealing of the stress memory technology of an integrated circuit, which can dynamically adjust the thermal budget temperature of the rapid thermal annealing of the annular region of each side wall between different silicon chips in the same batch or different batches and the thermal budget temperature of the rapid thermal annealing of the annular region of each side wall of the same silicon chip.
Another technical problem to be solved by the present invention is to provide an automatic thermal budget control system capable of dynamically adjusting the thermal budget temperature for the rapid thermal annealing of the sidewall annular regions between different silicon wafers in the same batch and/or different batches, and the thermal budget temperature for the rapid thermal annealing of the sidewall annular regions of the same silicon wafer.
In order to solve the above technical problems, the present invention provides an automatic thermal budget control method for an SMTRTA process for rapid thermal annealing in an integrated circuit stress memorization technique, comprising the following steps:
s1, setting a target value of the thickness of the side wall, a qualified interval of the thickness of the side wall and a thermal budget tolerance interval of the thickness of the side wall according to the process requirement;
and the thermal budget tolerance interval of the thickness of the side wall is a non-vacuum subset of the qualified interval of the thickness of the side wall.
Alternatively, the target value of the sidewall thickness is in the range
Figure BDA0002430314260000021
The qualified interval range of the side wall thickness is
Figure BDA0002430314260000022
Figure BDA0002430314260000023
The range of the thermal budget tolerance interval of the side wall thickness is
Figure BDA0002430314260000024
Figure BDA0002430314260000025
Wherein the content of the first and second substances,
Figure BDA0002430314260000026
and b is more than a, and X is more than Y and is more than or equal to 1.
Optionally, the target value of the thickness of the side wall is an optical measurement target value; hypothetical, optical measurement of sidewall thickness target
Figure BDA0002430314260000027
The qualified interval of the side wall thickness is
Figure BDA0002430314260000028
The thermal budget tolerance interval of the side wall thickness is
Figure BDA0002430314260000029
Figure BDA00024303142600000210
S2, measuring the thickness value of the whole side wall of the silicon wafer, and calculating the average value of the thickness of the side wall in the wafer and the deviation between the thickness value of the side wall in the annular region of different side walls and the target value of the thickness of the side wall; the deviation is the difference between the measured value and the measured average value;
s3, judging whether the first deviation between the average thickness value of the side wall in the silicon chip and the target thickness value of the side wall is in the qualified interval of the thickness of the side wall, if not, discarding the silicon chip;
s4, judging whether a second deviation between the side wall thickness value in the side wall annular region and the target side wall thickness value is within a thermal budget tolerance range;
if the second deviation of the side wall annular region is within the thermal budget tolerance interval, keeping the thermal budget temperature of the side wall annular region;
if the second deviation of the side wall annular region is negative, reducing the thermal budget temperature of the side wall annular region;
if the second deviation of the side wall annular region is positive, increasing the thermal budget temperature of the side wall annular region;
optionally, when the second deviation is negative, the reduced thermal budget temperature of the side wall annular region is equal to a thermal budget temperature corresponding to the influence of the reduced thickness of the side wall relative to the target value on the leakage current of the device;
when the second deviation is positive, the increased thermal budget temperature of the side wall annular region is equal to the thermal budget temperature corresponding to the influence of the increased relative target value of the side wall thickness on the leakage current of the device;
and S5, performing rapid thermal annealing according to the adjusted thermal budget temperature of each side wall annular region.
The invention provides a thermal budget automatic control system for an integrated circuit stress memory technology rapid thermal annealing SMT RTA process, which comprises:
the standard setting module is suitable for setting a target side wall thickness value, a qualified side wall thickness interval and a thermal budget tolerance interval of the side wall thickness according to the manufacturing process requirement;
the standard setting module sets a non-vacuum subset of a sidewall thickness qualified interval as a sidewall thickness thermal budget tolerance interval;
optionally, the standard setting module sets the target value of the sidewall thickness to be within the range
Figure BDA0002430314260000031
The qualified interval range of the side wall thickness is
Figure BDA0002430314260000032
The range of the thermal budget tolerance interval of the side wall thickness is
Figure BDA0002430314260000033
Figure BDA0002430314260000034
Wherein the content of the first and second substances,
Figure BDA0002430314260000035
b is more than a, X is more than Y and is more than or equal to 1;
optionally, the target value of the thickness of the side wall is an optical measurement target value; hypothetical, optical measurement of sidewall thickness target
Figure BDA0002430314260000036
The qualified interval of the side wall thickness is
Figure BDA0002430314260000037
The thermal budget tolerance interval of the side wall thickness is
Figure BDA0002430314260000038
Figure BDA0002430314260000039
The measurement calculation module is suitable for measuring the thickness value of the whole side wall of the silicon wafer, and calculating the average value of the thickness of the inner side wall and the deviation between the thickness value of the inner side wall in the annular region of different side walls and the target value of the thickness of the side wall;
the judging module is suitable for judging whether the first deviation between the average value of the thicknesses of the inner side walls and the target value of the thicknesses of the side walls is in the qualified interval of the thicknesses of the side walls or not, and if not, scrapping the silicon slice;
the method is suitable for judging whether a second deviation between the side wall thickness value in the side wall annular region and the side wall thickness target value is within a thermal budget tolerance range;
the control module is suitable for keeping the thermal budget temperature of the side wall annular region if the second deviation of the side wall annular region is within the thermal budget tolerance interval;
the method is suitable for reducing the thermal budget temperature of the side wall annular region if the second deviation of the side wall annular region is negative;
the method is suitable for increasing the thermal budget temperature of the side wall annular region if the second deviation of the side wall annular region is positive;
when the second deviation is negative, the reduced thermal budget temperature of the side wall annular region is equal to the thermal budget temperature corresponding to the influence of the reduced thickness of the side wall relative to the target value on the leakage current of the device, and the thermal budget temperature can be specified through calibration or empirical values.
When the second deviation is positive, the increased thermal budget temperature of the side wall annular region is equal to the thermal budget temperature corresponding to the influence of the increased thickness of the side wall relative to the target value on the leakage current of the device, and the thermal budget temperature can be specified through calibration or an empirical value.
And the heating module is suitable for executing rapid thermal annealing according to the adjusted thermal budget temperature of each side wall annular region.
Alternatively, the heating module is a concentric annular lamp set with adjustable power.
Taking a 28nm product silicon wafer as an example, referring to fig. 2, the thickness distribution of the inner side wall of the silicon wafer after the side wall etching is shown, and it can be seen that the thickness distribution is obviously distributed annularly, i.e. the side wall annular region of the invention. According to experience, the side wall thickness is smaller, the leakage current of the device is larger, and the temperature equivalent to the RTA temperature of the SMT is higher; the thickness of the side wall is larger, the leakage current of the device is smaller, and the temperature equivalent to SMT RTA is lower. If the SMT RTA heating lamp set can be dynamically adjusted according to the temperature of the bulbs in the annular regions of the different side walls when the product pieces reach the SMT RTA process, and the thermal budget is used to compensate for the mismatch of device performance caused by the deviation of the thickness of the side walls from the target value, the performance of devices between different batches of silicon wafers or between the same batch of silicon wafers and within the silicon wafers approaches the target value, and high uniformity is achieved, so that the yield of products can be improved on a large scale.
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The accompanying drawings, which are included to provide a further understanding of the invention, are incorporated in and constitute a part of this specification. The drawings are not necessarily to scale, however, and may not be intended to accurately reflect the precise structural or performance characteristics of any given embodiment, and should not be construed as limiting or restricting the scope of values or properties encompassed by exemplary embodiments in accordance with the invention. The invention will be described in further detail with reference to the following detailed description and accompanying drawings:
FIG. 1 is a schematic flow chart of a temperature adjustment method for a rapid thermal annealing SMT RTA process in the prior art.
Fig. 2 is a schematic distribution diagram in the thickness plane of the silicon wafer side wall, Mean:
Figure BDA0002430314260000041
3-sigma:
Figure BDA0002430314260000042
Range(U%):
Figure BDA0002430314260000043
(1.1%), and each numerical value is marked in the figure to represent the thickness of the side wall.
FIG. 3 is a schematic diagram of a distribution of stress memorization technology rapid thermal annealing SMT RTA process heating lamp sets.
FIG. 4 is a flow chart of an automatic thermal budget control method according to the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and technical effects of the present invention will be fully apparent to those skilled in the art from the disclosure in the specification. The invention is capable of other embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the general spirit of the invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. The following exemplary embodiments of the present invention may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. It is to be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the technical solutions of these exemplary embodiments to those skilled in the art.
Further, it will be understood that, although the terms first, second, etc. may be used herein to describe various elements, parameters, components, regions, layers and/or sections, these elements, parameters, components, regions, layers and/or sections should not be limited by these terms.
In a first embodiment, the present invention provides a method for automatically controlling a thermal budget for a rapid thermal annealing (SMT) RTA process of an integrated circuit stress memorization technique, comprising the steps of:
s1, setting a target value of the thickness of the side wall, a qualified interval of the thickness of the side wall and a thermal budget tolerance interval of the thickness of the side wall according to the process requirement;
and the thermal budget tolerance interval of the thickness of the side wall is a non-vacuum subset of the qualified interval of the thickness of the side wall.
S2, measuring the thickness value of the whole side wall of the silicon wafer, and calculating the average value of the thickness of the side wall in the wafer and the deviation between the thickness value of the side wall in the annular region of different side walls and the target value of the thickness of the side wall; the deviation is the difference between the measured value and the measured average value;
s3, judging whether the first deviation between the average thickness value of the side wall in the silicon chip and the target thickness value of the side wall is in the qualified interval of the thickness of the side wall, if not, discarding the silicon chip;
s4, judging whether a second deviation between the side wall thickness value in the side wall annular region and the target side wall thickness value is within a thermal budget tolerance range;
if the second deviation of the side wall annular region is within the thermal budget tolerance interval, keeping the thermal budget temperature of the side wall annular region;
if the second deviation of the side wall annular region is negative, reducing the thermal budget temperature of the side wall annular region;
if the second deviation of the side wall annular region is positive, increasing the thermal budget temperature of the side wall annular region;
and S5, performing rapid thermal annealing according to the adjusted thermal budget temperature of each side wall annular region.
In a second embodiment, the present invention provides a method for automatically controlling thermal budget for a rapid thermal annealing (SMT) RTA process of an integrated circuit stress memorization technique, comprising the following steps:
s1, setting a target value of the thickness of the side wall, a qualified interval of the thickness of the side wall and a thermal budget tolerance interval of the thickness of the side wall according to the process requirement;
the target value of the thickness of the side wall is in the range
Figure BDA0002430314260000061
Qualified interval range of side wall thicknessIs that
Figure BDA0002430314260000062
Figure BDA0002430314260000063
The range of the thermal budget tolerance interval of the side wall thickness is
Figure BDA0002430314260000064
Wherein the content of the first and second substances,
Figure BDA0002430314260000065
and b is more than a, and X is more than Y and is more than or equal to 1.
Optionally, the target value of the thickness of the side wall is an optical measurement target value; hypothetical, optical measurement of sidewall thickness target
Figure BDA0002430314260000066
The qualified interval of the side wall thickness is
Figure BDA0002430314260000067
The thermal budget tolerance interval of the side wall thickness is
Figure BDA0002430314260000068
Figure BDA0002430314260000069
S2, measuring the thickness value of the whole side wall of the silicon wafer, and calculating the average value of the thickness of the side wall in the wafer and the deviation between the thickness value of the side wall in the annular region of different side walls and the target value of the thickness of the side wall; the deviation is the difference between the measured value and the measured average value;
s3, judging whether the first deviation between the average thickness value of the side wall in the silicon chip and the target thickness value of the side wall is in the qualified interval of the thickness of the side wall, if not, discarding the silicon chip;
s4, judging whether a second deviation between the side wall thickness value in the side wall annular region and the target side wall thickness value is within a thermal budget tolerance range;
if the second deviation of the side wall annular region is within the thermal budget tolerance interval, keeping the thermal budget temperature of the side wall annular region;
if the second deviation of the side wall annular region is negative, the reduced thermal budget temperature of the side wall annular region is equal to the thermal budget temperature corresponding to the influence of the smaller relative target value of the side wall thickness on the leakage current of the device, and the thermal budget temperature is set according to a calibration/empirical value;
if the second deviation of the side wall annular region is positive, the increased thermal budget temperature of the side wall annular region is equal to the thermal budget temperature corresponding to the influence of the increased relative target value of the side wall thickness on the leakage current of the device, and the thermal budget temperature is set according to the calibration/empirical value;
and S5, performing rapid thermal annealing according to the adjusted thermal budget temperature of each side wall annular region.
In a third embodiment, the present invention provides an automatic thermal budget control system for an integrated circuit stress memorization (SRMA) technology fast thermal annealing (SMT) RTA process, comprising:
the standard setting module is suitable for setting a target side wall thickness value, a qualified side wall thickness interval and a thermal budget tolerance interval of the side wall thickness according to the manufacturing process requirement;
the standard setting module sets a non-vacuum subset of a sidewall thickness qualified interval as a sidewall thickness thermal budget tolerance interval;
the measurement calculation module is suitable for measuring the thickness value of the whole side wall of the silicon wafer, and calculating the average value of the thickness of the inner side wall and the deviation between the thickness value of the inner side wall in the annular region of different side walls and the target value of the thickness of the side wall;
the judging module is suitable for judging whether the first deviation between the average value of the thicknesses of the inner side walls and the target value of the thicknesses of the side walls is in the qualified interval of the thicknesses of the side walls or not, and if not, scrapping the silicon slice;
the method is suitable for judging whether a second deviation between the side wall thickness value in the side wall annular region and the side wall thickness target value is within a thermal budget tolerance range;
the control module is suitable for keeping the thermal budget temperature of the side wall annular region if the second deviation of the side wall annular region is within the thermal budget tolerance interval;
the method is suitable for reducing the thermal budget temperature of the side wall annular region if the second deviation of the side wall annular region is negative;
the method is suitable for increasing the thermal budget temperature of the side wall annular region if the second deviation of the side wall annular region is positive;
and the heating module is suitable for executing rapid thermal annealing according to the adjusted thermal budget temperature of each side wall annular region.
Alternatively, the heating module is a concentric annular lamp set with adjustable power. The standard setting module, the measurement calculation module, the judgment module and the control module can be integrated in a production machine and are realized by combining the existing functions of the production machine with a computer programming technology (such as scripts).
In a third embodiment, the present invention provides an automatic thermal budget control system for an integrated circuit stress memorization (SRMA) technology fast thermal annealing (SMT) RTA process, comprising:
the standard setting module is suitable for setting a target side wall thickness value, a qualified side wall thickness interval and a thermal budget tolerance interval of the side wall thickness according to the manufacturing process requirement;
wherein the standard setting module sets the target value of the thickness of the side wall to be within the range
Figure BDA0002430314260000071
The qualified interval range of the side wall thickness is
Figure BDA0002430314260000072
The range of the thermal budget tolerance interval of the side wall thickness is
Figure BDA0002430314260000073
Figure BDA0002430314260000074
B is more than a, X is more than Y and is more than or equal to 1;
optionally, the target value of the thickness of the side wall is an optical measurement target value; hypothetical, optical measurement of sidewall thickness target
Figure BDA0002430314260000075
The qualified interval of the side wall thickness is
Figure BDA0002430314260000076
The thermal budget tolerance interval of the side wall thickness is
Figure BDA0002430314260000077
Figure BDA0002430314260000078
The measurement calculation module is suitable for measuring the thickness value of the whole side wall of the silicon wafer, and calculating the average value of the thickness of the inner side wall and the deviation between the thickness value of the inner side wall in the annular region of different side walls and the target value of the thickness of the side wall;
the judging module is suitable for judging whether the first deviation between the average value of the thicknesses of the inner side walls and the target value of the thicknesses of the side walls is in the qualified interval of the thicknesses of the side walls or not, and if not, scrapping the silicon slice;
the method is suitable for judging whether a second deviation between the side wall thickness value in the side wall annular region and the side wall thickness target value is within a thermal budget tolerance range;
the control module is suitable for keeping the thermal budget temperature of the side wall annular region if the second deviation of the side wall annular region is within the thermal budget tolerance interval;
the method is suitable for reducing the thermal budget temperature of the side wall annular region to be equal to the thermal budget temperature corresponding to the influence of the reduction of the relative target value of the side wall thickness on the leakage current of the device if the second deviation of the side wall annular region is negative, and the thermal budget temperature can be specified through calibration or empirical values;
the method is suitable for increasing the thermal budget temperature of the side wall annular region to be equal to the thermal budget temperature corresponding to the influence of the larger relative target value of the side wall thickness on the leakage current of the device if the second deviation of the side wall annular region is positive, and the thermal budget temperature can be specified through calibration or empirical value;
and the heating module is suitable for executing rapid thermal annealing according to the adjusted thermal budget temperature of each side wall annular region.
Alternatively, the heating module is a concentric annular lamp set with adjustable power.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The present invention has been described in detail with reference to the specific embodiments and examples, but these are not intended to limit the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (9)

1. An automatic control method for thermal budget, which is used for thermal budget control of integrated circuit stress memorization technology rapid thermal annealing (SMT RTA) process, is characterized by comprising the following steps:
s1, setting a target value of the thickness of the side wall, a qualified interval of the thickness of the side wall and a thermal budget tolerance interval of the thickness of the side wall according to the process requirement;
s2, measuring the thickness value of the whole side wall of the silicon wafer, and calculating the average value of the thickness of the side wall in the wafer and the deviation between the thickness value of the side wall in the annular region of different side walls and the target value of the thickness of the side wall;
s3, judging whether the first deviation between the average thickness value of the side wall in the silicon chip and the target thickness value of the side wall is in the qualified interval of the thickness of the side wall, if not, discarding the silicon chip;
s4, judging whether a second deviation between the side wall thickness value in the side wall annular region and the target side wall thickness value is within a thermal budget tolerance range;
if the second deviation of the side wall annular region is within the thermal budget tolerance interval, keeping the thermal budget temperature of the side wall annular region;
if the second deviation of the side wall annular region is negative, reducing the thermal budget temperature of the side wall annular region;
if the second deviation of the side wall annular region is positive, increasing the thermal budget temperature of the side wall annular region;
and S5, performing rapid thermal annealing according to the adjusted thermal budget temperature of each side wall annular region.
2. The method of claim 1, wherein: the side wall thickness thermal budget tolerance interval is a non-vacuum subset of the qualified interval of the side wall thickness.
3. The method of claim 1, wherein: the target value of the thickness of the side wall is in the range
Figure FDA0002430314250000011
The qualified interval range of the side wall thickness is
Figure FDA0002430314250000012
The range of the thermal budget tolerance interval of the side wall thickness is
Figure FDA0002430314250000013
Wherein the content of the first and second substances,
Figure FDA0002430314250000014
and b is more than a, and X is more than Y and is more than or equal to 1.
4. The method of claim 1, wherein: when the second deviation is negative, the reduced thermal budget temperature of the side wall annular region is equal to the thermal budget temperature corresponding to the influence of the reduced relative target value of the side wall thickness on the leakage current of the device;
when the second deviation is positive, the increased thermal budget temperature of the side wall annular region is equal to the thermal budget temperature corresponding to the influence of the increased relative target value of the side wall thickness on the leakage current of the device.
5. An automatic thermal budget control system for thermal budget control of an integrated circuit stress memorization technique rapid thermal annealing (SMT RTA) process, comprising:
the standard setting module is suitable for setting a target side wall thickness value, a qualified side wall thickness interval and a thermal budget tolerance interval of the side wall thickness according to the manufacturing process requirement;
the measurement calculation module is suitable for measuring the thickness value of the whole side wall of the silicon wafer, and calculating the average value of the thickness of the inner side wall and the deviation between the thickness value of the inner side wall in the annular region of different side walls and the target value of the thickness of the side wall;
the judging module is suitable for judging whether the first deviation between the average value of the thicknesses of the inner side walls and the target value of the thicknesses of the side walls is in the qualified interval of the thicknesses of the side walls or not, and if not, scrapping the silicon slice;
the method is suitable for judging whether a second deviation between the side wall thickness value in the side wall annular region and the side wall thickness target value is within a thermal budget tolerance range;
the control module is suitable for keeping the thermal budget temperature of the side wall annular region if the second deviation of the side wall annular region is within the thermal budget tolerance interval;
the method is suitable for reducing the thermal budget temperature of the side wall annular region if the second deviation of the side wall annular region is negative;
the method is suitable for increasing the thermal budget temperature of the side wall annular region if the second deviation of the side wall annular region is positive;
and the heating module is suitable for executing rapid thermal annealing according to the adjusted thermal budget temperature of each side wall annular region.
6. The automatic thermal budget control system according to claim 5, wherein: the standard setting module sets the thermal budget tolerance interval of the side wall thickness to be a non-vacuum true subset of the qualified interval of the side wall thickness.
7. The automatic thermal budget control system according to claim 5, wherein: standard setting module deviceThe target thickness of the sidewall spacer is in the range
Figure FDA0002430314250000021
The qualified interval range of the side wall thickness is
Figure FDA0002430314250000022
Figure FDA0002430314250000023
The range of the thermal budget tolerance interval of the side wall thickness is
Figure FDA0002430314250000024
Wherein the content of the first and second substances,
Figure FDA0002430314250000025
and b is more than a, and X is more than Y and is more than or equal to 1.
8. The automatic thermal budget control system according to claim 5, wherein: when the second deviation is negative, the reduced thermal budget temperature of the side wall annular region is equal to the thermal budget temperature corresponding to the influence of the reduced relative target value of the side wall thickness on the leakage current of the device;
when the second deviation is positive, the increased thermal budget temperature of the side wall annular region is equal to the thermal budget temperature corresponding to the influence of the increased relative target value of the side wall thickness on the leakage current of the device.
9. The automatic thermal budget control system according to claim 5, wherein: the heating module is a concentric annular lamp group with adjustable power.
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