CN111385578B - Data decompression method applied to FPGA, imaging device and automobile - Google Patents
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Abstract
The application provides a data decompression method applied to an FPGA, imaging equipment and an automobile, wherein the method comprises the following steps: acquiring compressed data and a compression coefficient; when the digit m of the compression coefficient is judged to be larger than a preset fixed value n, determining data obtained by right shifting the compression coefficient by m minus n bits as first data; determining the compression coefficient as first data when the bit number m of the compression coefficient is judged to be less than or equal to a fixed value n; searching second data corresponding to the first data in a pre-established lookup table; the lookup table comprises binary second data obtained by shifting the reciprocal of each positive integer from n bits 0 to 1 to s bits of the binary left; determining a numerical value obtained by right shifting the second data corresponding to the first data by m minus n bits as third data; and performing multiplication operation on the compressed data and the third data to obtain decompressed data. The method and the device have the advantages that the decompressed data meeting the user requirements can be obtained, and the processing speed and the processing efficiency can be guaranteed.
Description
Technical Field
The application belongs to the technical field of image processing, and particularly relates to a data decompression method applied to an FPGA, imaging equipment and an automobile.
Background
In the field of audio and video transmission, in order to save transmission bandwidth, a sending end generally needs to compress data before transmitting data, and a receiving end decompresses the data after receiving the data. The decompression process is generally the inverse operation of the compression process.
For example, in the conventional image transmission, the original image is generally transmitted after being compressed, and in the compression, a multiplication operation is generally adopted. Correspondingly, in the process of restoring and displaying the image data after transmission, division operation is required, so that the original image is restored.
The Field Programmable Gate Array (FPGA) has the advantages of short development period, low manufacturing cost, flexible configuration, high processing speed and the like, and is widely applied to the Field of digital signal processing.
Disclosure of Invention
Although FPGAs have strong data processing performance, the existing FPGAs have many disadvantages in the division operation, for example, the existing FPGAs generally perform the division operation by using the following method:
1) using a divider IP core provided in the development software: in this way, a divider IP core carried by an FPGA development platform needs to be utilized, and the IP core is directly called in engineering to perform division operation, however, the time delay of the division operation is relatively high, for example, for dividers with 24 bits of dividends, 32 bits of divisors and 25 bits of remainders, a time delay of 51 clocks generally exists;
2) and (4) table lookup: in the method, reciprocals corresponding to all data need to be stored in the FPGA in advance, when division operation is performed, the reciprocal corresponding to the data is searched in a table look-up mode, but for the data with more digits, the table look-up mode occupies excessive resources, and the more digits are, the larger the occupied resources are;
3) self-developed write divider: the method needs engineers to develop dividers by themselves, needs operations such as shifting, adding and the like, has different delays according to different digits, and has the defects of long development time, poor stability and the like.
The above disadvantages of the FPGA in the division operation cause problems of high delay, large resource occupation, long development period, etc. when the FPGA is used to perform data decompression processing related to the division operation.
In view of the above, the present application provides a data decompression method applied to an FPGA, an imaging apparatus, and an automobile that overcome or at least partially solve the above problems.
In a first aspect of embodiments of the present application, a data decompression method applied to an FPGA is provided, including:
acquiring compressed data and a compression coefficient; the compressed data is obtained by multiplying original data and the compression coefficient which is shifted to the right by s bits; the compressed data, the original data and the compression coefficient are binary data, and the compression coefficient is m bits;
when the digit m of a compression coefficient is judged to be larger than a preset fixed value n, determining data obtained by right shifting the compression coefficient by m minus n bits as first data; when the bit number m of a compression coefficient is judged to be less than or equal to the fixed value n, determining the compression coefficient as first data; wherein m, n and s are positive integers;
searching second data corresponding to the first data in a pre-established lookup table; the lookup table comprises binary second data obtained by shifting the reciprocal of each positive integer from n bits 0 to 1 to the left by s bits;
determining a numerical value obtained by right shifting the second data corresponding to the first data by m minus n bits as third data;
and performing multiplication operation on the compressed data and the third data to obtain decompressed data.
In a second aspect of embodiments of the present application, there is provided an FPGA comprising: a configurable logic block comprising a shift register and a memory;
the memory is used for storing a pre-established lookup table, and the lookup table comprises binary second data obtained by shifting the reciprocal of each positive integer from n bits 0 to n bits 1 of the binary by s bits to the left;
the configurable logic block is to:
acquiring compressed data and a compression coefficient; the compressed data is obtained by multiplying original data and the compression coefficient which is shifted to the right by s bits; the compressed data, the original data and the compression coefficient are binary data, and the compression coefficient is m bits;
when the digit m of the compression coefficient is judged to be larger than a preset fixed value n, data obtained by shifting the compression coefficient to the right by m minus n bits is determined as first data by operating the shift register; when the bit number m of a compression coefficient is judged to be less than or equal to the fixed value n, the compression coefficient is determined to be first data by operating the shift register; wherein m, n and s are positive integers;
searching second data corresponding to the first data in the lookup table;
determining a numerical value obtained by right shifting second data corresponding to the first data by m minus n bits as third data by operating the shift register;
and performing multiplication operation on the compressed data and the third data to obtain decompressed data.
In a third aspect of embodiments of the present application, there is provided an image forming apparatus comprising: an image sensor and an FPGA;
the image sensor is used for shooting an image, multiplying original data of the image by a preset compression coefficient to obtain compressed data, and sending the compression coefficient and the compressed data to the FPGA;
the FPGA is configured to perform the steps of the data decompression method as previously described for application to the FPGA.
In a fourth aspect of embodiments of the present application, there is provided an automobile comprising: an image processing server and the imaging apparatus as described above;
and the image processing server receives the decompressed data output by the imaging equipment and performs visual analysis processing on the decompressed data.
In a fifth aspect of embodiments of the present application, a computer-readable storage medium is provided, which is characterized in that the computer-readable storage medium stores thereon computer instructions, and the instructions, when executed, implement the data decompression method applied to the FPGA as described above.
By means of the technical scheme, the data decompression method provided by the embodiment of the application can be well applied to the field of decompression processing (such as video, audio and the like) of the data in the FPGA, and has the advantages of obtaining the decompressed data meeting the user requirements and ensuring high processing speed and high efficiency.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without any creative effort.
Fig. 1 is a flowchart of a data decompression method applied to an FPGA according to an embodiment of the present application;
FIG. 2 is a block diagram of an autonomous vehicle according to an embodiment of the present application;
FIG. 3 is a graph illustrating piecewise linearization of compressed image data for an imaging device provided by an embodiment of the application;
fig. 4 is a block diagram of an imaging apparatus provided in an embodiment of the present application.
Detailed Description
In order to make those skilled in the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
For convenience of understanding, technical terms related to the present application are explained as follows:
(1) the "number of data bits m, n" referred to herein is decimal data;
(2) as used herein, "compressed data DcmpOriginal data DorgData processed by the FPGA, such as the compression coefficient gain, the first data D1, the second data D2, and the third data D3 ″ are binary data;
(3) the "left shift" operation and the identifier "<" in this document are to shift binary data to the left by the specified number of shifted bits, the shifted bits are discarded, and the left empty bit is complemented by 0;
(4) as used herein, the term "shift right" operation and the identifier "> >" refers to the shifting of binary data to the right by a specified number of shifted bits, the shifted bits being discarded, and the left shifted null or 0 being complemented;
(5) the term "and/or" herein is merely an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship;
(6) the term "autonomous vehicle" as used herein refers to a vehicle having a manned (e.g., a car for home use, a bus, etc.), a cargo (e.g., a general truck, a van, a closed truck, a tank truck, a flat truck, a container van, a dump truck, a truck with a special structure, etc.), or a special rescue function (e.g., a fire truck, an ambulance, etc.) by using an autonomous driving technique.
Summary of The Invention
In the field of signal transmission, in order to save bandwidth, a transmitting end usually aligns original data D with larger bandwidth before transmitting the dataorgPerforming compression processing, wherein the compression processing comprises the step of compressing the original data DorgMultiplying with a number less than 1 to obtain compressed data D with small bit widthcmpAccordingly, the receiving end receives the compressed data DcmpThen decompression processing is needed, and the decompression processing process comprises the step of compressing the data DcmpThe decompressed data is obtained by dividing by the above number smaller than 1.
When the receiving end is an FPGA, the division operation is performed in the decompression processing process, and the FPGA has the disadvantages of high delay, large resource occupation, poor stability and the like in the aspect of the division operation, so that the processing speed of the data decompression process is slow, and the transmission process is blocked. In addition, when the FPGA stores the decimal, the decimal can only be implemented by storing the binary positive integer and then performing right shift operation on the binary positive integer, and this storage mode also causes a slow processing speed and a high delay time in the decompression process.
In order to overcome the above problem, an embodiment of the present application provides a data decompression method applied to an FPGA, as shown in fig. 1, the method includes:
step S100, obtaining compressed data DcmpAnd a compression factor gain.
Wherein the data D is compressedcmpOriginal data DorgThe compression coefficient gain is binary data, and the compression coefficient gain is m bits (m is a positive integer).
Compressed data DcmpIs made up of the original data DorgThe data obtained by multiplication with the compression coefficient gain shifted to the right by s bits (s is a positive integer) has the following characteristics because the shift of the binary data by the FPGA is equivalent to the multiplication:
Dcmp＝Dorg×gain×2-s(formula 1)
The compression coefficient gain shifted to the right by s bits is actually a decimal used for multiplication in compression processing stored by the FPGA, and the FPGA cannot directly store the decimal, so that the compression coefficient gain is realized by storing a binary positive integer compression coefficient gain and shifting the compression coefficient gain to the right by s bits.
For example, the compression factor gain is 24-bit binary data, and is shifted to the right by 24 bits, i.e. m is 24 and s is 24, then: dcmp＝Dorg×gain×2-24。
Step S102, when the digit m of the compression coefficient gain is judged to be larger than a preset fixed value n (n is a positive integer), determining data obtained by shifting the compression coefficient gain to the right by m and subtracting n bits as first data D1; and determining the compression coefficient gain as the first data D1 when the bit number m of the compression coefficient gain is judged to be less than or equal to a preset fixed value n.
According to this step, the following formula is given:
when m is greater than n, D1 ═ gain>>(m-n)＝gain×2-m+n(formula 2)
When m is less than or equal to n, D1 ═ gain (formula 9)
For example, n is a fixed positive integer 10, and if m is 24, the compression coefficient gain is shifted to the right by 14 bits to obtain first data D1; if m is 8, the compression coefficient gain is determined as the first data D1.
And step S104, searching the second data D2 corresponding to the first data D1 in a pre-established lookup table, wherein the lookup table comprises binary second data D2 obtained by shifting the reciprocal of each positive integer from n bits 0 to n bits 1 of the binary system by S bits.
For example, if n is a fixed positive integer 10, the lookup table includes binary value ranges 0000000000 to 1111111111 (i.e. decimal 0-2)10-1) left-shifting the reciprocal of each positive integer by s bits resulting in binary second data D2. The first data D1 may be any positive integer in a lookup table, and since the reciprocal of each positive integer in the lookup table is a decimal, the FPGA stores the second data D2 obtained by shifting the decimal left by s bits.
According to the stepSudden, D2 ═ 1/D1)<<s＝(1/D1)×2s(formula 3)
In step S106, the second data D2 corresponding to the first data D1 is shifted to the right by m minus n bits to determine the third data D3.
That is, D3 ═ D2>>(m-n)＝D2×2-m+n(formula 4)
Step S108, compressing the data DcmpMultiplication is carried out with the third data D3 to obtain decompressed data Dun-cmp。
I.e. Dun-cmp＝DcmpX D3 (formula 5)
The following can be obtained according to the above equations 1 to 5:
Dorg＝Dcmp×(1/gain)×2s(formula 6)
Dun-cmp＝Dcmp×(1/D1)×2s-m+n(formula 7)
gain＝D1×2m-n(formula 8)
From the above equations 6 to 8, it can be seen that: decompressing data Dun-cmpApproximately equal to the original data Dorg。
It should be noted that, in formula 2, since the first data D1 is binary data obtained by right shifting the compression coefficient gain by m minus n bits, that is, the first data D1 is data obtained by discarding shifted m minus n bits by the compression coefficient gain, the reciprocal of the first data D1 is only approximately equal to the reciprocal of the compression coefficient gain, and the resulting decompressed data Dun-cmpApproximately equal to the original data Dorg。
As can be seen from the above equations 6, 7 and 9: decompressing data Dun-cmpApproximately equal to the original data Dorg。
Although equation 9 includes D1 being equal to gain, the binary data obtained by taking the reciprocal of the first data D1 and the compression coefficient gain may have different bits, and the accuracy of the binary data is directly affected by the bits, so that the reciprocal of the first data D1 is also only approximately equal to the reciprocal of the compression coefficient gain, and the resulting decompressed data D is obtainedun-cmpApproximately equal to the original data Dorg。
For the compression coefficient gain with m bits, if the existing FPGA table lookup method is used to perform the data decompression method, 2 needs to be stored in the lookup tablemIf the data decompression method provided by the application is adopted, 2 is stored in the lookup table at mostnAnd the reciprocal of the time is greatly saved, the storage resource of the FPGA is greatly saved, and the search time is reduced.
Thus, although the data D is decompressedun-cmpWith respect to the original data DorgThe loss exists, but the data decompression method greatly saves the calculation time and calculation resources of the FPGA decompressed data and accelerates the processing speed of the FPGA decompressed data. When the loss condition of the decompressed data relative to the original data is within the acceptable range of the user (for example, the distortion condition of the decompressed video signal and the decompressed audio signal is not obvious and can be accepted by the user), the data decompression method provided by the embodiment of the application can be well applied to the field of decompression processing (such as video, audio and the like) for the data in the FPGA, and has the advantages of obtaining the decompressed data meeting the user requirements and ensuring high processing speed and efficiency.
It should be noted that the data decompression method applied to the FPGA provided in the embodiment of the present application may be used for any data type that allows a certain distortion of a decompression result with respect to original data, for example, a video signal, an audio signal, and the like, and this is not limited in this application.
Having described the basic principles of the present application, various non-limiting embodiments of the present application are described in detail below.
In some embodiments, data D is compressedcmpIs the original data DorgAnd the data obtained by multiplication with the compression coefficient gain shifted to the right by s bits and addition and/or subtraction. For example, the compression formula used for compressing the image by means of piecewise linearization is: dcmp＝(Dorg-xi)×(gi×2-s)+yiWhere i is the original data D in the image compression processorgThe number of each segment obtained by the segmentation processing，i＝1,2,3....，xiIs the minimum value of each piece of original data, yiIs xiCorresponding compressed data, giIs the compression factor used for the compression process of each piece of original data. In such embodiments, since the compression process also adopts addition, subtraction, etc., step S108 will compress the data DcmpMultiplication is carried out with the third data D3 to obtain decompressed data Dun-cmpThe method comprises the following steps: will compress data DcmpAfter multiplication with the third data D3, the inverse operation of the above addition and/or subtraction is performed to obtain decompressed data Dun-cmp。
In some embodiments, raw data DorgIs a pixel value of an image, for example, a video signal to be transmitted is a still image signal, and raw data subjected to compression processing is a pixel value of an image (i.e., a gradation value of each pixel).
In some embodiments, raw data DorgIs the pixel value of a High Dynamic Range Imaging (HDR) image. In the HDR image, the bit width of the pixel value is large, for example, 24 bits, and the required transmission bandwidth is high, in order to implement transmission under the limited bandwidth, each pixel value is compressed from 24 bits to 12 bits and then transmitted, and after receiving the data, the FPGA restores the 12 bits of data back to 24 bits through decompression processing.
In the data decompression method applied to the FPGA, the fixed value n is a preset numerical value, the size of the fixed value n determines the data amount stored in the lookup table, and the smaller the value of n is, the less resources of the FPGA are occupied, but the larger the error caused by calculation is, that is, the more serious the distortion of the decompressed data relative to the original data is. In specific application, the size of the fixed value n can be determined by comprehensively considering factors such as the demand on memory resources, the demand on data distortion and the like.
Application scene overview
Fig. 2 shows a structural framework of an autonomous vehicle, which includes the following image acquisition processes: the imaging device 21 mounted on the vehicle body captures images of the driving environment and transmits these images in real time to the image processing server 22, and the image processing server 22 performs further visual analysis processing.
The imaging device 21 includes an image sensor 211 and an FPGA 212, where the two transmit data through a Mobile Industry Processor Interface (MIPI), and are limited by a transmission rate and a bandwidth of the MIPI Interface, the image sensor 211 needs to compress an image before transmitting the image to the FPGA 212, and the FPGA 212 decompresses the image after receiving the image, and the specific process is as follows:
after the image sensor 211 shoots an image, the original data of the image is compressed by using a preset compression coefficient to obtain compressed data, and the compression coefficient and the compressed data are sent to the FPGA 212; the FPGA 212 decompresses the compressed data using the compression coefficient to obtain decompressed data, and the decompression processing process adopts the data decompression method applied to the FPGA 212 provided in the embodiment of the present application.
It should be noted that the above application scenarios are only presented to facilitate understanding of the spirit and principles of the present application, and the embodiments of the present application are not limited in this respect. Rather, embodiments of the present application may be applied to any scenario where applicable.
Exemplary method
With reference to the application scenario shown in fig. 2, a data decompression method applied to an FPGA provided in the embodiment of the present application is described by the following embodiment.
An image sensor captures a driving environment to obtain an HDR image with a bit width of 24 bits, and compresses 24-bit image data into 12-bit image data by piecewise linearization before outputting the image, thereby obtaining compressed data.
The compression process adopts a compression formula Dcmp＝(Dorg-xi)×(gi×2-24)+yiAs shown in fig. 3, wherein i is the original data D in the image compression processorgThe number of each segment, i.e., 1,2,3., x, obtained by the segmentation processiIs the minimum value of each piece of original data, yiIs xiCorresponding compressed data, giIs the compression factor, g, used for compression processing of each piece of original dataiBit width of 24, DcmpIs the original data DorgThe corresponding compressed data.
The image sensor will compress data DcmpCompression factor giMinimum value x of each piece of original dataiAnd its corresponding compressed data yiSending to FPGA, FPGA utilizes the data and according to decompression formula Dun-cmp＝(Dcmp-yi)/gi×224+xiCalculating to obtain decompressed data Dun-cmpThe decompression process is specifically as follows:
step A100, judging the compression coefficient giIs greater than a predetermined fixed value n of 10, the compression factor g is reducediData obtained by right shifting 14 bits (24 bits minus 10 bits) is determined as first data D1; wherein, D1 ═ gi>>14＝gi×2-14；
Step A200, searching a second data D2 corresponding to the first data D1 in a pre-established lookup table; wherein D2 ═ 1/D1)<<24＝(1/D1)×224；
Step A300, determining a value obtained by right shifting 14 bits of the second data D2 corresponding to the first data D1 as third data D3; wherein D3-D2>>14＝D2×2-14；
Step A400, calculating Dcmp-yi；
Step A500, mixing (D)cmp-yi) Multiplication with third data D3, i.e. (D)cmp-yi)×D3＝(Dcmp-yi)×D2×2-14；
Step A600, calculate (D)cmp-yi)×D2×2-14+xiObtaining decompressed data Dun-cmp(ii) a I.e. Dun-cmp＝(Dcmp-yi)×D2×2-14+xi。
And the FPGA transmits the data obtained by decompression to an image processing server, and the image processing server performs further visual analysis processing.
The following experimental verification is performed in the embodiment of the application: by using the data decompression method provided by the embodiment of the application, the FPGA decompresses the compressed image with the pixel bit width of 12 bits to obtain the decompressed image with the pixel bit width of 24 bits, and the whole decompression process only needs the delay of 6 clocks; and the IP core carried by the current FPGA development platform is used for division operation, the compressed image with the pixel bit width of 12 bits is decompressed to obtain a decompressed image with the pixel bit width of 24 bits, and the time delay of the whole decompression process is up to 52 clocks.
In addition, by using the data decompression method provided by the embodiment of the application, the definition degree of the image obtained by FPGA decompression is almost consistent with that of the image obtained by decompressing the image by adopting the IP core of the FPGA development platform to perform division operation, and the error is within 0.1%.
Therefore, the data decompression method applied to the FPGA can effectively save the calculation time and the calculation resources on the premise of ensuring the image quality.
Exemplary device
Based on the same invention, an embodiment of the present application further provides an FPGA, including: the configurable logic block comprises a shift register and a memory.
The memory is used for storing a pre-established lookup table, and the lookup table comprises binary second data obtained by shifting the reciprocal of each positive integer from n bits 0 to n bits 1 of the binary by s bits to the left;
the configurable logic block is to:
acquiring compressed data and a compression coefficient; the compressed data is obtained by multiplying original data and a compression coefficient which is shifted to the right by s bits; the compressed data, the original data and the compression coefficient are all binary data, and the compression coefficient is m bits;
when m is larger than n, determining data obtained by right shifting a compression coefficient by m minus n bits as first data by operating a shift register; when m is judged to be less than or equal to n, determining a compression coefficient as first data by operating a shift register; wherein m, n and s are positive integers, and n is a fixed value;
searching second data corresponding to the first data in a lookup table;
determining a numerical value obtained by right shifting second data corresponding to the first data by m minus n bits as third data by operating a shift register;
and performing multiplication operation on the compressed data and the third data to obtain decompressed data.
In some embodiments, the compressed data is obtained by multiplying the original data by the compression coefficient which is shifted to the right by s bits and then performing addition and/or subtraction;
then, the step of multiplying the compressed data by the third data by the configurable logic block to obtain decompressed data includes:
and after the compressed data and the third data are subjected to multiplication operation, performing addition operation and/or inverse operation of subtraction operation to obtain decompressed data.
In some embodiments, the raw data is audio data.
In some embodiments, the raw data is video data.
In some embodiments, the raw data is pixel values of an image.
In some embodiments, the image is a high dynamic range HDR image.
The working principle of the FPGA provided in the embodiment of the present application and the data decompression method applied to the FPGA shown in fig. 1 are implemented based on the same inventive concept, and have the same non-limiting implementation manner, and specifically refer to the description of the data decompression method applied to the FPGA shown in fig. 1 in the foregoing exemplary method, which is not described herein again.
Based on the same invention, as shown in fig. 4, an embodiment of the present application further provides an image forming apparatus, including: an image sensor 41 and an FPGA 42.
The image sensor 41 is configured to capture an image, perform multiplication on original data of the image by using a preset compression coefficient to obtain compressed data, and send the compression coefficient and the compressed data to the FPGA 42; the FPGA 42 is operative to perform the various steps of the data decompression method applied to the FPGA 42 as shown in figure 1.
The working principle of the imaging device shown in fig. 4 is implemented based on the same inventive concept as the data decompression method applied to the FPGA 42 shown in fig. 1, and has the same non-limiting embodiment, and reference may be specifically made to the description of the data decompression method applied to the FPGA 42 shown in fig. 1 in the foregoing exemplary method, and details are not repeated here.
Based on the same invention, as shown in fig. 2, an embodiment of the present application further provides an automobile, including: an image processing server 22 and an imaging device 21.
The structure and operation principle of the imaging device 21 are described with reference to the imaging device shown in fig. 4, and will not be described herein again.
The image processing server 22 receives the decompressed data output from the imaging apparatus 21 and performs visual analysis processing thereon.
The automobile can be an automatic driving vehicle, namely a vehicle which is realized by utilizing an automatic driving technology and has manned functions (such as types of family cars, buses and the like), cargo-loaded functions (such as types of ordinary trucks, van trucks, closed trucks, tank trucks, flat trucks, container vans, dump trucks, trucks with special structures and the like) or special rescue functions (such as types of fire trucks, ambulances and the like).
The image acquisition process of the automobile shown in fig. 2 is implemented based on the same inventive concept as the data decompression method applied to the FPGA shown in fig. 1, and has the same non-limiting embodiment, and reference may be specifically made to the description of the data decompression method applied to the FPGA shown in fig. 1 in the foregoing exemplary method, and details thereof are not repeated here.
Based on the same inventive concept, the embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the data decompression method applied to the FPGA provided by the embodiment of the present application is provided. The computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. In some embodiments, the computer-readable storage medium may be: an electrical connection having one or more wires, a portable disk, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
Although the present application provides method steps as described in an embodiment or flowchart, additional or fewer steps may be included based on conventional or non-inventive efforts. The order of steps recited in the embodiments is merely one manner of performing the steps in a multitude of orders and does not represent the only order of execution. When an actual apparatus or client product executes, it may execute sequentially or in parallel (e.g., in the context of parallel processors or multi-threaded processing) according to the embodiments or methods shown in the figures.
The apparatuses or modules illustrated in the above embodiments may be implemented by a computer chip or an entity, or by a product with certain functions. For convenience of description, the above devices are described as being divided into various modules by functions, and are described separately. The functionality of the modules may be implemented in the same one or more software and/or hardware implementations of the present application. Of course, a module that implements a certain function may be implemented by a plurality of sub-modules or sub-units in combination.
The methods, apparatus or modules described herein may be implemented in computer readable program code to a controller implemented in any suitable manner, for example, the controller may take the form of, for example, a microprocessor or processor and a computer readable medium storing computer readable program code (e.g., software or firmware) executable by the (micro) processor, logic gates, switches, Application Specific Integrated Circuits (ASICs), programmable logic controllers and embedded microcontrollers, examples of which include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicone Labs C8051F320, the memory controller may also be implemented as part of the control logic for the memory. Those skilled in the art will also appreciate that, in addition to implementing the controller as pure computer readable program code, the same functionality can be implemented by logically programming method steps such that the controller is in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Such a controller may therefore be considered as a hardware component, and the means included therein for performing the various functions may also be considered as a structure within the hardware component. Or even means for performing the functions may be regarded as being both a software module for performing the method and a structure within a hardware component.
Some of the modules in the apparatus described herein may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, classes, etc. that perform particular tasks or implement particular abstract data types. The application may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.
From the above description of the embodiments, it is clear to those skilled in the art that the present application can be implemented by software plus necessary hardware. Based on such understanding, the technical solutions of the present application may be embodied in the form of software products or in the implementation process of data migration, which essentially or partially contributes to the prior art. The computer software product may be stored in a storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, mobile terminal, server, or network device, etc.) to perform the methods described in the various embodiments or portions of the embodiments of the present application.
The embodiments in the present specification are described in a progressive manner, and the same or similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. All or portions of the present application are operational with numerous general purpose or special purpose computing system environments or configurations. For example: personal computers, server computers, hand-held or portable devices, tablet-type devices, mobile communication terminals, multiprocessor systems, microprocessor-based systems, programmable electronic devices, network PCs, minicomputers, mainframe computers, distributed computing environments that include any of the above systems or devices, and the like.
While the present application has been described with examples, those of ordinary skill in the art will appreciate that there are numerous variations and permutations of the present application without departing from the spirit of the application, and it is intended that the appended claims encompass such variations and permutations without departing from the spirit of the application.
Claims (14)
1. A data decompression method applied to FPGA is characterized by comprising the following steps:
acquiring compressed data and a compression coefficient; the compressed data is obtained by multiplying original data and the compression coefficient which is shifted to the right by s bits; the compressed data, the original data and the compression coefficient are binary data, and the compression coefficient is m bits;
when the digit m of a compression coefficient is judged to be larger than a preset fixed value n, determining data obtained by right shifting the compression coefficient by m minus n bits as first data; when the bit number m of a compression coefficient is judged to be less than or equal to the fixed value n, determining the compression coefficient as first data; wherein m, n and s are positive integers;
searching second data corresponding to the first data in a pre-established lookup table; the lookup table comprises binary second data obtained by shifting the reciprocal of each positive integer from n bits 0 to 1 to the left by s bits;
determining a numerical value obtained by right shifting the second data corresponding to the first data by m minus n bits as third data;
and performing multiplication operation on the compressed data and the third data to obtain decompressed data.
2. The method of claim 1, wherein the raw data is an audio signal.
3. The method of claim 1, wherein the raw data is a video signal.
4. A method according to claim 3, wherein the raw data is pixel values of an image.
5. The method of claim 4, wherein the image is a High Dynamic Range (HDR) image.
6. A data decompression method applied to FPGA is characterized by comprising the following steps:
acquiring compressed data and a compression coefficient; the compressed data is obtained by performing addition operation and/or subtraction operation on original data and the compression coefficient which is shifted to the right by s bits after multiplication operation; the compressed data, the original data and the compression coefficient are binary data, and the compression coefficient is m bits;
when the digit m of a compression coefficient is judged to be larger than a preset fixed value n, determining data obtained by right shifting the compression coefficient by m minus n bits as first data; when the bit number m of a compression coefficient is judged to be less than or equal to the fixed value n, determining the compression coefficient as first data; wherein m, n and s are positive integers;
searching second data corresponding to the first data in a pre-established lookup table; the lookup table comprises binary second data obtained by shifting the reciprocal of each positive integer from n bits 0 to 1 to the left by s bits;
determining a numerical value obtained by right shifting the second data corresponding to the first data by m minus n bits as third data;
and after the compressed data and the third data are subjected to multiplication operation, performing inverse operation of the addition operation and/or the subtraction operation to obtain decompressed data.
7. The method of claim 6, wherein the raw data is an audio signal.
8. The method of claim 6, wherein the raw data is a video signal.
9. The method of claim 8, wherein the raw data is pixel values of an image.
10. The method of claim 9, wherein the image is a High Dynamic Range (HDR) image.
11. An FPGA, wherein the FPGA is configured to perform the steps of the data decompression method applied to the FPGA according to any one of claims 1 to 10.
12. An image forming apparatus, characterized by comprising: an image sensor and an FPGA;
the image sensor is used for shooting an image, multiplying original data of the image by a preset compression coefficient to obtain compressed data, and sending the compression coefficient and the compressed data to the FPGA;
the FPGA is used for executing the steps of the data decompression method applied to the FPGA according to any one of claims 1, 3-6 and 8-10.
13. An automobile, comprising: an image processing server and the imaging apparatus according to claim 12;
and the image processing server receives the decompressed data output by the imaging equipment and performs visual analysis processing on the decompressed data.
14. A computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and the instructions, when executed by a computer, implement the data decompression method applied to the FPGA according to any one of claims 1 to 10.
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| CN201811622214.7A CN111385578B (en) | 2018-12-28 | 2018-12-28 | Data decompression method applied to FPGA, imaging device and automobile |
| PCT/CN2019/077052 WO2020133692A1 (en) | 2018-12-28 | 2019-03-05 | Data decompression method for fpga, and imaging device and automobile |
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| CN201811622214.7A CN111385578B (en) | 2018-12-28 | 2018-12-28 | Data decompression method applied to FPGA, imaging device and automobile |
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| CN102566963A (en) * | 2010-12-21 | 2012-07-11 | 普天信息技术研究院有限公司 | Method for processing data in field programmable gate array (FPGA) |
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