CN111384946A - Method, circuit and clock generating device for preventing clock overshoot of phase-locked loop - Google Patents

Method, circuit and clock generating device for preventing clock overshoot of phase-locked loop Download PDF

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Publication number
CN111384946A
CN111384946A CN201811644487.1A CN201811644487A CN111384946A CN 111384946 A CN111384946 A CN 111384946A CN 201811644487 A CN201811644487 A CN 201811644487A CN 111384946 A CN111384946 A CN 111384946A
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phase
locked loop
signal
state
frequency
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熊江
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Actions Zhuhai Technology Co ltd
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Actions Zhuhai Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

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Abstract

The invention relates to a method, a circuit and a clock generating device for preventing a phase-locked loop clock from overshooting, wherein the method for preventing the phase-locked loop clock from overshooting comprises the following steps: acquiring an input signal and a feedback signal of a phase-locked loop, and determining the current state of the phase-locked loop according to the input signal and the feedback signal, wherein the state of the phase-locked loop comprises a locked state and an unlocked state; when the current state is the unlocking state, performing frequency reduction processing on an output signal of the phase-locked loop, and taking the signal subjected to frequency reduction processing as a clock signal; when the current state is the locking state, the output signal of the phase-locked loop is directly used as a clock signal. By implementing the technical scheme of the invention, the available clock can be provided more reliably and quickly at lower cost, the software running efficiency can be improved, and the power consumption can be saved.

Description

Method, circuit and clock generating device for preventing clock overshoot of phase-locked loop
Technical Field
The invention relates to the field of phase-locked loops, in particular to a method, a circuit and a clock generation device for preventing phase-locked loop clock overshoot.
Background
The Phase-Locked Loop is a feedback control circuit, and is called a Phase-Locked Loop (PLL). He uses an externally input reference signal to control the frequency and phase of the oscillating signal inside the loop. In the process of processing electronic signals, the phase-locked loop can realize automatic tracking of the frequency of an output signal to the frequency of an input signal, so the phase-locked loop is widely applied to a closed-loop tracking circuit. In the field of clocks, clock phase-locked loops are widely used for clock generation.
The clock phase locked loop shown in connection with fig. 1 generally consists of several parts: phase detector PD, loop filter LPF, voltage controlled oscillator VCO and loop frequency divider LPDIV. The phase detector PD is a unit that performs phase comparison, and is used to compare the phase difference between the input signal Fin and the feedback signal Fback, and the output voltage thereof is proportional to the phase difference between the two input signals. The LPF is an active or passive low pass filter, and functions to filter out high frequency components (including mixing and other high frequency noise) in the output voltage of the phase detector, to perform smoothing filtering, and finally output a control signal Vc, which usually consists of a resistor, a capacitor, or an inductor, and sometimes also includes an operational amplifier. The voltage-controlled oscillator VCO is an oscillator whose oscillation frequency is controlled by a control voltage, and the oscillation frequency of the oscillator has a linear relationship with the control voltage, and the voltage-controlled oscillator VCO outputs a corresponding oscillation frequency Fosc according to a control signal Vc. The loop divider LPDIV determines the multiplying factor of the input and output clocks, but may be an integer or a decimal. The relationship is Fosc ═ n (lpdiv) × Fin. For the clock phase locked loop, the output frequency Fout is the oscillator frequency Fosc.
It is known that the equation describing the second order PLL is a second order nonlinear differential equation (observing the locking process). the VCO in the second order PLL can be considered as an ideal integrator, so from a system perspective, if the LPF is first order, the PLL can be considered as a second order system.for a second order system, there is a natural frequency ω n and a damping coefficient ξ. if the parameters inside the system are suddenly changed, an intrinsic damping oscillation will occur according to the characteristics of the system.under the same LPF condition, the higher the sensitivity of the VCO is, the smaller ξ the faster the lock is, but the larger the amplitude of the damping oscillation is, the larger ξ the amplitude of the damping oscillation is small, the larger the damping oscillation is, the larger the amplitude is greater than 1 the damping oscillation is, but the lock time becomes very long, and the PLL usually needs to lock the amplitude as soon as possible.
When the system changes the frequency dividing ratio, the PLL needs to be locked again, and the locking action needs a certain time. For example, when the input reference frequency of a phase-locked loop is 12.5MHz, and the divider coefficient is changed from 31 to 60, as shown in fig. 2, the output frequency should be changed from 387.5MHz (12.5 × 31) to 750MHz (12.5 × 60), the second-order damped oscillation characteristic is clearly seen when the frequency is changed, and the output frequency of 780MHz exists during the overshoot due to oscillation, which is larger than the target value of 750MHz, and if the output frequency of 780MHz exceeds the highest operating frequency of the system (for example, only 770MHz), the system may be faulty, and even broken down may occur.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a method, a circuit and a clock generation apparatus for preventing a phase-locked loop clock from overshooting, aiming at the defect that the overshoot occurs when the PLL output clock is adjusted by changing a loop divider in the prior art, so as to reduce the overshoot risk.
The technical scheme adopted by the invention for solving the technical problems is as follows: constructing a method for preventing clock overshoot of a phase-locked loop, wherein the phase-locked loop comprises a phase discriminator, a low-pass filter, a voltage-controlled oscillator and a loop frequency divider, and when the frequency of an output signal of the phase-locked loop is changed by changing a frequency division coefficient of the loop frequency divider, the following steps are carried out:
acquiring an input signal and a feedback signal of a phase-locked loop, and determining the current state of the phase-locked loop according to the input signal and the feedback signal, wherein the state of the phase-locked loop comprises a locked state and an unlocked state;
when the current state is the unlocking state, performing frequency reduction processing on an output signal of the phase-locked loop, and taking the signal subjected to frequency reduction processing as a clock signal;
when the current state is the locking state, the output signal of the phase-locked loop is directly used as a clock signal.
Preferably, determining the current state of the phase locked loop from the input signal and the feedback signal comprises:
comparing the input signal with the feedback signal and judging whether the difference between the input signal and the feedback signal is smaller than a threshold value;
if the difference between the two is smaller than the threshold value within the preset time period, determining that the current state of the phase-locked loop is a locked state;
and if the difference between the two is not less than the threshold value within the preset time period, determining that the current state of the phase-locked loop is the lock losing state.
Preferably, the down-converting the output signal of the phase-locked loop includes:
and performing frequency reduction processing on the output signal of the phase-locked loop through a frequency reduction device.
Preferably, the method further comprises the following steps:
acquiring a frequency division control signal of a loop frequency divider of the phase-locked loop, and determining a frequency reduction coefficient of the frequency reduction device according to the frequency division control signal, wherein the frequency reduction coefficient is greater than 1.1.
The invention also constructs a circuit for preventing the clock overshoot of the phase-locked loop, wherein the phase-locked loop comprises a phase discriminator, a low-pass filter, a voltage-controlled oscillator and a loop frequency divider, and the circuit for preventing the clock overshoot of the phase-locked loop comprises:
the state detection module is used for acquiring an input signal and a feedback signal of the phase-locked loop and determining the current state of the phase-locked loop according to the input signal and the feedback signal, wherein the state of the phase-locked loop comprises a locked state and an unlocked state;
the safety frequency reduction module is used for performing frequency reduction processing on an output signal of the phase-locked loop when the current state is an unlocked state, and taking the signal subjected to the frequency reduction processing as a clock signal; when the current state is the locking state, the output signal of the phase-locked loop is directly used as a clock signal.
Preferably, the state detection module is configured to compare the input signal with the feedback signal, determine whether a difference between the input signal and the feedback signal is smaller than a threshold, and determine that a current state of the phase-locked loop is a locked state if the difference between the input signal and the feedback signal is smaller than the threshold within a preset time period; and if the difference between the two is not less than the threshold value within the preset time period, determining that the current state of the phase-locked loop is the lock losing state.
Preferably, the state detection module includes: the phase-locked loop comprises a first delayer, a second delayer, a first D trigger, a second D trigger and an AND gate, wherein the input end of the first delayer is connected with the input end of a phase-locked loop so as to be used for inputting an input signal of the phase-locked loop, the output end of the first delayer is connected with the clock end of the first D trigger, the data input end of the first D trigger is connected with the feedback end of the phase-locked loop so as to be used for inputting a feedback signal of the phase-locked loop, and the data output end of the first D trigger is connected with the first input end of the AND gate; the input end of the second time delay is connected with the feedback end of the phase-locked loop so as to input a feedback signal of the phase-locked loop, the output end of the second time delay is connected with the clock end of the second D trigger, the data input end of the second D trigger is connected with the input end of the phase-locked loop so as to input an input signal of the phase-locked loop, the data output end of the second D trigger is connected with the second input end of the AND gate, and the output end of the AND gate is used for outputting a state signal.
Preferably, the safety frequency-reducing module includes a frequency-reducing device and a switch, wherein an input end of the frequency-reducing device and a first input end of the switch are both connected to an output end of the phase-locked loop for inputting an output signal of the phase-locked loop, an output end of the frequency-reducing device is connected to a second input end of the switch, a control end of the switch is connected to an output end of the and gate, and an output end of the switch is used for outputting a clock signal.
Preferably, the method comprises the following steps:
the frequency reduction control module is used for acquiring a frequency division control signal of a loop frequency divider of the phase-locked loop and determining a frequency reduction coefficient of the frequency reduction device according to the frequency division control signal, wherein the frequency reduction coefficient of the frequency reduction device is greater than 1.1.
The invention also constructs a clock generating device, which comprises a phase-locked loop, wherein the phase-locked loop comprises a phase discriminator, a low-pass filter, a voltage-controlled oscillator and a loop frequency divider, and the clock generating device also comprises the circuit for preventing the clock overshoot of the phase-locked loop.
By implementing the technical scheme of the invention, when the frequency of the output signal of the phase-locked loop is adjusted by changing the frequency division coefficient of the loop frequency divider, the current state of losing lock can be judged according to the input signal and the feedback signal during the period that the phase-locked loop is not stably locked, and the output signal of the phase-locked loop is subjected to frequency reduction treatment so as to eliminate the risk of overshoot. And, once it is judged that the lock state is currently in accordance with the input signal and the feedback signal, the target frequency signal that has been stabilized is output. Therefore, each frequency switching time is self-adaptive and the system is shortest, and the highest-speed safe clock which can be provided currently can be provided to the system at zero cost during the switching period, so that the CPU processing capacity is exerted, and the subsequent software programs can be operated at the highest-speed and safe frequency. Therefore, compared with the prior art, the method can provide the available clock with lower cost, more reliability and higher speed, can improve the software running efficiency and save the power consumption.
Drawings
In order to illustrate the embodiments of the invention more clearly, the drawings that are needed in the description of the embodiments will be briefly described below, it being apparent that the drawings in the following description are only some embodiments of the invention, and that other drawings may be derived from those drawings by a person skilled in the art without inventive effort. In the drawings:
FIG. 1 is a logical block diagram of a phase locked loop of the prior art;
FIG. 2 is a simulated graph of clock signal versus time during relocking for the phase locked loop of FIG. 1;
FIG. 3 is a flowchart of a first embodiment of a method for preventing clock overshoot in a phase locked loop according to the present invention;
FIG. 4 is a simulation of clock signal versus time during relocking of a phase locked loop using the method of FIG. 3;
FIG. 5 is a logic structure diagram of a first embodiment of the clock generation apparatus of the present invention;
FIG. 6 is a logic diagram of a first embodiment of the status detection module of FIG. 5;
FIG. 7 is a logical block diagram of a second embodiment of the status detection module of FIG. 5;
FIG. 8 is a logical block diagram of a third embodiment of the status detection module of FIG. 5;
FIG. 9 is a logical block diagram of a fourth embodiment of the status detection module of FIG. 5;
FIG. 10 is a logical block diagram of a fifth embodiment of the status detection module of FIG. 5;
fig. 11 is a logic structure diagram of the first embodiment of the secure down-conversion module in fig. 5.
Detailed DescriptionThe following detailed description of embodiments of the invention refers to the accompanying drawings.
The embodiments/examples described herein are specific embodiments of the present invention, are intended to be illustrative of the concepts of the present invention, are intended to be illustrative and exemplary, and should not be construed as limiting the embodiments and scope of the invention. In addition to the embodiments described herein, those skilled in the art will be able to employ other technical solutions which are obvious based on the disclosure of the claims and the specification of the present application, and these technical solutions include those which make any obvious replacement or modification of the embodiments described herein, and all of which are within the scope of the present invention.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
Fig. 3 is a flowchart of a first embodiment of a method for preventing clock overshoot of a phase-locked loop according to the present invention, and first illustrates that the phase-locked loop includes a phase detector, a low-pass filter, a voltage-controlled oscillator, and a loop divider. In this embodiment, when the frequency of the phase-locked loop output signal is changed by changing the division coefficient of the loop divider, the following steps are performed:
s10, acquiring an input signal and a feedback signal of a phase-locked loop, and determining the current state of the phase-locked loop according to the input signal and the feedback signal, wherein the state of the phase-locked loop comprises a locked state and an unlocked state;
in this step, it should be noted first that the frequency of the output signal of the phase-locked loop is usually changed by changing the frequency division coefficient of the loop divider, and therefore, the frequency division coefficient can be used to characterize the frequency relationship between the output signal and the input signal. The phase locked loop is in lock condition and the rising edges of its input signal and feedback signal are aligned (phase difference is constant). When the frequency division coefficient of the loop frequency divider is changed, the feedback signal of the phase-locked loop changes, and whether the current state is in a locked state or an unlocked state can be determined by detecting the change of the feedback signal (the frequency of the input signal is unchanged).
S20, when the current state is the unlocking state, performing frequency reduction processing on an output signal of the phase-locked loop, and taking the signal subjected to the frequency reduction processing as a clock signal;
in this step, since the phase-locked loop may overshoot in the out-of-lock state, the output signal of the phase-locked loop in the out-of-lock state may be subjected to a frequency reduction process, that is, the damped oscillation frequency is forcibly reduced and then used as the clock signal, so that the overshoot may be prevented.
And S30, when the current state is the locking state, directly taking the output signal of the phase-locked loop as a clock signal.
Referring to fig. 4, first, the input signal of the phase-locked loop is assumed to have a frequency of 12.5MHz, and the output signal is assumed to be down-converted by a factor of 2 during the loss of lock. When the frequency division coefficient of the loop divider is changed from 31 to 60, in the process of changing the frequency of the output signal from 387.5MHz (12.5 × 31) to 750MHz (12.5 × 60), as is apparent from the figure, the original overshoot frequency point 780MHz is changed to 390MHz due to the adoption of 2-time down-conversion in the out-of-lock state, so that overshoot does not occur, and the phase-locked loop outputs the output signal of 750MHz after re-stabilization.
By implementing the technical scheme of the embodiment, when the frequency of the output signal of the phase-locked loop is adjusted by changing the frequency division coefficient of the loop frequency divider, the current out-of-lock state of the phase-locked loop can be judged according to the input signal and the feedback signal during the period that the phase-locked loop is not stably locked, and the output signal of the phase-locked loop is subjected to frequency reduction processing to eliminate the risk of overshoot. And, once it is judged that the current state is in the lock state according to the input signal and the feedback signal, outputting the stabilized target frequency signal. Therefore, each frequency switching time is self-adaptive and the system is shortest, and the highest-speed safe clock which can be provided currently can be provided to the system at zero cost during the switching period, so that the CPU processing capacity is exerted, and the subsequent software programs can be operated at the highest-speed and safe frequency. Therefore, compared with the prior art, the method can provide the available clock with lower cost, more reliability and higher speed, can improve the software running efficiency and save the power consumption.
In an alternative embodiment, in step S10, the current state of the phase-locked loop may be determined according to the following: comparing the input signal with the feedback signal and judging whether the difference between the input signal and the feedback signal is smaller than a threshold value; if the difference between the two is smaller than the threshold value within the preset time period, determining that the current state of the phase-locked loop is a locked state; and if the difference between the two is not less than the threshold value within the preset time period, determining that the current state of the phase-locked loop is the lock losing state.
It should be noted that the threshold is determined according to the characteristics of the PLL and the requirement of locking accuracy, and may be set according to the requirement, for example, one clock cycle of the oscillator.
In an alternative embodiment, in step S20, the down-conversion process may be performed according to the following manner: the frequency reduction device is used for carrying out frequency reduction processing on the output signal of the phase-locked loop, and the frequency reduction can be realized theoretically. Generally, the frequency reduction coefficient of the frequency reduction device is set to be more than 1.1. In this embodiment, it should be noted that the coefficient of the downconversion frequency is determined by the damping factor theoretically, and the conventional overshoot is generally between 10% and 20% according to the actual circuit, so that setting the coefficient of the downconversion frequency to be greater than 1.1 can reduce the overshoot risk, and preferably, the coefficient of the downconversion frequency can be selected to be 1.5.
Further, since the magnitude of the overshoot is also related to the frequency at the start and end of the lock, for example, for a phase locked loop with an input signal frequency of 12.5MHz, the magnitude of the overshoot occurring when the division factor of its loop divider changes from 31 to 32 and when the division factor changes from 31 to 60 is not the same, if the division factor selects the same value in both cases, the following situations may occur: if the frequency division coefficient is too small, the overshoot risk cannot be completely eliminated; or, if the division factor is too large, the highest speed secure clock signal cannot be provided. Therefore, in an alternative embodiment, before step S20, the method further includes: and acquiring a frequency division control signal of a loop frequency divider of the phase-locked loop, and determining a frequency reduction coefficient of the frequency reduction device according to the frequency division control signal, wherein the frequency division control signal is used for indicating the change of the frequency division coefficient of the loop frequency divider. In this embodiment, the down-conversion factor is not a fixed value, but an adaptive variable value, and it can be determined according to the frequency division control signal of the loop frequency divider, so that the overshoot risk can be further reduced, and the highest-speed safe clock which can be provided currently can be provided to the system.
Fig. 5 is a logical block diagram of a first embodiment of the clock generation apparatus according to the present invention, which includes a general phase-locked loop 10 and a circuit for preventing the phase-locked loop from clock overshooting. The phase-locked loop 10 includes a phase detector 11, a low-pass filter 12, a voltage-controlled oscillator 13, and a loop frequency divider 14, and it should be understood that the functions, specific implementations, and logic relationships of the phase detector 11, the low-pass filter 12, the voltage-controlled oscillator 13, and the loop frequency divider 14 in the phase-locked loop 10 may adopt known methods in the art, and are not described herein again. The circuit for preventing the clock overshoot of the phase-locked loop specifically comprises a state detection module 20 and a safety frequency reduction module 30, wherein the state detection module 20 is used for acquiring an input signal and a feedback signal of the phase-locked loop and determining the current state of the phase-locked loop according to the input signal and the feedback signal, and the states of the phase-locked loop comprise a locked state and an unlocked state; the safety frequency-reducing module 30 is configured to, when the current state is an unlocked state, perform frequency-reducing processing on an output signal of the phase-locked loop, and use the signal subjected to the frequency-reducing processing as a clock signal; when the current state is the locking state, the output signal of the phase-locked loop is directly used as a clock signal.
In this embodiment, the status detecting module 20 monitors the input signal Fin and the feedback clock Fback of the phase-locked loop 10, and outputs the status signal LCK according to the difference between the input signal Fin and the feedback clock Fback, for example, LCK is 0 to represent the out-of-lock status, and LCK is 1 to represent the lock status. The safety down-conversion module 30 determines whether to down-convert the output signal Fosc of the phase-locked loop 10 according to the lock status signal LCK, and directly outputs Fosc after re-locking.
In an optional embodiment, the state detection module 20 is configured to compare the input signal with the feedback signal, and determine whether a difference between the input signal and the feedback signal is smaller than a threshold, and if the difference between the input signal and the feedback signal is smaller than the threshold within a preset time period, that is, if the difference meets a requirement within a certain time, it indicates locking, and at this time, it determines that the current state of the phase-locked loop is a locked state; and if the difference between the two is not less than the threshold value within the preset time period, determining that the current state of the phase-locked loop is the lock losing state.
In an alternative embodiment, with reference to fig. 6, the state detection module of this embodiment is implemented by using a cross-delay latch structure, and specifically, the state detection module includes: regarding the first delay unit 21 and the second delay unit 22, it should be noted that the delay time of the first delay unit 21 and the second delay unit 22 should be longer than the setup time of the D flip-flop and shorter than the period of the output signal, and in practical applications, the delay times of the two delay units can be designed within a reasonable range. In this embodiment, the input terminal of the first delay unit 21 is connected to the input terminal of the phase-locked loop for inputting the input signal Fin of the phase-locked loop, the output terminal of the first delay unit 21 is connected to the clock terminal of the first D flip-flop 23, the data input terminal of the first D flip-flop 23 is connected to the feedback terminal of the phase-locked loop for inputting the feedback signal Fback of the phase-locked loop, and the data output terminal of the first D flip-flop 23 is connected to the first input terminal of the and gate 25; the input end of the second delay 22 is connected to the feedback end of the phase-locked loop for inputting the feedback signal Fback of the phase-locked loop, the output end of the second delay 22 is connected to the clock end of the second D flip-flop 24, the data input end of the second D flip-flop 24 is connected to the input end of the phase-locked loop for inputting the input signal Fin of the phase-locked loop, the data output end of the second D flip-flop 24 is connected to the second input end of the and gate 25, and the output end of the and gate 25 is used for outputting the status signal LCK.
It should be noted that the connection relationship in the present application includes, but is not limited to, a connection relationship generated by connecting two input terminals based on the input signals for receiving the same input signals, a connection relationship generated by connecting output terminals and input terminals, and the like.
The phase-locked loop state detection operation is described below with reference to fig. 5-6: the phase-locked loop aligns the rising edges of the input signal Fin and the feedback signal Fback (phase difference is constant) during locking, the rising edge of either delay can capture the high level of the other, and the output signals of the two D flip- flops 23 and 24 are always 1. When the division factor of the loop divider is changed, the output signal Fback of the phase locked loop changes, and its new rising edge will differ from the input signal Fin by one or more cycles of the output signal Fosc. If the phase-locked loop increases the output frequency, i.e. the frequency division factor increases (e.g. from N to N + K), Fback will be delayed by K cycles from Fin, at which time the first D flip-flop 23 will output 0, so that the LCK signal output by the and gate 25 is 0, i.e. an out-of-lock signal is issued. Then, the output signal Fosc is gradually increased under the loop action until the overshoot occurs, at which time, the edge of the feedback signal Fback will lead the edge of the input signal Fin, and the second D flip-flop 24 will output 0 again, so that the and gate 25 continues to output the LCK signal of 0. Only when the edges of the feedback signal Fback and the input signal Fin are realigned within a certain range, the two D flip- flops 23 and 24 output 1 again, so that the LCK signal output by the and gate is 1, i.e., a lock signal is sent out.
In an alternative embodiment, referring to fig. 7, the status detection module of this embodiment comprises: module 222 and phase inverter 223 are engulfed to exclusive-or gate 221, pulse, the first input of exclusive-or gate 221 is used for the input signal Fin of phase-locked loop, the second input of exclusive-or gate 221 is used for the input the feedback signal Fback of phase-locked loop, the output of exclusive-or gate 221 with the input that module 222 was engulfed to the pulse is connected, the output that module 222 was engulfed to the pulse with the input of phase inverter 223 is connected, the output of phase inverter 223 with the control end of safety module 30 that falls is connected for output status signal LCK extremely safety module 30 that falls.
In an alternative embodiment, referring to fig. 8, the status detection module of this embodiment comprises: the phase-locked loop comprises an exclusive-or gate 231, a resistor R1, a capacitor C1 and a phase inverter 232, wherein a first input end of the exclusive-or gate 231 is used for inputting an input signal Fin of the phase-locked loop, a second input end of the exclusive-or gate 231 is used for inputting a feedback signal Fback of the phase-locked loop, an output end of the exclusive-or gate 231 is connected with one end of the resistor R1, the other end of the resistor R1 is connected with one end of the capacitor C1 and an input end of the phase inverter 232 respectively, the other end of the capacitor C1 is grounded, and an output end of the phase inverter 232 is connected with a control end of the safety frequency-down module 30 and used for outputting a state signal LCK to the safety frequency-.
In an alternative embodiment, referring to fig. 9, the status detection module of this embodiment comprises: the phase-locked loop comprises an exclusive-or gate 241, a delay unit 242, an and gate 243 and a phase inverter 244, wherein a first input end of the exclusive-or gate 241 is used for inputting an input signal Fin of the phase-locked loop, a second input end of the exclusive-or gate 241 is used for inputting a feedback signal Fback of the phase-locked loop, an output end of the exclusive-or gate 241 is respectively connected with an input end of the delay unit 242 and a first input end of the and gate 243, an output end of the delay unit 242 is connected with a second input end of the and gate 243, an output end of the and gate 243 is connected with an input end of the phase inverter 244, and an output end of the phase inverter 244 is connected with a control end of the safety frequency-down module 30 and is used for outputting a state signal.
In an alternative embodiment, referring to fig. 10, the status detection module of this embodiment comprises: the phase-locked loop control circuit comprises an exclusive-or gate 251, a PMOS transistor M1, an NMOS transistor M2, a capacitor C2 and a delay unit 252, wherein a first input end of the exclusive-or gate 251 is used for inputting an input signal Fin of the phase-locked loop, a second input end of the exclusive-or gate 251 is used for inputting a feedback signal Fback of the phase-locked loop, an output end of the exclusive-or gate 251 is respectively connected with gates of the PMOS transistor M1 and the NMOS transistor M2, a source of the PMOS transistor M1 is respectively connected with a power supply end and one end of the capacitor C2, a constant current source is connected between a source of the NMOS transistor M2 and the ground, after being connected with drains of the PMOS transistor M1 and the NMOS transistor M2, the constant current source is respectively connected with the other end of the capacitor C2 and an input end of the delay unit 252, and an output end of the delay unit 252 is used as an output end of a state detection module and is connected with a control end. The delay unit 252 may be implemented by a buffer. In this embodiment, optionally, the delay unit 252 may be omitted, that is, the drain of the PMOS transistor M1, the drain of the NMOS transistor M2, and the other end of the capacitor C2 are connected to serve as the output end of the state detection module, and are used to output the state signal LCK to the safety frequency reduction module.
In an alternative embodiment, referring to fig. 11, the safety down-conversion module of this embodiment includes a down-conversion device 31 and a switch 32, the down-conversion coefficient of the down-conversion device 31 is greater than 1.1, wherein an input terminal of the down-conversion device 31 and a first input terminal of the switch 32 are both connected to an output terminal of the phase-locked loop for inputting an output signal Fosc of the phase-locked loop, an output terminal of the down-conversion device 31 is connected to a second input terminal of the switch 32, a control terminal of the switch 32 is connected to an output terminal of the and gate 25, and an output terminal of the switch 32 is used for outputting a clock signal Fout. In this embodiment, theoretically, the frequency demultiplier can implement frequency demultiplier, generally the frequency demultiplier coefficient is determined by the damping factor, and the conventional overshoot is generally between 10% and 20% according to the actual circuit, so that generally, only setting the frequency demultiplier coefficient to be more than 1.1 can reduce the overshoot risk, and preferably, the frequency demultiplier coefficient can be selected to be 1.5.
Furthermore, the circuit for preventing the clock overshoot of the phase-locked loop of the present invention may further include a frequency-reduction control module, where the frequency-reduction control module is configured to obtain a frequency-division control signal of a loop frequency divider of the phase-locked loop, and determine a frequency-reduction coefficient of the frequency-reduction device according to the frequency-division control signal.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.

Claims (10)

1. A method of preventing clock overshoot in a phase locked loop comprising a phase detector, a low pass filter, a voltage controlled oscillator and a loop divider, characterized by the following steps when changing the frequency of the output signal of the phase locked loop by changing the division factor of the loop divider:
acquiring an input signal and a feedback signal of a phase-locked loop, and determining the current state of the phase-locked loop according to the input signal and the feedback signal, wherein the state of the phase-locked loop comprises a locked state and an unlocked state;
when the current state is the unlocking state, performing frequency reduction processing on an output signal of the phase-locked loop, and taking the signal subjected to frequency reduction processing as a clock signal;
when the current state is the locking state, the output signal of the phase-locked loop is directly used as a clock signal.
2. The method of claim 1, wherein determining the current state of the phase locked loop based on the input signal and the feedback signal comprises:
comparing the input signal with the feedback signal and judging whether the difference between the input signal and the feedback signal is smaller than a threshold value;
if the difference between the two is smaller than the threshold value within the preset time period, determining that the current state of the phase-locked loop is a locked state;
and if the difference between the two is not less than the threshold value within the preset time period, determining that the current state of the phase-locked loop is the lock losing state.
3. The method of claim 1, wherein down-converting the output signal of the phase-locked loop comprises:
and performing frequency reduction processing on the output signal of the phase-locked loop through a frequency reduction device.
4. A method for preventing phase-locked loop clock overshoot as defined in claim 3, further comprising:
acquiring a frequency division control signal of a loop frequency divider of the phase-locked loop, and determining a frequency reduction coefficient of the frequency reduction device according to the frequency division control signal, wherein the frequency reduction coefficient is greater than 1.1.
5. A circuit for preventing overshoot in a clock of a phase locked loop, the phase locked loop including a phase detector, a low pass filter, a voltage controlled oscillator, and a loop divider, the circuit comprising:
the state detection module is used for acquiring an input signal and a feedback signal of the phase-locked loop and determining the current state of the phase-locked loop according to the input signal and the feedback signal, wherein the state of the phase-locked loop comprises a locked state and an unlocked state;
the safety frequency reduction module is used for performing frequency reduction processing on an output signal of the phase-locked loop when the current state is an unlocked state, and taking the signal subjected to the frequency reduction processing as a clock signal; when the current state is the locking state, the output signal of the phase-locked loop is directly used as a clock signal.
6. The circuit for preventing phase-locked loop clock overshoot as defined in claim 5,
the state detection module is used for comparing the input signal with the feedback signal and judging whether the difference between the input signal and the feedback signal is smaller than a threshold value, and if the difference between the input signal and the feedback signal is smaller than the threshold value within a preset time period, determining that the current state of the phase-locked loop is a locked state; and if the difference between the two is not less than the threshold value within the preset time period, determining that the current state of the phase-locked loop is the lock losing state.
7. The circuit of claim 6, wherein the state detection module comprises: the phase-locked loop comprises a first delayer, a second delayer, a first D trigger, a second D trigger and an AND gate, wherein the input end of the first delayer is connected with the input end of a phase-locked loop so as to be used for inputting an input signal of the phase-locked loop, the output end of the first delayer is connected with the clock end of the first D trigger, the data input end of the first D trigger is connected with the feedback end of the phase-locked loop so as to be used for inputting a feedback signal of the phase-locked loop, and the data output end of the first D trigger is connected with the first input end of the AND gate; the input end of the second time delay is connected with the feedback end of the phase-locked loop so as to input a feedback signal of the phase-locked loop, the output end of the second time delay is connected with the clock end of the second D trigger, the data input end of the second D trigger is connected with the input end of the phase-locked loop so as to input an input signal of the phase-locked loop, the data output end of the second D trigger is connected with the second input end of the AND gate, and the output end of the AND gate is used for outputting a state signal.
8. The circuit for preventing clock overshoot of a phase-locked loop according to claim 7, wherein the safety frequency-reducing module comprises a frequency-reducing device and a switch, wherein an input terminal of the frequency-reducing device and a first input terminal of the switch are both connected to an output terminal of the phase-locked loop for inputting the output signal of the phase-locked loop, an output terminal of the frequency-reducing device is connected to a second input terminal of the switch, a control terminal of the switch is connected to the output terminal of the and gate, and an output terminal of the switch is used for outputting the clock signal.
9. The circuit for preventing phase-locked loop clock overshoot as defined in claim 8, comprising:
the frequency reduction control module is used for acquiring a frequency division control signal of a loop frequency divider of the phase-locked loop and determining a frequency reduction coefficient of the frequency reduction device according to the frequency division control signal, wherein the frequency reduction coefficient of the frequency reduction device is greater than 1.1.
10. A clock generation arrangement comprising a phase locked loop comprising a phase detector, a low pass filter, a voltage controlled oscillator and a loop divider, characterized in that the clock generation arrangement further comprises a circuit for preventing overshoot of the clock of the phase locked loop as claimed in any of the claims 4-7.
CN201811644487.1A 2018-12-30 2018-12-30 Method, circuit and clock generating device for preventing clock overshoot of phase-locked loop Pending CN111384946A (en)

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