CN111383704A - Memory built-in self-test circuit and memory test method - Google Patents
Memory built-in self-test circuit and memory test method Download PDFInfo
- Publication number
- CN111383704A CN111383704A CN201811645058.6A CN201811645058A CN111383704A CN 111383704 A CN111383704 A CN 111383704A CN 201811645058 A CN201811645058 A CN 201811645058A CN 111383704 A CN111383704 A CN 111383704A
- Authority
- CN
- China
- Prior art keywords
- test
- memory
- algorithm
- instruction
- test element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
Landscapes
- Tests Of Electronic Circuits (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
The embodiment of the application discloses a built-in self-test circuit of a memory and a test method for the memory, which are used for reducing the development cost of modifying a test algorithm supported by an MBIST circuit. The memory built-in self-test MBIST circuit can comprise: the algorithm generation module is used for sequentially constructing each test element according to the target test instruction and the construction rules of each test element of the background data, the pre-stored test element module and the target test algorithm; and the algorithm execution module is used for sequentially executing all the test elements on the memory to be tested.
Description
Technical Field
The present application relates to the field of memory technologies, and in particular, to a built-in self-test circuit for a memory and a method for testing the memory.
Background
The most common test method of the Memory at present is a Memory built-in Self-test (MBIST) method, an MBIST circuit automatically generates a test circuit of the Memory by targeting the Memory, and detects some defects existing in the Memory by executing a specific test algorithm, and different test algorithms can obtain different Memory test coverage rates.
In the prior art, developers usually need to program algorithm modules in advance in an MBIST circuit, one algorithm module corresponds to one test algorithm, and when the MBIST circuit receives a test instruction, the MBIST circuit can generate a corresponding test algorithm according to background data specified in the test instruction and a prestored algorithm module, so as to execute the test algorithm on a memory and detect defects in the memory.
However, when the test algorithm needs to be modified, a developer needs to modify the whole algorithm module written in advance, and the development cost of the test algorithm is high.
Disclosure of Invention
The embodiment of the application provides a built-in self-test circuit of a memory and a test method for the memory, which are used for reducing the development cost of modifying a test algorithm supported by an MBIST circuit.
To solve the foregoing technical problem, in a first aspect, an embodiment of the present application provides a memory built-in self-test circuit, including: the algorithm generation module is used for sequentially constructing each test element according to a target test instruction and according to background data, a pre-stored test element module and a construction rule of each test element of a target test algorithm; and the algorithm execution module is used for sequentially executing all the test elements to the memory. The memory built-in self-test MBIST circuit provided by the application constructs each test element of the test algorithm by pre-storing the test element module, then executes each test element of the test algorithm on the memory, completes the test, and when the test algorithm needs to be modified, developers only need to modify the pre-stored test element module, so that the development cost of modifying the algorithm is reduced.
Based on the first aspect, in a first possible implementation manner of the first aspect, the construction rule includes a construction parameter, where the construction parameter includes at least one of a combination of memory operations included in the corresponding test element, a correspondence between an operand of each memory operation and background data, a data length of the operand of each memory operation, and an address sequence of each memory operation, and by refining the construction rule, the operability of the embodiment of the present application is increased.
Based on the first possible implementation manner of the first aspect, in a second possible implementation manner of the first aspect, the construction rule further includes a module identifier of a test element module that matches the corresponding test element; the algorithm generation module is used for acquiring a target test element module from a plurality of pre-stored test element modules according to a module identifier in a construction rule of the test element when the test element is constructed; and then constructing the test element according to the background data, the target test element module and the construction parameters of the test element. By pre-storing a plurality of test element modules, the types of test algorithms which can be constructed by the MBIST circuit can be enriched.
Based on any one of the first aspect to the second possible implementation manner of the first aspect, in a third possible implementation manner of the first aspect, the target test algorithm includes N test elements, the target test instruction includes N sub-test instructions, i is a positive integer not greater than N, the ith sub-test instruction is used to instruct the MBIST circuit to execute the ith test element of the target test algorithm on the memory, and the algorithm generation module is specifically configured to construct the ith test element according to the ith sub-test instruction when the ith test element is constructed. The memory is tested according to the test instruction corresponding to each test element, so that the test waiting time is favorably shortened.
Based on the third possible implementation manner of the first aspect, in a fourth possible implementation manner of the first aspect, the memory built-in self-test circuit further includes a recovery module, where the recovery module is configured to send recovery information of an instruction identifier of an ith test instruction to the processing circuit after the algorithm execution module executes an ith test element on the memory, and the processing circuit is configured to manage an idle instruction identifier and generate a test instruction according to the idle instruction identifier. After the test element is executed, the recovery information of the instruction identifier of the test instruction corresponding to the test element is sent, so that the idle instruction identifier of the processor is increased, the test continuation is ensured, and the test running time is shortened.
In a second aspect, an embodiment of the present application provides a method for testing a memory, including: the memory built-in self-test MBIST circuit sequentially constructs each test element according to a target test instruction and according to background data, a pre-stored test element module and a construction rule of each test element of a target test algorithm; the MBIST circuit executes each of the test elements in sequence on the memory.
Based on the second aspect, in a first possible implementation manner of the second aspect, the construction rule includes a construction parameter, where the construction parameter includes at least one of a combination of memory operations included in the corresponding test element, a correspondence between an operand of each memory operation and background data, a data length of the operand of each memory operation, and an address sequence of each memory operation.
Based on the first possible implementation manner of the second aspect, in a second possible implementation manner of the second aspect, the construction rule further includes a module identifier of a test element module that matches with a corresponding test element; the MBIST circuit constructing the test elements includes: the MBIST circuit acquires a target test element module from a plurality of pre-stored test element modules according to the module identification in the construction rule of the test element; the MBIST circuit constructs the test elements according to the background data, the target test element module and the construction parameters of the test elements.
Based on any one of the second aspect to the second possible implementation manner of the second aspect, in a third possible implementation manner of the second aspect, the target test algorithm includes N test elements, the test instruction includes N sub-test instructions, i is a positive integer not greater than N, the ith sub-test instruction is used to instruct the MBIST circuit to execute the ith test element of the target test algorithm on the memory, and the MBIST circuit constructs the ith test element includes: the MBIST circuit constructs the ith test element according to the ith sub-test instruction.
Based on the third possible implementation manner of the second aspect, in a fourth possible implementation manner of the second aspect, the method further includes: after the ith test element is executed on the memory, the MBIST circuit sends the recovery information of the instruction identifier of the ith sub-test instruction to a processing circuit, and the processing circuit is used for managing the idle instruction identifier and generating the test instruction according to the idle instruction identifier.
Drawings
FIG. 1 is a schematic diagram of an MBIST test system;
FIG. 2 is a schematic diagram of an embodiment of an MBIST circuit of the present application;
FIG. 3 is a schematic diagram of an embodiment of the MBIST test system of the present application;
FIG. 4 is a diagram illustrating a process of testing a memory by the MBIST test system of the present application;
FIG. 5 is another schematic diagram of the test process of the MBIST test system for the memory of the present application;
FIG. 6 is another schematic diagram of the test process of the MBIST test system for the memory of the present application;
FIG. 7 is a schematic diagram of an embodiment of a method for testing a memory according to the present application;
FIG. 8 is a schematic diagram of a possible refinement of step 701 in the corresponding embodiment of FIG. 7;
FIG. 9 is a schematic diagram of an embodiment of a method for executing an ith test element on a memory according to the present application.
Detailed Description
The embodiment of the application provides a built-in self-test circuit of a memory and a test method of the memory.
Embodiments of the present application are described below with reference to the accompanying drawings.
The term "and/or" appearing in the present application may be an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone, wherein A and B can be singular or plural. In addition, the character "/" in this application generally indicates that the former and latter related objects are in an "or" relationship. In the present application, "at least one" means one or more, "a plurality" means two or more. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or multiple.
The terms "first," "second," and the like in the description and in the claims of the present application and in the above-described drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and are merely descriptive of the various embodiments of the application and how objects of the same nature can be distinguished. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Modern integrated circuits increasingly require memory to be embedded on the semiconductor chip itself, and conventional testing methods for memory are limited by the difficulty and cost of testing and are not accepted by chip designers. The most common test method of the Memory at present is realized by a Memory built-in Self-test (MBIST) method, a test circuit of the Memory is automatically generated, and the Memory address is read and written according to a corresponding test algorithm to complete the test of the Memory. Although the test method adds some control logics in the circuit, thereby increasing the area of the chip, for a large-scale test circuit, the method can realize test automation, reduce test time, improve test coverage rate and greatly save test cost.
The MBIST method is a test method that targets the memory to detect certain defects in the memory by executing a specific test algorithm, and different test algorithms can obtain different memory test coverage rates. Referring to fig. 1, a schematic diagram of an MBIST test system is shown, where the MBIST test system includes a processing circuit 1, an MBIST circuit 2, a memory controller 3, and a memory 4, where the processing circuit 1, such as a processor or a module in the processor, may input a test instruction to the MBIST circuit 2, where the test instruction is used to specify a test algorithm, and optionally, may also specify background data, and the MBIST circuit 2 is used to generate a corresponding test algorithm according to the received test instruction and execute the test algorithm to detect a defect existing in the memory 4 through the memory controller 3. In practical applications, the background data may also be preconfigured in MBIST circuit 2.
The testing algorithm employed by MBIST is a finite sequence of test elements that include a series of specified memory operations, operands for each memory operation, and address sequences for the memory operations. The following are the algorithm primitives of the March C-algorithm:
the March C-algorithm contains 6 test elements, respectively
And
with the 2 nd test element
For example, the memory operations include a read operation and a write operation in sequence, where the background data is a, the operand of the read operation is background data, the operand of the write operation is the inverse of the background data, and the address sequence of the memory operation is ascending, that is, the memory operations specified in the test element are performed on the memory cells in the memory 4 in sequence according to the ascending order. The execution of the 2 nd test element by the MBIST circuit 2 on the memory 4 means that the following memory operations are sequentially performed on each memory cell in the memory 4 in ascending order: firstly, reading the data in the current storage unit, comparing the data with A, writing A into the current storage unit if the data are the same as A, and reporting an error if the data are not the same as A.
In order to flexibly adjust the test strategy for the memory 4, it is necessary to enrich the available test algorithms of the MBIST circuit, from which one or more test algorithms are selected to test the memory 4. Therefore, in the prior art, developers usually need to program algorithm modules in advance in the MBIST circuit 2, one algorithm module corresponds to one test algorithm, and when the MBIST circuit 2 receives a test instruction sent by the processing circuit 1, the corresponding test algorithm can be generated according to background data specified in the test instruction and a prestored algorithm module. If the test algorithm needs to be modified, a developer needs to modify the whole algorithm module which is written in advance, and if the test algorithm needs to be newly added, the developer needs to rewrite the whole algorithm module corresponding to the newly added test algorithm, so that the development cost of the test algorithm is high.
In order to solve the above problem, the present application provides an MBIST circuit 2, please refer to fig. 2, where the MBIST circuit 2 includes: the system comprises an algorithm generation module 21 and an algorithm execution module 22, wherein the algorithm generation module 21 is used for constructing each test element of the target test algorithm according to the test instruction and the construction rules of each test element of the background data, the pre-stored test element module and the target test algorithm after receiving the test instruction; the algorithm execution module 22 is used for executing each test element of the target test algorithm on the memory to be tested. The test instruction is used to specify a test algorithm, and optionally, the test instruction may also specify background data, or the background data may not be specified by the test instruction, but may be preconfigured in the MBIST circuit 2. In order to reduce the development cost as much as possible, the same test element module may be used to construct a plurality of test elements, and specifically, the plurality of test elements that the same test element module may construct may belong to the same test algorithm or may belong to different test algorithms, which is not specifically limited herein.
In one possible implementation manner of the present application, with reference to fig. 2, the MBIST circuit 2 may further include a storage module 23, and the storage module 23 may be configured to store the test element module and the construction rule of each test element of the plurality of test algorithms. Developers can write a test element module according to the same points among different algorithm elements by comparing a plurality of algorithm elements of a test algorithm, and write the construction rule of each test element according to the different points among different algorithm elements. Illustratively, by comparing different test elements of the March-type algorithm (including different test elements of the same algorithm and test elements of different algorithms), the March C-algorithm and the March Y algorithm are taken as examples, wherein the algorithm primitives of the March C-algorithm are:
the algorithm primitives of March Y algorithm are:
it can be found that the operation objects of the memory operation in each test element of the March-type algorithm are all current memory units, and the difference between each test element is mainly reflected in: 1. the address sequence of the memory operation may be different: in ascending or descending order; 2. the combination of memory operations involved may vary: the included combination may be one operation, such as a write operation or a read operation, the included combination may be two operations, may be a combination of a read operation and a write operation, or may be a combination of a write operation and a read operation, and the included combination may be three or more operations, which is not specifically illustrated; 3. the correspondence between operands of memory operations and background data may be different: the operand of the memory operation may be the background data, or, alternatively, may be the inverse of the background data; 4. the data length of the operands of the memory operation may be different; and so on. In a possible implementation manner of the present application, the construction rule of the test element may include a construction parameter, where the construction parameter of the test element includes at least one of a combination of memory operations included in the corresponding test element, a correspondence between an operand of each memory operation in the corresponding test element and background data, a data length of the operand of each memory operation, and an address sequence of the memory operation. The developer can compile at least one test element module for the March-class algorithm, and compile the construction parameters of each test element by using the difference as a configurable parameter, and when a certain March-class algorithm needs to be generated, the algorithm generation module 21 can respectively construct each test element of the test algorithm according to the background data, the test element module of the test algorithm and the construction parameters of each test element of the test algorithm, thereby obtaining the test algorithm. Therefore, developers only need to write one test element module at least, and the algorithm generation module 21 can construct all March algorithms.
The testing algorithm adopted by the MBIST includes, besides the mainstream March-type algorithm, other types of algorithms such as Butterfly algorithm, surround algorithm, 3-step algorithm, and PRBS algorithm, and developers may need to write corresponding testing element modules for these non-March-type algorithms. Each test element of the non-March type algorithm can be generated by using the test element module corresponding to the algorithm, or part of the test elements in the non-March type algorithm can be generated by multiplexing the test element module corresponding to the March type algorithm, and other test elements can be generated by using the test element module corresponding to the algorithm. Taking the Butterfly algorithm as an example, the algorithm primitives are as follows:
the algorithm contains 4 test elements, the first test element
And a third test element
The operation objects of the middle memory operation are the current memory units, and the two test elements can pass through the complexThe test element module is constructed by a March type algorithm. And a second test element in the algorithm
And a fourth test element
The operand of the partial memory operation in (1) is not the current memory location, e.g.,
the two test elements cannot be constructed by the test element module of the multiplexing March-type algorithm, so that a second test element of the Butterfly algorithm and a test element module corresponding to a fourth test element need to be added. Only read-write operands are different between M1 and M3, and the read-write operand of M3 is the inverse of the read-write operand of M1, so as to reduce the development cost of the test element module, at least one test element module is required to be constructed and shared by the second test element and the fourth test element. By a similar approach, we can extend the test element module of other algorithms (such as surrouding algorithm, 3-step algorithm, PRBS algorithm, etc.). In order to reduce the development cost of the test element module, the test elements of the non-March algorithm can reuse the written test element module as much as possible, for example, the test element module of the March algorithm, and can write a corresponding test element module for the test elements which can not reuse the existing test element module.
It can be seen that, in order to enable the MBIST circuit 2 provided by the present application to test a memory by using multiple test algorithms, in a possible implementation manner of the present application, the MBIST test system may store a plurality of test element modules in advance, for example, test element modules corresponding to a March-type algorithm, a Butterfly algorithm, a Surrouding algorithm, a 3-step algorithm, and a PRBS algorithm, where identifications of different test element modules are different. The construction rule of the test element also includes a module identification of the test element module corresponding to the test element, and at this time, the algorithm generating module 21 is specifically configured to, when constructing the test element according to the background data, the pre-stored test element module, and the construction rule of the ith test element in the target test algorithm (where i is a positive integer and is not greater than the number of test elements included in the target test algorithm), obtain the target test element module from the pre-stored multiple test element modules according to the module identifier in the construction rule of the ith test element, where the target test element module is a test element module corresponding to the ith test element in the target test algorithm, and then, and constructing the ith test element of the target test algorithm according to the background data, the obtained target test element module and the construction parameters of the ith test element.
One possible implementation of the MBIST test system to perform a target test algorithm on a memory under test is described below. Referring to fig. 3, the MBIST test system includes a processing circuit 1, an MBIST circuit 2, a memory controller 3, and a memory 4, the MBIST circuit 2 including: the algorithm generating module 21, the algorithm executing module 22, and the storage module 23, and functions of each module in the MBIST circuit 2 may be described in the embodiment corresponding to fig. 2, which is not described herein again. Processing circuit 1 may input to MBIST circuit 2 a test instruction indicating the background data and target test algorithm selected for testing memory 4, and for ease of description, the test instruction corresponding to the complete target test algorithm will be referred to as the target test instruction. The algorithm generating module 21 may construct each test element of the target test algorithm according to the received target test instruction, and the algorithm executing module 22 may execute each test element to execute the target test algorithm on the memory 4, thereby detecting a defect existing in the memory 4 through the memory controller 3.
The process of testing the memory 4 by the MBIST test system with the test algorithm 1 and the test algorithm 2 in sequence can be implemented in various specific ways. For example, in example 1, the processing circuit 1 may first generate the test instruction 1, where the test instruction 1 may be used to instruct the MBIST circuit 2 to execute all test elements of the test algorithm 1, at this time, the algorithm generating module 21 may construct all test elements corresponding to the test algorithm 1 according to the test instruction 1, and the algorithm executing module 22 may sequentially execute each test element after the algorithm generating module 21 generates all test elements of the test algorithm 1. After the algorithm execution module 22 completes execution of each test element, the processing circuit 1 may generate a test instruction 2, and continue to input the test instruction 2 to the MBIST circuit 2, where the test instruction 2 is used to instruct the MBIST circuit 2 to execute all test elements of the test algorithm 2, and the algorithm execution module 22 may execute each test element in sequence after the algorithm generation module 21 generates all test elements of the test algorithm 2. Assuming that the test algorithm 1 includes 5 test elements and the test algorithm 2 includes 4 test elements, the process of testing the memory 4 by the MBIST test system according to the test algorithm 1 and the test algorithm 2 may be embodied in a time axis manner, as shown in fig. 4. The test runtime of an MBIST test system generally includes two parts: the processing circuit 1 configures the time length Ta of the target test instruction and the time length Tb for the MBIST circuit 2 to execute the test according to the target test instruction. Wherein, Ta is mainly limited by the operating frequency of the configuration processing circuit 1, and the like, and the occupied proportion is also larger in the test operation time length; tb is mainly limited by factors such as access timing parameters and access traffic of the memory 4 itself, and is generally relatively fixed. Ta1 and Ta2 in fig. 4 represent the time periods for the processing circuit 1 to configure the test instruction 1 and the test instruction 2, respectively, and Tb1 and Tb2 represent the time periods for the MBIST circuit 2 to perform the test according to the test instruction 1 and the test instruction 2, respectively. It can be seen that the test run length of the MBIST test system corresponding to example 1 is: ta1+ Tb1+ Ta2+ Tb 2.
In example 2, on the basis of example 1, the algorithm execution module 22 may also execute a part of test elements (for example, a first test element) of the test algorithm 1 after the algorithm generation module 21 generates the test element, which is beneficial to reduce a time length Tb for the MBIST circuit 2 to execute the test according to the target test instruction, and further reduce a test operation time length of the MBIST test system, compared with example 1.
If the target test algorithm includes N test elements, where N is a positive integer, in a possible implementation manner of the present application, the target test instruction may include N sub-test instructions, where the ith sub-test instruction is used to instruct the MBIST circuit 2 to execute the ith test element of the target test algorithm, and i is a positive integer not greater than N, that is, the process of generating the target test instruction by the processing circuit 1 may specifically refer to a process of sequentially configuring the N sub-test instructions, the processing circuit 1 may sequentially input the configured sub-test instructions into the MBIST circuit 2, and then the MBIST circuit 2 may sequentially execute the N sub-test instructions, and the process of executing the ith sub-test instruction by the MBIST circuit 2 may include: the algorithm generating module 21 constructs the ith test element, and after the algorithm generating module 21 constructs the ith test element, the algorithm executing module 22 may execute the ith test element. Therefore, the process of testing the memory 4 by the MBIST test system with the test algorithm 1 and the test algorithm 2 in sequence can also be as in example 3: the processing circuit 1 may first configure 5 sub-test instructions corresponding to the test algorithm 1, sequentially generate the test instruction 1_1, the test instruction 1_2, the test instruction 1_3, the test instruction 1_4, and the test instruction 1_5, and sequentially input each generated test instruction into the MBIST circuit 2. Where test instruction 1_1 may be used to instruct MBIST circuit 2 to execute the first test element of test algorithm 1, test instruction 1_2 may be used to instruct MBIST circuit 2 to execute the second test element of test algorithm 1, and so on, test instruction 1_5 may be used to instruct MBIST circuit 2 to execute the fifth test element of test algorithm 1. After the processing circuit 1 generates the test instruction 1_1, the test instruction 1_1 may be input to the algorithm generating module 21, the algorithm generating module 21 may construct a first test element of the test algorithm 1 according to the test instruction 1_1, and the algorithm executing module 22 may execute the first test element of the test algorithm 1 after the algorithm generating module 21 generates the test element. Thereafter, MBIST circuit 2 may execute test instruction 1_2, test instruction 1_3, test instruction 1_4, and test instruction 1_5 in sequence. After the algorithm execution module 22 executes each instruction corresponding to the test algorithm 1, the processing circuit 1 may generate four sub-test instructions corresponding to the test algorithm 2, sequentially generate a test instruction 2_1, a test instruction 2_2, a test instruction 2_3, and a test instruction 2_4, and sequentially input each generated test instruction into the MBIST circuit 2, where the test instruction 2_1 may be used to instruct the MBIST circuit 2 to execute a first test element of the test algorithm 2, the test instruction 2_2 may be used to instruct the MBIST circuit 2 to execute a second test element of the test algorithm 2, and so on, the test instruction 2_4 may be used to instruct the MBIST circuit 2 to execute a fourth test element of the test algorithm 2. The process of MBIST circuit 2 executing the individual sub-test instructions of test algorithm 2 may be referred to above as the process of executing the individual sub-test instructions of test algorithm 1. Therefore, the process of testing the memory 4 according to the test algorithm 1 and the test algorithm 2 by the MBIST test system in example 3 can be embodied in a time axis manner, as shown in fig. 5. Ta1_ m and Ta2_ n in fig. 5 represent the time length for which the processing circuit 1 configures the test instruction 1_ m and the test instruction 2_ n, respectively, and Tb1_ m and Tb2_ n represent the time length for which the MBIST circuit 2 performs the test in accordance with the test instruction 1_ m and the test instruction 2_ n, respectively, where m is 1, 2, 3, 4, 5, and n is 1, 2, 3, 4. It can be seen that the test run length of the MBIST test system corresponding to example 3 is: ta1_1+ (Tb1_1+ Tb1_2+ Tb1_3+ Tb1_4+ Tb1_5) + Ta2_1+ (Tb2_1+ Tb2_2+ Tb2_3+ Tb2_4), wherein Tb1_1+ Tb1_2+ Tb1_3+ Tb1_4+ Tb1_5 is equivalent to Tb1 in example 1, and Tb2_1+ Tb2_2+ Tb2_3+ Tb2_4 is equivalent to Tb2 in example 1. As can be easily seen from the test run lengths of the MBIST test systems corresponding to comparative examples 3 and 1, the test run length of the MBIST test system of example 3 is much shorter than that of example 1. As can be seen, by splitting the test instruction corresponding to the target test algorithm into a plurality of sub-test instructions according to each test element of the target test algorithm, the MBIST circuit 2 tests the memory 4 according to the target test algorithm by sequentially executing each sub-test instruction, which is beneficial to shortening the test operation time of the MBIST test system.
In actual operation of the MBIST test system, the MBIST test system generally includes an instruction cache 5, such as a First Input First Output (FIFO) memory, and the processing circuit 1 may Input the generated test instruction into the instruction cache 5, and then the MBIST circuit 2 reads the test instruction from the instruction cache 5. Subject to the memory space limitations of the instruction cache 5 and in order to ensure that the MBIST test system executes test instructions correctly in order, referring to fig. 3, the processing circuit 1 may also be configured to manage idle instruction identifications and to generate test instructions using the idle instruction identifications.
In example 1, since the test instruction configured by the processing circuit 1 is a target test instruction corresponding to a complete test algorithm, the content of the target test instruction is more, at this time, the processing circuit 1 usually sets only one instruction identifier, so that only after the MBIST circuit 2 completes executing the test instruction 1, the processing circuit 1 can obtain an idle instruction identifier again, and then, the processing circuit 1 can start configuring the test instruction 2. In example 3, the test instruction configured by the processing circuit 1 corresponds to one sub-test instruction, and each sub-test instruction corresponds to one test element, so that the content of the sub-test instruction is less, the processing circuit 1 may be provided with a plurality of instruction identifiers, for example, 5 instruction identifiers, the processing circuit 1 may sequentially generate 5 sub-test instructions (i.e., the test instruction 1_1, the test instruction 1_2, the test instruction 1_3, the test instruction 1_4, and the test instruction 1_5) corresponding to the test algorithm 1, each sub-test instruction corresponds to one instruction identifier, and the processing circuit 1 may input each generated sub-test instruction into the instruction cache 5. After the processing circuit 1 generates 5 sub-test instructions corresponding to the test algorithm 1, no idle instruction identifier exists in the processing circuit 1, and at this time, the processing circuit 1 cannot continue to configure the sub-test instruction corresponding to the test algorithm 2. After the MBIST circuit 2 executes the 5 sub-test instructions corresponding to the test algorithm 1, the processing circuit 1 may obtain the idle 5 instruction identifiers again, and at this time, the processing circuit 1 may start to configure the 4 sub-test instructions corresponding to the test algorithm 2.
In order to further shorten the test operation length of the MBIST test system, referring to fig. 3, the MBIST circuit 2 may further include a recovery module 24, when the algorithm execution module 22 executes the ith sub-test instruction of the target test algorithm, the recovery module 24 may send recovery information of an instruction identifier of the ith sub-test instruction to the processing circuit 1, the processing circuit 1 may use the instruction identifier of the ith sub-test instruction as an idle instruction identifier, and generate the test instruction according to the idle instruction identifier, where the generated test instruction is a test instruction corresponding to a certain test element, that is, the above-mentioned sub-test instruction, for example, the test instruction to be generated may be a certain sub-test instruction of the target test algorithm, or may be a certain sub-test instruction of another test algorithm to be executed other than the target test algorithm. Thus, based on example 3, it is assumed that the processing circuit 1 may be provided with 5 instruction identifiers, and after the MBIST circuit 2 executes the test instruction 1_1, the processing circuit 1 may send the recovery information of the instruction identifier corresponding to the test instruction 1_1 to the processing circuit 1, so that the processing circuit 1 obtains an idle instruction identifier again, at this time, the processing circuit 1 may configure the test instruction to be generated by using the idle instruction identifier, in this example, configure the sub-test instruction 2_1 corresponding to the first test element of the test algorithm 2, which is favorable for the continuation of the test. At this time, the process of testing the memory 4 by the MBIST test system according to the test algorithm 1 and the test algorithm 2 in example 3 may be embodied in a time axis manner, as shown in fig. 6, the configuration process of the sub-test instruction 2_1 is performed in parallel with the execution process of the test algorithm 1, so that the test runtime length of the MBIST test system corresponding to example 3 may reduce the configuration time length Ta2_1 of the sub-test instruction 2_1, specifically: ta1_1+ (Tb1_1+ Tb1_2+ Tb1_3+ Tb1_4+ Tb1_5) + (Tb2_1+ Tb2_2+ Tb2_3+ Tb2_ 4).
The above device embodiment of the present application is described, and in accordance with the above MBIST circuit, an embodiment of the present application further provides a method for testing a memory, and with reference to fig. 7, an embodiment of the method for testing a memory of the present application includes the following steps:
701. sequentially constructing each test element according to the target test instruction and the construction rules of each test element of the background data, the pre-stored test element module and the target test algorithm;
the memory built-in self-test MBIST circuit can sequentially construct each test element according to a target test instruction and according to background data, a pre-stored test element module and a construction rule of each test element of a target test algorithm. The target test instruction is used for instructing the MBIST circuit to execute a target test algorithm on the memory to be tested, and corresponds to the whole target test algorithm.
702. The individual test elements are executed in sequence on the memory.
The MBIST circuit executes each test element to the memory to be tested in sequence
In a possible implementation manner of the present application, the construction rule includes a construction parameter, and the construction parameter includes at least one of a combination of memory operations included in the corresponding test element, a correspondence between an operand of each memory operation and background data, a data length of the operand of each memory operation, and an address sequence of each memory operation.
Step 701 may be performed by the algorithm generating module 21 in the above-described apparatus embodiment, and step 702 may be performed by the algorithm executing module 22 in the above-described apparatus embodiment.
In one possible implementation manner of the present application, the construction rule further includes a module identifier of the test element module that matches the corresponding test element. Referring to fig. 8, the process of constructing a single test element by the MBIST circuit in step 701 may specifically include:
7011. acquiring a target test element module from a plurality of pre-stored test element modules according to a module identifier in a construction rule of the test element;
7012. and constructing the test elements according to the background data, the target test element module and the construction parameters of the test elements.
In a possible implementation manner of the present application, if the target test algorithm includes N test elements, the target test instruction may include N sub-test instructions, i is a positive integer not greater than N, the ith sub-test instruction is used to instruct the MBIST circuit to execute the ith test element of the target test algorithm on the memory to be tested, and in step S100, the process of constructing the ith test element by the MBIST circuit may include:
and constructing the ith test element according to the ith sub-test instruction. The specific process of constructing the ith test element can refer to the corresponding refinement steps of fig. 8.
In a possible implementation manner of the present application, after the ith test element is executed on the memory to be tested, the MBIST circuit may send the recovery information of the instruction identifier of the ith sub-test instruction to the processing circuit, where the processing circuit is configured to manage an idle instruction identifier and generate a test instruction according to the idle instruction identifier. Referring to fig. 9, in the process of the MBIST circuit executing the target test algorithm on the memory to be tested, the step of the MBIST circuit executing the ith test element of the target test algorithm on the memory to be tested may include:
901. according to the ith sub-test instruction, acquiring a target test element module from a plurality of pre-stored test element modules according to the module identification in the construction rule of the test element;
the ith test element module corresponds to the ith test element.
902. Constructing an ith test element according to the background data, the target test element module and the construction parameters of the ith test element;
903. executing the ith test element on the memory;
904. and sending the recycling information of the instruction identification of the ith sub-test instruction to the processing circuit.
It should be noted that the foregoing embodiments related to the MBIST circuit 2 are all applicable to the embodiment of the method of the present application, and the method embodiment and the corresponding apparatus embodiment can achieve the same technical effect, and are not described herein again.
In the embodiments of the present application, words such as "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.
In the embodiments of the present application, various illustrations are made for the sake of an understanding of aspects. However, these examples are merely examples and are not meant to be the best mode of carrying out the present application.
The above-described embodiments may be implemented in whole or in part by software, hardware, firmware, or any combination thereof, and when implemented using software, may be implemented in whole or in part in the form of a computer program product.
The technical solutions provided by the present application are introduced in detail, and the present application applies specific examples to explain the principles and embodiments of the present application, and the descriptions of the above examples are only used to help understand the method and the core ideas of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A memory built-in self-test circuit, comprising:
the algorithm generation module is used for sequentially constructing each test element according to a target test instruction and according to background data, a pre-stored test element module and a construction rule of each test element of a target test algorithm;
and the algorithm execution module is used for sequentially executing all the test elements to the memory.
2. The memory built-in self-test circuit of claim 1, wherein the construction rules comprise construction parameters comprising at least one of a combination of memory operations included in corresponding test elements, a correspondence of operands to background data for each memory operation, a data length of an operand for each memory operation, and an address sequence for each memory operation.
3. The memory built-in self-test circuit of claim 2, wherein the construction rule further comprises a module identification of a test element module that matches a corresponding test element;
the algorithm generation module is specifically configured to, when the algorithm generation module is used to construct the test element:
acquiring a target test element module from a plurality of pre-stored test element modules according to the module identification in the construction rule of the test element;
and constructing the test element according to the background data, the target test element module and the construction parameters of the test element.
4. The memory built-in self-test circuit of any one of claims 1 to 3, wherein the target test algorithm comprises N test elements, the target test instruction comprises N sub-test instructions, i is a positive integer not greater than N, the ith sub-test instruction is configured to instruct the MBIST circuit to execute the ith test element of the target test algorithm on the memory, and the algorithm generation module, when configured to construct the ith test element, is specifically configured to:
and constructing the ith test element according to the ith sub-test instruction.
5. The memory built-in self-test circuit of claim 4, further comprising a reclamation module to:
and after the algorithm execution module executes the ith test element on the memory, sending recovery information of the instruction identifier of the ith sub-test instruction to a processing circuit, wherein the processing circuit is used for managing the idle instruction identifier and generating the test instruction according to the idle instruction identifier.
6. A method for testing a memory, comprising:
the memory built-in self-test MBIST circuit sequentially constructs each test element according to a target test instruction and according to background data, a pre-stored test element module and a construction rule of each test element of a target test algorithm;
the MBIST circuit executes each of the test elements in sequence on the memory.
7. The method according to claim 6, wherein the construction rule comprises construction parameters, and the construction parameters comprise at least one of a combination of the memory operations included in the corresponding test element, a correspondence relationship between an operand of each memory operation and background data, a data length of the operand of each memory operation, and an address sequence of each memory operation.
8. The method of testing a memory of claim 7, wherein the construction rule further comprises a module identification of a test element module that matches the corresponding test element;
the MBIST circuit constructing the test elements includes:
the MBIST circuit acquires a target test element module from a plurality of pre-stored test element modules according to the module identification in the construction rule of the test element;
the MBIST circuit constructs the test elements according to the background data, the target test element module and the construction parameters of the test elements.
9. The method according to any one of claims 6 to 8, wherein the target test algorithm includes N test elements, the target test instruction includes N sub-test instructions, i is a positive integer not greater than N, the ith sub-test instruction is used to instruct the MBIST circuit to execute the ith test element of the target test algorithm on the memory, and the MBIST circuit constructs the ith test element includes:
the MBIST circuit constructs the ith test element according to the ith sub-test instruction.
10. The method of testing a memory of claim 9, further comprising:
after the ith test element is executed on the memory, the MBIST circuit sends the recovery information of the instruction identifier of the ith sub-test instruction to a processing circuit, and the processing circuit is used for managing the idle instruction identifier and generating the test instruction according to the idle instruction identifier.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811645058.6A CN111383704B (en) | 2018-12-29 | 2018-12-29 | Built-in self-test circuit of memory and test method for memory |
| PCT/CN2019/115239 WO2020134572A1 (en) | 2018-12-29 | 2019-11-04 | Memory built-in self-test circuit and test method for memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811645058.6A CN111383704B (en) | 2018-12-29 | 2018-12-29 | Built-in self-test circuit of memory and test method for memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111383704A true CN111383704A (en) | 2020-07-07 |
| CN111383704B CN111383704B (en) | 2022-07-26 |
Family
ID=71128590
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811645058.6A Active CN111383704B (en) | 2018-12-29 | 2018-12-29 | Built-in self-test circuit of memory and test method for memory |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN111383704B (en) |
| WO (1) | WO2020134572A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112071355A (en) * | 2020-11-12 | 2020-12-11 | 南京邮电大学 | Self-adaptive BIST (built-in self-test) test method for improving fault coverage rate |
| CN115691632A (en) * | 2022-10-19 | 2023-02-03 | 中科声龙科技发展（北京）有限公司 | Test control system and method |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090172486A1 (en) * | 2003-02-13 | 2009-07-02 | Ross Don E | Testing embedded memories in an integrated circuit |
| US20130019130A1 (en) * | 2011-07-15 | 2013-01-17 | Synopsys Inc. | Testing electronic memories based on fault and test algorithm periodicity |
| CN103310852A (en) * | 2013-05-13 | 2013-09-18 | 桂林电子科技大学 | MBIST (Memory Built In Self Test) controller structure system based on IEEE (Institute of Electrical and Electronics Engineers) 1500 standard and compatible with SRAM/ROM (Static Random Access Memory/Read Only Memory) |
| CN103617810A (en) * | 2013-11-26 | 2014-03-05 | 中国科学院嘉兴微电子与***工程中心 | Test structure and test method for embedded memory |
| US20140089874A1 (en) * | 2012-09-24 | 2014-03-27 | Cadence Design Systems, Inc. | Method and Apparatus for Optimizing Memory-Built-In-Self Test |
| CN104122497A (en) * | 2014-08-11 | 2014-10-29 | 中国科学院自动化研究所 | Circuit and method for generating test vectors required by built-in self-test of integrated circuit |
| US20150371718A1 (en) * | 2014-06-20 | 2015-12-24 | Arm Limited | Memory built-in self-test for a data processing apparatus |
| CN105203908A (en) * | 2015-10-12 | 2015-12-30 | 中国人民解放军国防科学技术大学 | BIST-based open-circuit test method for TSVs in 3D SRAM |
| CN106409343A (en) * | 2016-08-31 | 2017-02-15 | 上海华力微电子有限公司 | Built-in self-testing circuit of memory suitable for various periodic testing algorithms |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102157205B (en) * | 2011-05-10 | 2015-09-30 | 北京航空航天大学 | A kind of method of testing to FPGA inside fault of multiposition memorizer inlaid |
| CN103093829A (en) * | 2011-10-27 | 2013-05-08 | 迈实电子(上海)有限公司 | Memory test system and memory test method |
| CN105679377B (en) * | 2016-01-11 | 2018-07-03 | 福州瑞芯微电子股份有限公司 | The self-adapting testing method and device of CPU cache memories |
| US10007588B2 (en) * | 2016-01-25 | 2018-06-26 | Nxp Usa, Inc. | Full address coverage during memory array built-in self-test with minimum transitions |
-
2018
- 2018-12-29 CN CN201811645058.6A patent/CN111383704B/en active Active
-
2019
- 2019-11-04 WO PCT/CN2019/115239 patent/WO2020134572A1/en active Application Filing
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090172486A1 (en) * | 2003-02-13 | 2009-07-02 | Ross Don E | Testing embedded memories in an integrated circuit |
| US20130019130A1 (en) * | 2011-07-15 | 2013-01-17 | Synopsys Inc. | Testing electronic memories based on fault and test algorithm periodicity |
| US20140089874A1 (en) * | 2012-09-24 | 2014-03-27 | Cadence Design Systems, Inc. | Method and Apparatus for Optimizing Memory-Built-In-Self Test |
| CN103310852A (en) * | 2013-05-13 | 2013-09-18 | 桂林电子科技大学 | MBIST (Memory Built In Self Test) controller structure system based on IEEE (Institute of Electrical and Electronics Engineers) 1500 standard and compatible with SRAM/ROM (Static Random Access Memory/Read Only Memory) |
| CN103617810A (en) * | 2013-11-26 | 2014-03-05 | 中国科学院嘉兴微电子与***工程中心 | Test structure and test method for embedded memory |
| US20150371718A1 (en) * | 2014-06-20 | 2015-12-24 | Arm Limited | Memory built-in self-test for a data processing apparatus |
| CN104122497A (en) * | 2014-08-11 | 2014-10-29 | 中国科学院自动化研究所 | Circuit and method for generating test vectors required by built-in self-test of integrated circuit |
| CN105203908A (en) * | 2015-10-12 | 2015-12-30 | 中国人民解放军国防科学技术大学 | BIST-based open-circuit test method for TSVs in 3D SRAM |
| CN106409343A (en) * | 2016-08-31 | 2017-02-15 | 上海华力微电子有限公司 | Built-in self-testing circuit of memory suitable for various periodic testing algorithms |
Non-Patent Citations (1)
| Title |
|---|
| YASHA JYOTHI M. SHIRUR: "Implementation of Area Efficient Hybrid MBIST for Memory Clusters in Asynchronous SoC", 《2014 FIFTH INTERNATIONAL SYMPOSIUM ON ELECTRONIC SYSTEM DESIGN》, 30 July 2015 (2015-07-30), pages 226 - 227 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112071355A (en) * | 2020-11-12 | 2020-12-11 | 南京邮电大学 | Self-adaptive BIST (built-in self-test) test method for improving fault coverage rate |
| WO2022099947A1 (en) * | 2020-11-12 | 2022-05-19 | 南京邮电大学 | Adaptive bist method for improving fault coverage |
| CN115691632A (en) * | 2022-10-19 | 2023-02-03 | 中科声龙科技发展（北京）有限公司 | Test control system and method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111383704B (en) | 2022-07-26 |
| WO2020134572A1 (en) | 2020-07-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9244883B2 (en) | Reconfigurable processor and method of reconfiguring the same | |
| KR20210038288A (en) | Method and apparatus for testing artificial intelligence chip, device and storage medium | |
| US11275661B1 (en) | Test generation of a distributed system | |
| US9395992B2 (en) | Instruction swap for patching problematic instructions in a microprocessor | |
| CN111383704B (en) | Built-in self-test circuit of memory and test method for memory | |
| CN111666210A (en) | Chip verification method and device | |
| US8701074B2 (en) | Automatic reduction of modes of electronic circuits for timing analysis | |
| US20210263837A1 (en) | Real time fault localization using combinatorial test design techniques and test case priority selection | |
| CN117907812B (en) | Circuit detection method and device, electronic device, storage medium, and program product | |
| US10684834B2 (en) | Method and apparatus for detecting inter-instruction data dependency | |
| Ibrahim et al. | An on-chip IEEE 1687 network controller for reliability and functional safety management of system-on-chips | |
| Eisenhardt et al. | Spatial and temporal data path remapping for fault-tolerant coarse-grained reconfigurable architectures | |
| CN109145338B (en) | Method and device for repairing voltage drop | |
| US11500639B2 (en) | Arithmetic processing apparatus and control method using ordering property | |
| US20200349304A1 (en) | Method, apparatus, device, and medium for implementing simulator | |
| US10997087B2 (en) | Direct memory access | |
| US20100199284A1 (en) | Information processing apparatus, self-testing method, and storage medium | |
| US8726206B1 (en) | Deadlock detection method and related machine readable medium | |
| US20090249132A1 (en) | Data Processing Apparatus and Method of Verifying Programs | |
| JP5279817B2 (en) | Test apparatus and test method | |
| US7945433B2 (en) | Hardware simulation accelerator design and method that exploits a parallel structure of user models to support a larger user model size | |
| JP2021005379A (en) | Method for detecting deep learning chip, device, electronic apparatus, and computer storage medium | |
| JP6473023B2 (en) | Performance evaluation module and semiconductor integrated circuit incorporating the same | |
| CN117313595B (en) | Random instruction generation method, equipment and system for function verification | |
| CN113742198B (en) | Test method, test device, electronic equipment and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |