CN111370388A - 一种芯片的封装结构及其封装方法 - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 57
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 36
- 239000010410 layer Substances 0.000 claims abstract description 91
- 239000010931 gold Substances 0.000 claims abstract description 57
- 229910052737 gold Inorganic materials 0.000 claims abstract description 57
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 51
- 239000002184 metal Substances 0.000 claims abstract description 45
- 229910052751 metal Inorganic materials 0.000 claims abstract description 45
- 239000011241 protective layer Substances 0.000 claims abstract description 28
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910021389 graphene Inorganic materials 0.000 claims abstract description 18
- 239000012790 adhesive layer Substances 0.000 claims abstract description 14
- 239000011247 coating layer Substances 0.000 claims abstract description 10
- 230000002093 peripheral effect Effects 0.000 claims abstract description 7
- 239000000463 material Substances 0.000 claims description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims description 18
- 238000009713 electroplating Methods 0.000 claims description 11
- 229910052802 copper Inorganic materials 0.000 claims description 9
- 239000003292 glue Substances 0.000 claims description 9
- 229910052759 nickel Inorganic materials 0.000 claims description 9
- 238000001259 photo etching Methods 0.000 claims description 9
- 229910052719 titanium Inorganic materials 0.000 claims description 9
- 239000011521 glass Substances 0.000 claims description 8
- 238000000227 grinding Methods 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 8
- 238000004544 sputter deposition Methods 0.000 claims description 7
- 239000007769 metal material Substances 0.000 claims description 6
- 229910052718 tin Inorganic materials 0.000 claims description 6
- 229910010165 TiCu Inorganic materials 0.000 claims description 5
- 238000005260 corrosion Methods 0.000 claims description 5
- 230000007797 corrosion Effects 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 5
- 238000003825 pressing Methods 0.000 claims description 5
- 239000000853 adhesive Substances 0.000 claims description 4
- 230000001070 adhesive effect Effects 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 238000007639 printing Methods 0.000 claims description 4
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 claims description 3
- 230000009471 action Effects 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 238000007772 electroless plating Methods 0.000 claims description 3
- 239000003822 epoxy resin Substances 0.000 claims description 3
- 239000011344 liquid material Substances 0.000 claims description 3
- 229920001568 phenolic resin Polymers 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- 238000005507 spraying Methods 0.000 claims description 3
- 229920001169 thermoplastic Polymers 0.000 claims description 3
- 229920001187 thermosetting polymer Polymers 0.000 claims description 3
- 239000004634 thermosetting polymer Substances 0.000 claims description 3
- 239000004416 thermosoftening plastic Substances 0.000 claims description 3
- 239000002253 acid Substances 0.000 claims description 2
- 239000005007 epoxy-phenolic resin Substances 0.000 claims description 2
- 238000011049 filling Methods 0.000 claims description 2
- 238000005538 encapsulation Methods 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 239000012634 fragment Substances 0.000 abstract description 2
- 238000013467 fragmentation Methods 0.000 abstract 1
- 238000006062 fragmentation reaction Methods 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 6
- 239000002131 composite material Substances 0.000 description 5
- 238000005520 cutting process Methods 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 238000005253 cladding Methods 0.000 description 3
- 238000012858 packaging process Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 229910003336 CuNi Inorganic materials 0.000 description 1
- 239000003929 acidic solution Substances 0.000 description 1
- 125000003277 amino group Chemical group 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002923 metal particle Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000009972 noncorrosive effect Effects 0.000 description 1
- 239000004482 other powder Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 238000006748 scratching Methods 0.000 description 1
- 230000002393 scratching effect Effects 0.000 description 1
- 229910002027 silica gel Inorganic materials 0.000 description 1
- 239000000741 silica gel Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
- 238000005491 wire drawing Methods 0.000 description 1
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Abstract
本发明公开了一种芯片的封装结构及其封装方法,属于半导体封装技术领域。其芯片本体(100)的有源表面和芯片电极(101)的上表面设置有保护层(200),所述保护层(200)在芯片电极(101)上方开设保护层开口(201),所述保护层开口(201)内设置金属凸块(300),所述金属凸块(300)通过保护层开口(201)与芯片电极(101)连接;所述芯片本体(100)的背面依次设置有粘附层(601)、种子层(602),所述粘附层(601)覆盖芯片本体(100)的背面;所述种子层(602)的下表面依次设置背金块(600)和石墨烯层(610),所述包覆层(700)包覆背金块(600)裸露面,并向上延展至粘附层(601)的下表面的四周边缘。本发明能够有效地克服晶圆翘曲及碎片、降低划片难度、解决封装成品产生的翘曲及碎裂等问题。
Description
技术领域
本发明涉及一种芯片的封装结构及其封装方法,属于半导体芯片封装技术领域。
背景技术
随着半导体产业的发展,对电子产品的性能要求不断提升。对于以MOSFET为代表的电源产品,需要不断降低芯片的厚度、同时增加芯片背面金属(简称背金)的厚度,以此实现电阻的降低、以及产品性能的提升;目前这类产品的芯片厚度最薄达到50微米,同时背金最厚达到50微米;并且随着产品电阻的不断降低的趋势,芯片厚度需要进一步降低、背金厚度需要进一步增加。
现有芯片封装结构如图1所示,芯片上设置有保护层及凸块,芯片背面设置有背金。其封装方法为:在晶圆正面通过光刻形成保护层,通过电镀或化学镀形成凸块,对晶圆背面进行磨片及蒸发沉积金属,然后用切成单颗芯片。
随着芯片厚度的持续降低以及背金厚度的不断增加,现有的封装方法存在以下问题:1,由于晶圆很薄,划片时受到切削力时会产生抖动;加上背金很厚,直接划过厚背金时金属会粘刀及切割拉丝;这容易引起芯片崩裂,导致划片难度很大。2,背金材料中经常含有Cu等容易扩散到芯片内的金属,厚的背金在划片时容易形成拉丝,含Cu的金属丝与芯片接触后会扩散到芯片内部,导致芯片功能失效。封装成品存在以下问题:1,芯片比较薄、背金比较厚,由于芯片和背金的热膨胀系数的差异,芯片会产生翘曲,导致在SMT(表面贴片)时产生虚焊;2,封装成品的机械强度与芯片厚度直接相关,随着芯片厚度的降低,封装成品的强度降低,后续使用时容易出现碎裂,导致可靠性问题。
发明内容
本发明的目的在于克服现有封装技术不足,提供一种能够降低划片难度、避免背金扩散到芯片内部导致功能失效、解决封装成品产生翘曲及碎裂的芯片的封装结构及其封装方法。
本发明的目的是这样实现的:
本发明一种芯片的封装结构,其包括具有有源表面的芯片本体,所述芯片本体的有源表面设置有芯片电极,所述芯片本体的有源表面和芯片电极的上表面设置有保护层,所述保护层在芯片电极上方开设保护层开口,所述保护层开口内设置金属凸块,所述金属凸块通过保护层开口与芯片电极连接;
所述芯片本体的背面依次设置有粘附层、种子层,所述粘附层覆盖芯片本体的背面;
所述种子层的横截面小于芯片本体的横截面和/或粘附层的横截面,并露出粘附层的下表面的四周边缘;
所述种子层的下表面依次设置背金块和石墨烯层,其覆盖面积相等;
还包括包覆层,所述包覆层包覆背金块裸露面,并向上延展至粘附层的下表面的四周边缘。
进一步地,所述金属凸块的金属材质包括但不限于Ti、Cu、Ni、Sn、Au元素。
进一步地,所述背金块的材质包括但不限于TiNiAg、TiNiAgNi、CrCu、CrCuCr,TiCu、TiCuTi、TiCuNi。
本发明还提供了一种芯片的封装结构的封装方法,工艺步骤如下:
步骤一、提供一晶圆,晶圆上设有横向和纵向交织的划片道将其划分为复数颗阵列排布的芯片单元,芯片单元的芯片本体的有源表面设置有芯片电极;
步骤二、通过光刻的方法,在晶圆的表面选择性的形成保护层,并开设保护层开口露出芯片电极的上表面;
步骤三、依次通过溅射、光刻、电镀、去胶及腐蚀的方法,在保护层开口内形成金属凸块,与芯片电极形成互联;
步骤四、通过键合的方法,用键合胶将载片与晶圆键合在一起,键合方法通常为将键合胶涂敷或压合在晶圆表面,然后与载片在压力、温度、真空的作用下粘合到一起;
步骤五、通过磨片的方法,对晶圆的芯片本体的背面进行减薄,磨片后通过化学腐蚀改变芯片本体的微观形貌;
步骤六、通过溅射的方法,依次在晶圆背面沉积粘附层及种子层。
步骤七、通过光刻的方法,在晶圆上形成光刻胶层,并形成阵列状的光刻胶层开口,然后通过电镀的方法,在光刻胶层开口内电镀沉积背金块,并形成有间隔的背金块阵列;
步骤八、再在背金块阵列的背面喷涂石墨烯,形成石墨烯层;
步骤九、通过有机溶液去除光刻胶,通过酸性溶液腐蚀掉种子层,形成金属开口,同时保留粘附层不被腐蚀;
步骤十、通过压膜、印刷或包封的方法,使包覆层包覆于背金块的裸露面,并填充金属开口;
步骤十一、通过解键合的方法,将载片与晶圆分离,并且去除键合胶;
步骤十二、通过划片的方法,沿划片道将晶圆划成芯片封装结构。
进一步地,步骤三中,金属凸块的形成通过化学镀的方法形成,所述金属凸块的金属材质包括但不限于Ti、Cu、Ni、Sn、Au元素。
进一步地,步骤四中,键合胶材料为热塑性的液态材料,或者为对UV光敏感的薄膜材料。
进一步地,步骤六中,背金块包括但不限于CrCu、TiCu、TiCu、TiCuNi、TiCuNiAu。
进一步地,步骤六中,粘附层包括但不限于Cr、Ti、TiW、V、NiV;所述粘附层的厚度为0.01~3微米;所述种子层包括但不限于Cu、Ni,所述种子层的厚度为0.01~1微米。
进一步地,步骤九中,包覆层的材质为热固性高分子材料,包括但不限于环氧树脂、酚醛树脂。
进一步地,步骤十中,解键合包括但不限于热解键合、化学解键合、激光解键合或者UV解键合。
有益效果
1、本发明通过由晶圆、背金块、石墨烯层和包封层形成的复合晶圆结构,增加了晶圆封装工艺过程中的强度,克服了切割时切削力导致的抖动问题;通过设置背金块间隔,解决了直接划过厚背金块时的粘刀问题,减少了划片造成的芯片崩裂不良,降低了划片难度;
2、本发明将背金块形成间隔,避免直接划过厚的背金块引起的金属拉丝问题,以及引起的背金材料中Cu等易扩散的金属扩散到芯片内部而造成的芯片功能失效的问题;同时,工艺上不腐蚀粘附层,保留的粘附层确保了种子层及背金与芯片本体之间有完整的扩散阻挡层,有效地避免了金属原子扩散造成的芯片功能失效;
3、本发明通过由芯片、背金块和石墨烯层及包封层形成的复合封装体结构,增加了芯片封装结构成品的刚性,克服封装成品翘曲问题,解决了SMT虚焊;以及通过复合封装体结构,提高了芯片封装成品的机械强度和散热能力,克服了碎片封装成品问题,提升了可靠性。
附图说明
图1为传统芯片封装结构示意图;
图2为本发明芯片的封装结构的封装流程图;
图3为本发明芯片的封装结构的剖面示意图;
图3为本发明芯片的封装结构的实施例的剖面示意图;
图4A至4O为本发明芯片的封装结构的封装方法的剖面示意图;
图中:
晶圆10A
芯片本体100
芯片电极101
保护层 200
凸块300
键合胶400
载片500
背金块600
粘附层 601
种子层 602
石墨烯层610
包覆层700
划片道 900。
具体实施方式
下面结合附图对本发明的具体实施方式进行详细说明。
参照图1,本发明一种芯片的封装结构的封装流程如下:
执行步骤S101:提供晶圆;
执行步骤S102:通过光刻的方法在晶圆表面选择性的形成保护层;
执行步骤S103:通过电镀或者化学镀的方法,制作金属凸块;
执行步骤S104:通过键合的方法将载片与晶圆键合起来;
执行步骤S105:通过磨片的方法对晶圆的背面进行减薄;
执行步骤S106:通过溅射的方法,在晶圆背面形成粘附层及种子层;
执行步骤S107:通过光刻的方法,在晶圆上选择性的形成光刻胶,并通过电镀的方法形成背金块阵列;
执行步骤S108:在背金块阵列的背面形成石墨烯层;
执行步骤S109:去除光刻胶,腐蚀种子层,同时保留粘附层不腐蚀;
执行步骤S110:通过压膜、印刷或包封的方法,使包覆层包覆于背金块、并填充于背金块的间隔处;
执行步骤S111:通过解键合的方法将载片与晶圆分离,并且去除键合胶;
执行步骤S112:通过划片的方法,将晶圆划成单颗芯片封装结构。
实施例
本发明一种芯片的封装结构,如图3所示;为本发明芯片封装结构的剖面示意图。其包括具有有源表面的芯片本体100,芯片本体100厚度为25~150微米。在芯片本体100的有源表面设置有芯片电极101,在芯片的有源表面和芯片电极101的上表面设置有保护层200,保护层200包括但不限于钝化层、绝缘层。保护层200在芯片电极101上方开设保护层开口201,在保护层开口201内设置金属凸块300。金属凸块300的材质为含有Ti、Cu、Ni、Sn、Au元素的金属材料,金属凸块300的高度通常为2~100微米。
金属凸块300通过保护层开口201与芯片电极101连接。金属凸块300的横截面形状根据实际需要设计,包括但不限于矩形、圆形、椭圆形。
芯片本体100的背面依次设置有粘附层601、种子层602,粘附层601覆盖芯片本体100的背面。种子层602的横截面小于芯片本体100的横截面和/或粘附层601的横截面,并露出粘附层601的下表面的四周边缘;
种子层602的下表面依次设置背金块600和石墨烯层610,其覆盖面积相等。
背金块600的材质通常为TiNiAg、TiNiAgNi、CrCu、CrCuCr,TiCu、TiCuTi、TiCuNi等多层材料;背金块600的厚度通常为10~100微米。
包覆层700包覆背金块600裸露面,并向上延展至粘附层601的下表面的四周边缘,起支撑保护作用。
本发明一种芯片的封装结构的封装方法,图4A至图4O为芯片封装方法的示意图。其工艺步骤如下:
步骤一、参见图4A和4B,提供一晶圆10A,图4A为晶圆的俯视示意图;晶圆10A上设有横向和纵向交织的划片道900将其划分为复数颗阵列排布的芯片单元10B,芯片单元10B的芯片本体100的有源表面设置有芯片电极101。
步骤二、参见图4C,通过光刻的方法,在晶圆10A的表面选择性的形成保护层200,并开设保护层开口201露出芯片电极101的上表面。
步骤三、参见图4D,依次通过溅射、光刻、电镀、去胶及腐蚀的方法,在保护层开口201内形成金属凸块300,与芯片电极101形成互联。金属凸块300的形成也可以通过化学镀的方法形成。金属凸块300材料为含有Ti、Cu、Ni、Sn、Au元素的金属材料,金属凸块300的高度通常为2~100微米。
步骤四、参见图4E,通过键合的方法,用键合胶400将载片500与晶圆10A键合在一起。键合方法通常为将键合胶400涂敷或压合在晶圆10A表面,然后与载片500在压力、温度、真空的作用下粘合到一起。优选的,键合胶400材料为热塑性的液态材料,或者为对UV光敏感的薄膜材料。
步骤五、参见图4F,通过磨片的方法,对晶圆10A的芯片本体100的背面进行减薄;磨片可以是机械研磨,也可以是化学机械研磨。通常的,在磨片后增加化学腐蚀来改变芯片本体100的微观形貌,以此增加后续的背金块600与芯片本体100的结合力。磨片后芯片本体100的厚度通常为25~150微米。
步骤六、参见图4G,通过溅射的方法,依次在晶圆10A背面沉积粘附层601及种子层602。粘附层601的材质为Cr、Ti、TiW、V、NiV等,可以是一层或两层材料构成的复合层,粘附层601的厚度为0.01~3微米。种子层602的材质为Cu、Ni等,种子层602的厚度为0.01~1微米。粘附层601除了起到与芯片本体101 结合外,还起到阻挡种子层601及背金块600的金属原子或其他金属粒子扩散到芯片本体100中。
步骤七、参见图4H和4I,通过光刻的方法,在晶圆上形成光刻胶层603,并形成阵列状的光刻胶层开口604。然后通过电镀的方法,在光刻胶层开口604内电镀沉积背金块600;背金块600的材料通常为Cu、CuNi、CuNiAu、NiAu等材料,背金块600的厚度为5~100微米。由于保留有光刻胶层603的区域不能被电镀上,所以形成有间隔的背金块阵列。
步骤八、参见图4J,再在背金块阵列的背面喷涂石墨烯,形成石墨烯层610;
步骤九、参见图4K,通过有机溶液如丙酮、NMP等去除光刻胶603,通过酸性溶液腐蚀掉种子层602,形成金属开口604,同时保留粘附层601不被腐蚀。粘附层601不腐蚀的目的在于确保种子层601及背金块600与芯片本体100之间有完整的扩散阻挡层。
步骤十、参见图4L,通过压膜、印刷或包封的方法,使包覆层700包覆于背金块600的裸露面,并填充金属开口604。优选的,粘接层700的材料为热固性高分子如环氧树脂、酚醛树脂、硅胶、氨基、不饱和树脂;为了提高散热能力,粘阶层可以为含有金属、陶瓷、氧化硅、石墨烯等粉末或纤维的复合材料;包覆层700的厚度为25~200微米。
步骤十一、参见图4M,通过解键合的方法,将载片500与晶圆10A分离,并且去除键合胶400;解键合可以是热解键合、化学解键合、激光解键合或者UV解键合等。
步骤十二、参见图4N和4O,通过划片的方法,沿划片道900将晶圆10A划成单颗芯片封装结构;划片可以用含有金刚石或者陶瓷颗粒的刀片,也可以选用激光进行切割。
以上所述的具体实施方式,对本发明的目的、技术方案和有益效果进行了进一步地详细说明,所应理解的是,以上所述仅为本发明的具体实施方式而已,并不用于限定本发明的保护范围,凡在本发明的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (10)
1.一种芯片的封装结构,其包括具有有源表面的芯片本体(100),所述芯片本体(100)的有源表面设置有芯片电极(101),
其特征在于,所述芯片本体(100)的有源表面和芯片电极(101)的上表面设置有保护层(200),所述保护层(200)在芯片电极(101)上方开设保护层开口(201),所述保护层开口(201)内设置金属凸块(300),所述金属凸块(300)通过保护层开口(201)与芯片电极(101)连接;
所述芯片本体(100)的背面依次设置有粘附层(601)、种子层(602),所述粘附层(601)覆盖芯片本体(100)的背面;
所述种子层(602)的横截面小于芯片本体(100)的横截面和/或粘附层(601)的横截面,并露出粘附层(601)的下表面的四周边缘;
所述种子层(602)的下表面依次设置背金块(600)和石墨烯层(610),其覆盖面积相等;
还包括包覆层(700),所述包覆层(700)包覆背金块(600)裸露面,并向上延展至粘附层(601)的下表面的四周边缘。
2.根据权利要求1所述的芯片的封装结构,其特征在于,所述金属凸块(300)的金属材质包括但不限于Ti、Cu、Ni、Sn、Au元素。
3.根据权利要求1所述的芯片的封装结构,其特征在于,所述背金块(600)的材质包括但不限于TiNiAg、TiNiAgNi、CrCu、CrCuCr,TiCu、TiCuTi、TiCuNi。
4.一种芯片的封装结构的封装方法,工艺步骤如下:
步骤一、提供一晶圆(10A),晶圆(10A)上设有横向和纵向交织的划片道(900)将其划分为复数颗阵列排布的芯片单元(10B),芯片单元(10B)的芯片本体(100)的有源表面设置有芯片电极(101);
步骤二、通过光刻的方法,在晶圆(10A)的表面选择性的形成保护层(200),并开设保护层开口(201)露出芯片电极(101)的上表面;
步骤三、依次通过溅射、光刻、电镀、去胶及腐蚀的方法,在保护层开口(201)内形成金属凸块(300),与芯片电极(101)形成互联;
步骤四、通过键合的方法,用键合胶(400)将载片(500)与晶圆(10A)键合在一起,键合方法通常为将键合胶(400)涂敷或压合在晶圆(10A)表面,然后与载片(500)在压力、温度、真空的作用下粘合到一起;
步骤五、通过磨片的方法,对晶圆(10A)的芯片本体(100)的背面进行减薄,磨片后通过化学腐蚀改变芯片本体(100)的微观形貌;
步骤六、通过溅射的方法,依次在晶圆(10A)背面沉积粘附层(601)及种子层(602);
步骤七、通过光刻的方法,在晶圆上形成光刻胶层(603),并形成阵列状的光刻胶层开口(604),然后通过电镀的方法,在光刻胶层开口(604)内电镀沉积背金块(600),并形成有间隔的背金块阵列;
步骤八、再在背金块阵列的背面喷涂石墨烯,形成石墨烯层(610);
步骤九、通过有机溶液去除光刻胶(603),通过酸性溶液腐蚀掉种子层(602),形成金属开口(604),同时保留粘附层(601)不被腐蚀;
步骤十、通过压膜、印刷或包封的方法,使包覆层(700)包覆于背金块(600)的裸露面,并填充金属开口(604);
步骤十一、通过解键合的方法,将载片(500)与晶圆(10A)分离,并且去除键合胶(400);
步骤十二、通过划片的方法,沿划片道(900)将晶圆(10A)划成芯片封装结构。
5.根据权利要求4所述的封装方法,其特征在于,步骤三中,金属凸块(300)的形成通过化学镀的方法形成,所述金属凸块(300)的金属材质包括但不限于Ti、Cu、Ni、Sn、Au元素。
6.根据权利要求5所述的封装方法,其特征在于,步骤四中,键合胶(400)材料为热塑性的液态材料,或者为对UV光敏感的薄膜材料。
7.根据权利要求6所述的封装方法,其特征在于,步骤六中,背金块(600)包括但不限于CrCu、TiCu、TiCu、TiCuNi、TiCuNiAu。
8.根据权利要求7所述的封装方法,其特征在于,步骤六中,粘附层(601)包括但不限于Cr、Ti、TiW、V、NiV;所述粘附层(601)的厚度为0.01~3微米;所述种子层(602)包括但不限于Cu、Ni,所述种子层(602)的厚度为0.01~1微米。
9.根据权利要求8所述的封装方法,其特征在于,步骤九中,包覆层(700)的材质为热固性高分子材料,包括但不限于环氧树脂、酚醛树脂。
10.根据权利要求9所述的封装方法,其特征在于,步骤十中,解键合包括但不限于热解键合、化学解键合、激光解键合或者UV解键合。
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US11641713B2 (en) | 2021-03-31 | 2023-05-02 | Unimicron Technology Corp. | Circuit board structure and manufacturing method thereof |
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US11641713B2 (en) | 2021-03-31 | 2023-05-02 | Unimicron Technology Corp. | Circuit board structure and manufacturing method thereof |
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