CN111368928A - Wafer pattern matching method and device, electronic equipment and storage medium - Google Patents
Wafer pattern matching method and device, electronic equipment and storage medium Download PDFInfo
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Abstract
The invention provides a wafer pattern matching method, a wafer pattern matching device, electronic equipment and a storage medium, wherein the wafer pattern matching method comprises the following steps: obtaining test data of each bare chip in a plurality of bare chips of a wafer to be matched; and determining a target mode matched with the wafer to be matched in the M candidate modes according to the test data of the N bare chips and the N standard data of each of the M candidate modes, wherein N is an integer greater than or equal to 2, and M is an integer greater than or equal to 1.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a method and an apparatus for pattern matching of a wafer, an electronic device, and a storage medium.
Background
With the development of integrated circuit technology, the amount of data generated during production and development is larger and larger, and the test data of all circuits on a 12-inch wafer can reach hundreds of gb (gigabyte). The big data contains abundant information, some information is related, and some information is not related.
In order to facilitate learning of defects, problems, or other phenomena of the wafer, the test data may be analyzed, and in the related art, the test data may be observed, counted, and analyzed manually, however, the manual method has a large workload and is difficult to ensure accuracy.
Disclosure of Invention
The invention provides a wafer pattern matching method and device, electronic equipment and a storage medium, and aims to solve the problems that the workload is large in a manual mode and the accuracy is difficult to guarantee.
According to a first aspect of the present invention, there is provided a method for pattern matching of a wafer, including:
obtaining test data of each bare chip in a plurality of bare chips of a wafer to be matched;
and determining a target mode matched with the wafer to be matched in the M candidate modes according to the test data of the N bare chips and the N standard data of each of the M candidate modes, wherein N is an integer greater than or equal to 2, and M is an integer greater than or equal to 1.
Optionally, determining, according to the test data of the N bare chips and the N standard data of each candidate mode of the M candidate modes, a target mode matched with the wafer to be matched in the M candidate modes includes:
calculating correlation information of the test data of the N bare chips and N standard data of each candidate mode in the M candidate modes; and/or: calculating similarity information between the test data of the N bare chips and N standard data of each candidate mode in the M candidate modes;
if only the correlation information is obtained by calculation, then: determining the target mode according to the correlation information;
if only the similarity information is obtained through calculation, the following steps are carried out: determining the target mode according to the similarity information;
if the correlation information and the similarity information are obtained through calculation, then: and determining the target mode according to the correlation information and the similarity information.
Optionally, determining the target mode according to the correlation information and the similarity information includes:
and if the correlation information corresponding to any one current candidate mode in the candidate modes is greater than a preset correlation threshold value and the similarity information corresponding to the current candidate mode is also greater than a preset similarity threshold value, determining that the current candidate mode is the target mode.
Optionally, the similarity information is Jaccard similarity information.
Optionally, before the test data of the N bare chips and the N standard data of each of the M candidate patterns, the method includes:
determining the N bare chips in the plurality of bare chips according to first position information and second position information of a single candidate mode, wherein the first position information is used for representing the positions of the corresponding bare chips in the wafer to be matched, the second position information is predefined position information for each standard data in the single candidate mode, and the first position information of each bare chip in the N bare chips is matched with the second position information of one standard data.
Optionally, after determining the N die in the plurality of die according to the first location information and the second location information of the single candidate mode, the method further includes:
and if the N is determined to be smaller than the preset number threshold, determining that the wafer to be matched is not matched with each candidate mode.
Optionally, the test data of the N bare chips is already eliminated with abnormal values, and the abnormal values include maximum values and/or minimum values.
According to a second aspect of the present invention, there is provided a wafer pattern matching apparatus, comprising:
the device comprises an acquisition module, a matching module and a comparison module, wherein the acquisition module is used for acquiring the test data of each bare chip in a plurality of bare chips of a wafer to be matched;
and the matching module is used for determining a target mode matched with the wafer to be matched in the M candidate modes according to the test data of the N bare chips and the N standard data of each of the M candidate modes, wherein N is an integer greater than or equal to 2, and M is an integer greater than or equal to 1.
According to a third aspect of the invention, there is provided an electronic device comprising a processor and a memory,
the memory is used for storing codes and related data;
the processor is configured to execute the codes in the memory to implement the wafer pattern matching method of any one of claims 1 to 7.
According to a fourth aspect of the present invention, there is provided a storage medium having stored thereon a computer program which, when executed by a processor, implements the method of pattern matching for wafers according to the first aspect and alternatives thereof.
In the wafer pattern matching method, device, electronic equipment and storage medium provided by the invention, the test data of the wafer can have a certain pattern due to partial defects, problems or other phenomena of the wafer, so that in the invention, under the condition that the candidate pattern and the standard data thereof are preset, the target pattern matched with the wafer to be matched can be determined in M candidate patterns by taking the test data of bare chips in the wafer as the basis, and further, the defects, problems or other phenomena of the wafer can be conveniently determined through the matching of the wafer patterns, thus the defects, problems or other phenomena of the wafer can be assisted to be determined based on the patterns, and the workload can be effectively reduced. Meanwhile, if the human eyes find the similar test data mode, the work which still wastes time and labor is extremely time-consuming, so that the processing process based on the invention can be realized without manpower, the workload is further reduced, the processing efficiency is improved, and better mode matching accuracy can be ensured.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a first flowchart illustrating a wafer pattern matching method according to an embodiment of the present invention;
FIG. 2a is a schematic diagram illustrating the distribution of modeless standard data in an embodiment of the present invention;
FIG. 2b is a schematic diagram of a test data distribution of a pattern according to an embodiment of the present invention;
FIG. 2c is a schematic diagram of another exemplary test data distribution according to an embodiment of the present invention;
FIG. 2d is a schematic diagram of test data distribution for another embodiment of the present invention;
FIG. 3a is a diagram illustrating test data according to an embodiment of the present invention;
FIG. 3b is a diagram illustrating standard data of candidate patterns according to an embodiment of the present invention;
FIG. 4 is a flowchart illustrating step S12 according to an embodiment of the present invention;
FIG. 5 is a flowchart illustrating step S123 according to an embodiment of the present invention;
FIG. 6 is a second flowchart illustrating a wafer pattern matching method according to an embodiment of the present invention;
FIG. 7 is a first block diagram illustrating a first process of a wafer pattern matching apparatus according to an embodiment of the present invention;
FIG. 8 is a second block diagram of a wafer pattern matching apparatus according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of an electronic device in an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The technical solution of the present invention will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
Fig. 1 is a first flowchart illustrating a wafer pattern matching method according to an embodiment of the present invention. FIG. 2a is a schematic diagram illustrating the distribution of modeless standard data in an embodiment of the present invention; FIG. 2b is a schematic diagram of a test data distribution of a pattern according to an embodiment of the present invention; FIG. 2c is a schematic diagram of another exemplary test data distribution according to an embodiment of the present invention; FIG. 2d is a schematic diagram of test data distribution of another embodiment of the present invention. FIG. 3a is a diagram illustrating test data according to an embodiment of the present invention;
FIG. 3b is a diagram illustrating standard data of candidate patterns according to an embodiment of the present invention;
referring to fig. 1 to 3, a method for pattern matching of a wafer includes:
s11: obtaining test data of each bare chip in a plurality of bare chips of a wafer to be matched;
s12: and determining a target mode matched with the wafer to be matched in the M candidate modes according to the test data of the N bare chips and the N standard data of each of the M candidate modes, wherein N is an integer greater than or equal to 2, and M is an integer greater than or equal to 1.
The bare chip, which may also be referred to as a die, may be characterized as die. Each wafer may be divided into a plurality of die. The test data of the N bare chips may be understood as test data of all the bare chips for determining the target mode, which may be part or all of all the bare chips of the wafer to be matched.
The test data may be any data to be tested, for example, current data or voltage data, which may be three columns of data, such as parameter1, parameter2 and parameter3 shown in fig. 3 a. Furthermore, based on the Test data, the Test data may be used to form a wafer Defect Pattern (Defect Pattern), a circuit probing Pattern (CPPattern), an Electrical performance Test Pattern (Electrical Test Pattern), and the like, in other words, the Test data that can provide direct or indirect basis for the formation of these patterns may also be regarded as the Test data according to the present embodiment.
The modes therein can be understood as: in the wafer classified as the same mode, the test data of each bare chip is distributed in a specific manner, and further, the standard data of the candidate mode can be understood as a set of data predefined for the specific distribution manner, so that it is convenient to distinguish whether a certain test data belongs to the specific distribution manner.
The standard data can be determined by means of statistics, experiments, theoretical calculation, machine learning and the like of empirical data, and the standard data corresponding to one mode can be fixed or variable. In any way, and whether or not it is itself changed, as long as the standard data has been determined before the implementation of step S12 and can be used in step S12, it does not depart from the description of the present embodiment. The standard data may be, for example, the data of parameter0 shown in fig. 3 b.
The particular distribution may further indicate that the values of the test data are clustered in one or more regions of the wafer, where clustering may indicate that the data in the regions are the same or similar.
Taking fig. 2b to 2d as an example, the color map is formed by converting the color map into a gray scale map, in the color map, colors can be filled in the positions of each die of the wafer, different colors can be used to represent different values of the test data, and the aggregation of a certain color (or its close color) can represent the aggregation of a certain value or a certain value range.
When the color map is converted into a gray scale map, in fig. 2b to 2d, since the colors representing a certain value or a certain value interval can be displayed as the same or similar gray scale, the following steps are performed: where a partial region may be considered as having been aggregated, for example: in fig. 2b, the dark area to the upper left in the middle can be regarded as the aggregation; for example, in fig. 2c, the ring-shaped region with dark middle and the ring-shaped region with dark edge can be regarded as having aggregation, and for example, in fig. 2d, the ring-shaped region with dark middle and right side can be regarded as having aggregation; of course, the aggregation in fig. 2b to 2d is not limited to the above list.
In some embodiments, as shown in fig. 2a, the test data of the wafer may not be aggregated, which may be regarded as having no pattern.
Furthermore, in the solution of the present embodiment, based on the test data and the standard data, it can be determined exactly which candidate mode the test data belongs to and whether the test data belongs to the candidate mode.
In this embodiment, it can be seen that, creatively: the partial defects, problems or other phenomena of the wafer can enable the test data of the wafer to have a certain mode, based on the mode, under the condition that the candidate mode and the standard data thereof are preset, the target mode matched with the wafer to be matched can be determined in the M candidate modes by taking the test data of the bare chips in the wafer as the basis, and further, the defects, the problems or other phenomena of the wafer can be conveniently determined through the matching of the wafer modes.
Meanwhile, in the process, manual observation and statistical analysis are not needed, the workload is reduced, the processing efficiency is improved, and better pattern matching accuracy (namely the accuracy of classification of defects, problems and phenomena of the wafer) can be ensured.
In addition, the correspondence between each pattern and the defect, problem, or other phenomenon of the wafer may be determined in advance, or the wafer corresponding to each determined target pattern may be analyzed to find the defect, problem, or other phenomenon. The samples in the same mode can be classified, and the commonality of design of experiments (DOE) can be conveniently found out through the data of each type of samples.
Fig. 4 is a flowchart illustrating step S12 according to an embodiment of the present invention.
Referring to fig. 4, in one embodiment, step S12 may include:
s121: calculating correlation information of the test data of the N bare chips and N standard data of each candidate mode in the M candidate modes;
s122: calculating similarity information between the test data of the N bare chips and N standard data of each candidate mode in the M candidate modes;
s123: and determining the target mode according to the correlation information and the similarity information.
The correlation information is understood to be information for characterizing the correlation between the variation of the test data with the variation of the die position and the variation of the standard data with the variation of the die position. In the change of the test data and the standard data along with the change of the die position, the more similar the change trend is, the higher the correlation represented by the correlation information is, and the more likely the correlation information belongs to the same mode.
Specifically, each test data and standard data may be sorted according to the X-direction and Y-direction positions of each die (for example, die _ X and die _ Y shown in the figure), so as to form a column of data, the sorting manner of the test data and the standard data is the same, and further, the change of the test data along with the change of the die position may be understood as the change of the test data along with the change of the row number, and the change of the standard data along with the change of the die position may be understood as the change of the standard data along with the change of the row number.
In a specific implementation, the correlation information may specifically include a correlation coefficient (e.g., a linear correlation coefficient) between the test data and the standard data.
The similarity information may be any information representing the similarity between the test data and the standard data. The higher the similarity represented by the similarity information is, the more likely it belongs to the same pattern.
In a specific implementation process, the similarity information may be a Jaccard similarity, which may also be characterized as a Jaccard coefficient, a Jaccard similarity coefficient, or a Jaccard coefficient; wherein the larger the value of Jaccard similarity, the higher the similarity characterized.
Fig. 5 is a flowchart illustrating step S123 according to an embodiment of the present invention.
Referring to fig. 5, in one embodiment, for a current candidate mode in any one of a plurality of candidate modes, step S123 may include:
s1231: whether the correlation information corresponding to the current candidate mode is larger than a preset correlation threshold value or not;
s1232: whether the similarity information corresponding to the current candidate mode is larger than a preset similarity threshold value or not;
if the determination results in step S1231 and step S1232 are both yes, step S1233 may be performed: determining the current candidate mode as the target mode.
In this embodiment, at least one of the correlation information and the similarity information that does not reach the corresponding threshold may be regarded as the wafer to be matched does not belong to the current candidate pattern.
In the embodiment shown in fig. 4 and 5, step S121, step S122, step S1231, and step S1232 may be performed, and in other embodiments, only step S121 or only step S122 may be performed.
If only step S121 is implemented, the target mode may be determined according to the correlation information; for example: if the correlation information corresponding to the current candidate mode is larger than a preset correlation threshold, determining that the current candidate mode is the target mode;
if only step S122 is performed, the target mode may be determined according to the similarity information; for example: if the similarity information corresponding to the current candidate mode is larger than a preset similarity threshold, determining that the current candidate mode is the target mode;
the correlation threshold and the similarity threshold may be preset arbitrary values, which may be determined empirically, and may be the same as or different from each other, and in an example, both the correlation threshold and the similarity threshold may be 0.5.
Fig. 6 is a second flowchart illustrating a wafer pattern matching method according to an embodiment of the invention.
Referring to fig. 6, before step S12, the method may further include:
s13: determining the N die in the plurality of die based on the first location information and second location information of the single candidate pattern.
The first position information is used to represent the position of the corresponding die in the wafer to be matched, and taking fig. 3a as an example, when the test data are sorted to form a row of data, the first position information may be, for example, die _ x and die _ y shown in fig. 3a, or the row number thereof.
The second position information is predefined position information for each standard data in a single candidate mode, and for example, in fig. 3b, when the standard data are sorted to form a column of data, the second position information may be, for example, die _ x and die _ y shown in fig. 3b, or a row number thereof.
In step S13, the first position information of each of the N die is matched with the second position information of one standard data, that is, the test data and the N standard data of the N die may be selected from all the test data and all the standard data, and the test data and the N standard data of the N die may be in one-to-one correspondence.
Furthermore, if one of the first location information does not find the matched second location information, it indicates that there is test data at this location in the wafer to be matched, but there is no standard data at this location in the candidate pattern, at this time, the test data of the die at this location may not be included in the test data of the N die, that is, the test data does not participate in the pattern matching in step S12, for example, if 100 die test data are generated but only 98 standard data exist, the test data participating in the pattern matching in step S12 may be only 98 of those.
Similarly, if there is no first position information matching with the second position information, it indicates that the candidate pattern has the standard data of the position, but there is no test data of the position in the wafer to be matched, at this time, the standard data of the position may not be counted in the N standard data, that is, the standard data does not participate in the pattern matching in step S12, for example, if there are 98 die test data generated, but there are 100 standard data, the standard data participating in the pattern matching in step S12 may be only the 98 standard data.
In addition, in an example, the number of original test data may be different from the number of standard data, and in another example, if the original test data is partially removed, the number of test data may be different from the number of standard data only due to the removal, and the number of test data and the number of standard data are different regardless of the reason, and the test data and the standard data participating in the pattern matching in step S12 are determined in step S13, without departing from the description of the above embodiment.
Of course, if the number of original test data is the same as the number of standard data, step S13 may not be performed, or N may be determined to be the same as the number of original test data through step S13.
In a specific implementation process, the number of standard data of different candidate patterns and the distribution of position information thereof may be the same, and taking fig. 3b as an example, if different position information can be characterized as different row numbers, the row number of the standard data of different candidate patterns, and the die _ x and the die _ y corresponding to each row may be the same.
In a specific implementation process, referring to fig. 6, after step S13, the method may further include:
s14: whether N is determined to be less than a preset number threshold;
if the determination result of step S14 is yes, it indicates that: the data available for matching is not sufficient, and the wafer to be matched is not suitable for matching with the candidate pattern, and then step S15 may be implemented: determining that the wafer to be matched is not matched with each candidate mode;
if the determination result of step S14 is no, step S12 may be performed.
In one embodiment, the test data of the N bare chips may have been subjected to outlier rejection, and the outlier rejection may be performed before step S13, or may be performed before step S12.
Where the outliers may include maxima and/or minima. A maximum value is understood to mean that the value has been so large that it exceeds the limit that can be reached, and a minimum value is understood to mean that the value has been so small that it exceeds the limit that can be reached.
The maximum and minimum values may be determined, for example, according to other test data of the wafer to be matched, for example, when a certain test data exceeds a certain limit with respect to the nearby or all other test data, it may be understood that it is impossible to reach the test data based on the current test data, and the data may be regarded as the maximum value or the minimum value, i.e., an abnormal value.
In one example, the outlier can be eliminated by using the LOF algorithm, and the distance parameter k can be set to 5 when the LOF algorithm is implemented.
The LOF is specifically a localeotlierfactor, which may be understood as a local anomaly algorithm.
By eliminating the abnormal value, the influence of the abnormal value on the pattern matching in the step S102 can be avoided, so that the accuracy of the matching result is guaranteed.
In addition to the LOF algorithm listed above, in other alternative embodiments, the outliers may be removed in other manners, for example, the outliers may be removed by using a 3- σ criterion (also called a laida criterion), a COF algorithm (where the COF is specifically a Connectivity-based outpilermector), a LoOP algorithm (where the LoOP is specifically a localoulilerprobability), and the like.
In one embodiment, after step S12, the method may further include: the test data distribution diagrams shown in fig. 2b to fig. 2d are input and output to the outside, so that the user can actively check and check the matching result of step S12.
In summary, in the method for pattern matching of a wafer according to this embodiment, because a part of defects, problems, or other phenomena of the wafer may make test data of the wafer have a certain pattern, in this embodiment, under the condition that a candidate pattern and standard data thereof are preset, a target pattern matched with the wafer to be matched may be determined in M candidate patterns based on the test data of bare chips in the wafer, and further, the defects, problems, or other phenomena of the wafer may be conveniently determined through matching of the wafer patterns. Meanwhile, in the process, manual observation and statistical analysis are not needed, the workload is reduced, the processing efficiency is improved, and better pattern matching accuracy can be guaranteed.
FIG. 7 is a first block diagram illustrating a first process of a wafer pattern matching apparatus according to an embodiment of the present invention;
fig. 8 is a second schematic diagram of a process module of a wafer pattern matching apparatus according to an embodiment of the invention.
Referring to fig. 7 and 8, a wafer pattern matching apparatus 200 includes:
an obtaining module 201, configured to obtain test data of each bare chip in a plurality of bare chips of a wafer to be matched;
a matching module 202, configured to determine, according to the test data of the N bare chips and the N standard data of each candidate pattern of the M candidate patterns, a target pattern matched with the wafer to be matched in the M candidate patterns, where N is an integer greater than or equal to 2, and M is an integer greater than or equal to 1.
Optionally, the matching module 202 is specifically configured to:
calculating correlation information of the test data of the N bare chips and N standard data of each candidate mode in the M candidate modes; and/or: calculating similarity information between the test data of the N bare chips and N standard data of each candidate mode in the M candidate modes;
if only the correlation information is obtained by calculation, then: determining the target mode according to the correlation information;
if only the similarity information is obtained through calculation, the following steps are carried out: determining the target mode according to the similarity information;
if the correlation information and the similarity information are obtained through calculation, then: and determining the target mode according to the correlation information and the similarity information.
Optionally, the matching module 202 is specifically configured to:
and if the correlation information corresponding to any one current candidate mode in the candidate modes is greater than a preset correlation threshold value and the similarity information corresponding to the current candidate mode is also greater than a preset similarity threshold value, determining that the current candidate mode is the target mode.
Optionally, the similarity information is a Jaccard similarity.
Optionally, referring to fig. 8, the wafer pattern matching apparatus 200 further includes:
a determining module 203, configured to determine the N die in the plurality of die according to first location information and second location information of a single candidate pattern, where the first location information is used to characterize a location of a corresponding die in the wafer to be matched, the second location information is predefined location information for each standard data in the single candidate pattern, and the first location information of each die in the N die is matched with the second location information of one standard data.
Optionally, referring to fig. 8, the wafer pattern matching apparatus 200 further includes:
a mismatching module 204, configured to determine that the wafer to be matched is not matched with each candidate mode if N is determined to be smaller than a preset number threshold.
Optionally, the test data of the N bare chips is already eliminated with abnormal values, and the abnormal values include maximum values and/or minimum values.
In summary, in the mode matching apparatus for a wafer provided in this embodiment, because a part of defects, problems, or other phenomena of the wafer may make test data of the wafer have a certain mode, in this embodiment, under the condition that a candidate mode and standard data thereof are preset, a target mode matched with the wafer to be matched may be determined in M candidate modes based on the test data of bare chips in the wafer, and further, the defects, problems, or other phenomena of the wafer may be conveniently determined through matching of the wafer modes. Meanwhile, in the process, manual observation and statistical analysis are not needed, the workload is reduced, the processing efficiency is improved, and better pattern matching accuracy can be guaranteed.
Fig. 9 is a schematic structural diagram of an electronic device in an embodiment of the present invention.
Referring to fig. 9, an electronic device 30 is provided, which includes:
a processor 31; and the number of the first and second groups,
a memory 32 for storing executable instructions of the processor;
wherein the processor 31 is configured to perform the above-mentioned method via execution of the executable instructions.
The processor 31 is capable of communicating with the memory 32 via a bus 33.
The present embodiment also provides a computer-readable storage medium, on which a computer program is stored, characterized in that the program, when executed by a processor, implements the above-mentioned method.
Those of ordinary skill in the art will understand that: all or a portion of the steps of implementing the above-described method embodiments may be performed by hardware associated with program instructions. The program may be stored in a computer-readable storage medium. When executed, the program performs steps comprising the method embodiments described above; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A method for matching patterns of a wafer is characterized by comprising the following steps:
obtaining test data of each bare chip in a plurality of bare chips of a wafer to be matched;
and determining a target mode matched with the wafer to be matched in the M candidate modes according to the test data of the N bare chips and the N standard data of each of the M candidate modes, wherein N is an integer greater than or equal to 2, and M is an integer greater than or equal to 1.
2. The method of claim 1, wherein determining the target pattern matching the wafer to be matched among the M candidate patterns according to the test data of the N bare chips and the N standard data of each of the M candidate patterns comprises:
calculating correlation information of the test data of the N bare chips and N standard data of each candidate mode in the M candidate modes; and/or: calculating similarity information between the test data of the N bare chips and N standard data of each candidate mode in the M candidate modes;
if only the correlation information is obtained by calculation, then: determining the target mode according to the correlation information;
if only the similarity information is obtained through calculation, the following steps are carried out: determining the target mode according to the similarity information;
if the correlation information and the similarity information are obtained through calculation, then: and determining the target mode according to the correlation information and the similarity information.
3. The wafer pattern matching method of claim 2, wherein determining the target pattern according to the correlation information and the similarity information comprises:
and if the correlation information corresponding to any one current candidate mode in the candidate modes is greater than a preset correlation threshold value and the similarity information corresponding to the current candidate mode is also greater than a preset similarity threshold value, determining that the current candidate mode is the target mode.
4. The method of claim 2, wherein the similarity information is Jaccard similarity.
5. The method of any one of claims 1 to 4, wherein the step of matching the test data of the N bare chips with the N standard data of each of the M candidate patterns comprises:
determining the N bare chips in the plurality of bare chips according to first position information and second position information of a single candidate mode, wherein the first position information is used for representing the positions of the corresponding bare chips in the wafer to be matched, the second position information is predefined position information for each standard data in the single candidate mode, and the first position information of each bare chip in the N bare chips is matched with the second position information of one standard data.
6. The method of claim 5, wherein determining the N die of the plurality of die based on the first location information and the second location information for the single candidate pattern further comprises:
and if the N is determined to be smaller than the preset number threshold, determining that the wafer to be matched is not matched with each candidate mode.
7. The wafer pattern matching method of any one of claims 1 to 4, wherein the test data of the N bare chips are excluded with abnormal values, and the abnormal values include maximum values and/or minimum values.
8. A device for pattern matching of a wafer, comprising:
the device comprises an acquisition module, a matching module and a comparison module, wherein the acquisition module is used for acquiring the test data of each bare chip in a plurality of bare chips of a wafer to be matched;
and the matching module is used for determining a target mode matched with the wafer to be matched in the M candidate modes according to the test data of the N bare chips and the N standard data of each of the M candidate modes, wherein N is an integer greater than or equal to 2, and M is an integer greater than or equal to 1.
9. An electronic device, comprising a processor and a memory,
the memory is used for storing codes and related data;
the processor is configured to execute the codes in the memory to implement the wafer pattern matching method of any one of claims 1 to 7.
10. A storage medium having stored thereon a computer program which, when executed by a processor, implements the method of pattern matching for a wafer as claimed in any one of claims 1 to 7.
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