CN111357118A - Electron transfer gate circuit and methods of making, operating and using the same - Google Patents

Electron transfer gate circuit and methods of making, operating and using the same Download PDF

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CN111357118A
CN111357118A CN201880070919.4A CN201880070919A CN111357118A CN 111357118 A CN111357118 A CN 111357118A CN 201880070919 A CN201880070919 A CN 201880070919A CN 111357118 A CN111357118 A CN 111357118A
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鲁克·克里斯托弗·J
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Lu KeKelisituofuJ
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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/122Single quantum well structures
    • H01L29/127Quantum box structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66977Quantum effect devices, e.g. using quantum reflection, diffraction or interference effects, i.e. Bragg- or Aharonov-Bohm effects
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/20Organic diodes
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/04Architecture, e.g. interconnection topology
    • G06N3/045Combinations of networks
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065Analogue means
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0814Diodes only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes

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Abstract

The invention discloses a circuit comprising a first electrode, a second electrode and a plurality of quantum dot devices arranged between the first electrode and the second electrode. The second electrode is coupled to an impedance, and the impedance is selected to be a value that conducts current or prevents current from conducting when one or more quantum dot devices (e.g., quantum dot devices in adjacent circuits) form a coherent electronic conduction band.

Description

Electron transfer gate circuit and methods of making, operating and using the same
Technical Field
The present invention relates generally to the field of circuits, and more particularly to an electron transfer gating circuit that uses quantum coherence or other electron transfer mechanisms to drive a gate circuit.
Background
Quantum dot arrays (QDs) form electronic microstrips that provide electron transfer through the array. See U.S. patent 9287412B2, which is now incorporated by reference for any purpose as if fully set forth herein. These quantum dots can be dispersed in bulk conjugated polymers, resulting in nanocomposites with improved properties. See U.S. patent 9349888B2, which is now incorporated by reference for any purpose as if fully set forth herein. However, the use of such electron transport mechanisms in device integration is not clear.
Conjugated polymeric nanoparticles are currently known for Quantum Dot (QD) applications. See U.S. patent 2016/0161475Al, which is now incorporated by reference into this disclosure for any purpose, as if fully set forth herein. However, the formation of arrays of conjugated polymeric nanoparticles with inorganic Quantum Dots (QDs) is not known.
Disclosure of Invention
The invention discloses a circuit comprising a first electrode, a second electrode and a plurality of quantum dot devices arranged between the first electrode and the second electrode. The second electrode is coupled to an impedance, and the impedance is selected to be a value that conducts current or prevents current from conducting when one or more quantum dot devices (e.g., quantum dot devices in adjacent circuits) form a coherent electronic conduction band.
Other systems, methods, features and advantages of the invention will be, or will become, apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features and advantages be included within this description, be within the scope of the invention, and be protected by the accompanying claims.
Drawings
Various aspects of the invention may be better understood with reference to the following drawings. The components in the figures may be scaled, but emphasis is placed upon clearly illustrating the principles of the present invention. And in which like reference numerals represent corresponding elements throughout the several views, and in which:
FIG. 1 is a schematic diagram of a circuit for converting with electronic transfer in accordance with an exemplary embodiment of the present invention;
fig. 2 is a schematic diagram of a configuration of a plurality of quantum dots according to an example embodiment of the invention;
FIG. 3 is a schematic diagram of an Electron Transfer (ET) gate circuit with an associated impedance network in accordance with an exemplary embodiment of the present invention;
FIG. 4 is a schematic diagram of a coupled electron transfer device system according to an example embodiment of the present invention;
FIG. 5 is a schematic diagram of a system for coupling electron transfer devices with neural network control in accordance with an exemplary embodiment of the present invention;
FIG. 6 is a schematic diagram of a node output register with voltage and impedance control according to an example embodiment of the invention.
Detailed Description
In the following description, like parts are marked throughout the specification and drawings with the same reference numerals. The figures are to scale and certain parts are shown in generalized or schematic form and labeled with trade names for the sake of clarity and conciseness.
The present application claims the benefit of the following patent applications: 1) us provisional patent application 62/578,483 filed 2017, 10, 30, 2) us provisional patent application 62/581,766 filed 2017, 11, 6, 3) us provisional patent application 62/584,898 filed 2017, 11, 4) us provisional patent application 62/590,632 filed 2017, 11, 26, 5) us provisional patent application 62/614,412 filed 2018, 1, 6, and 6) us provisional patent application 62/641,382 filed 2018, 3, 11, which are now incorporated by reference for all purposes as if fully set forth herein.
Fig. 1 is a schematic diagram of a circuit 100 for converting with electron transfer according to an example embodiment of the invention. The circuit 100 includes electron transport devices 102 and 104, both of which are made of Quantum Dots (QDs) and other elements, as discussed further herein. The device designs may be similar and are further described herein as electron transfer devices 102/104, with the relevant elements of each device being described in a similar manner. The Quantum Dots (QDs) are selected from suitable materials whose size and spacing can produce electron transport mechanisms such as electron microstrip, electron hopping, coherent tunneling, and other suitable electron transport mechanisms as described above. For example, the Quantum Dots (QDs) may include a single or multiple layers of inorganic Quantum Dots (QDs), a bottom layer of inorganic Quantum Dots (QDs), and a top layer of organic Quantum Dots (QDs) (also referred to herein as Conjugated Polymer Nanoparticles (CPNPs), but are not limited to, conjugated polymer materials), one or multiple layers of hybrid inorganic Quantum Dots (QDs), one or multiple layers of hybrid organic Quantum Dots (QDs), one or multiple layers of hybrid inorganic and organic Quantum Dots (QDs), alternating organic Quantum Dots (QDs) and inorganic quantum dot layers (QDs), other suitable configurations of organic Quantum Dots (QDs), inorganic Quantum Dots (QDs), mixtures of inorganic Quantum Dots (QDs) and organic and inorganic Quantum Dots (QDs), combinations of Quantum Dots (QDs) and different materials or structures, or other suitable materials or structures that produce electron transfer between electron transfer devices. The spacing 134 between the Quantum Dots (QDs) may be air, a conjugated polymer, a ligand, a combination of three or other materials, or other suitable materials.
The electron transfer device 102/104 includes a lead 106/122 to the anode 108/124 and a lead 112/130 to the cathode 110/126. Quantum Dots (QDs) or Conjugated Polymer Nanoparticles (CPNPs) are disposed between the anode 108/124 and the cathode 110/126. Impedance 116/132 is connected in series with wire 112/130, and piezoelectric device 114/128 may be configured to apply force vectors to the Quantum Dots (QDs) and/or Conjugated Polymer Nanoparticles (CPNPs) of electron transfer device 102/104 to facilitate localization of electronic or other quantum mechanical effects.
Conductive line 106/122, anode 108/124, conductive line 112/130, and cathode 110/126 can be formed by vapor deposition techniques, single crystal wafer techniques, micro-forming, etching, or other suitable processes using gold, aluminum, semiconductor materials, conductive oxides, or other suitable materials to form an electron transfer device having linear conductivity, schottky conductivity, diode conductivity, or other suitable conductivity. In one exemplary embodiment, the inner surfaces of the anode 108 and cathode 110 may be coated with a patterned polymer or organic material that is also used to form Quantum Dots (QDs) of the Conjugated Polymer Nanoparticles (CPNPs) nature, such as poly-P-phenylene vinylene (PPEs), poly-P-phenylene vinylene (PPVs), trioctyl phosphine oxide (TOPO), poly (3-hexylthiophene) (P3HT), polyaniline, polypyrrole, a material that attracts ligands such as oleic acid, or other materials used to passivate the surface of the Quantum Dots (QDs), or other suitable materials, the pattern of which may be set as desired to attract different types of Quantum Dots (QDs) or conjugated polymer nanoparticles. Suitable masks may be used to coat selected portions of the interior surfaces of anode 108/124 and cathode 110/126 with suitable inorganic, polymeric, or organic materials to facilitate alignment of Quantum Dots (QDs) and Conjugated Polymeric Nanoparticles (CPNPs) (quantum dots (QDs) and conjugated polymeric nanoparticles formed by electron microstrip or other electron transport mechanisms, as described herein).
Impedance 116/132 may be a fixed or variable impedance for controlling current flow from electron transfer device 102/104. The value of the impedance 116/132 may be resistive, inductive, capacitive, may be a suitable combination of series and/or parallel resistive, inductive, and capacitive elements, variable impedance, controllable variable impedance, or other suitable impedance type.
The piezoelectric device 114/128 may generate force vectors that subject the Quantum Dots (QDs) and/or the Conjugated Polymer Nanoparticles (CPNPs) of the electron transport device 102/104 to mechanical forces, such as stress, acceleration, compressive forces, or other suitable forces, respectively. The piezoelectric device 114/128 may be positioned and oriented so as to apply or apply a force vector in a predetermined direction to the electric field vector generated by the electric field components of the anode 108/124 and cathode 110/126, respectively, such as an orthogonal vector direction or other suitable vector combination between the force and the electric field vector.
Insulators 118 and 120 mechanically connect electron transfer device 102 and electron transfer device 104 and contain additional Quantum Dots (QDs) and/or Conjugated Polymer Nanoparticles (CPNPs). Insulators 118 and 120 and their associated Quantum Dots (QDs) and/or Conjugated Polymer Nanoparticles (CPNPs) may be omitted, for example, when sufficient coupling exists between one or more external electron transfer devices and electron transfer devices 102 and 104, when the external electron transfer devices are used as probes or sensors to connect with electron transfer devices 102 and 104 and measure signals generated by the electron transfer mechanisms of electron transfer devices 102 and 104. In another exemplary embodiment, the external electron transfer device may be used to link in vivo an array of Quantum Dots (QDs) disposed within one or more cells, including but not limited to naturally occurring Quantum Dots (QDs) such as ferritin and melanin, and synthetic semiconductor Quantum Dots (QDs), to modify the characteristics of the electron transfer mechanism, to measure the time-varying electron transfer signal generated by the array, or to achieve other suitable purposes. In this example embodiment, measuring the signal produced by the electron transfer mechanism may include impedance matching the effective impedance of the electron transfer mechanism, using a selected impedance to prevent interference with the electron transfer mechanism, or other suitable circuit configuration to optimize the measurement. In another example embodiment, the external electron transfer device may be arranged to manipulate the electron transfer mechanism of the appropriate electron transfer device in a predetermined manner, to change the electron transfer mechanism, to increase or decrease a local effect, to increase or decrease a global effect, or to achieve other suitable objectives. The placement and electrical parameters of the external electron transfer devices relative to electron transfer devices 102 and 104 or other suitable electron transfer devices can be determined by solving the systems kronecker panner's equation and schrodinger poisson's equation.
In operation, the Quantum Dots (QDs) and Conjugated Polymer Nanoparticles (CPNPs) of the circuit 100 generate an electron transport mechanism by generating excitons and conduct current depending on the design of the electron transport devices 102 and 104. In a first example embodiment, the electron transfer devices 102 and 104 may apply electric fields and forces that, in turn, may cause the formation of excitons in the Quantum Dots (QDs) where the excitons form electron microstrips, electron hopping, coherent tunneling, and other suitable electron transfer mechanisms. In the present example, where an electronic microstrip is formed between the Quantum Dots (QDs) of the electron transfer devices 102 and 104, electrons may be localized to one of the electron transfer devices 102 or 104 by controlling the applied electric field, the applied force, the values of the impedances 116 and 132, or other suitable circuit parameters of the circuit 100. In this example, electrons may be localized in the electron transfer device 102 or 104 where the associated impedance 116 or 132 is lowest, respectively, and may remain delocalized if the impedances 116 and 132 are equal and the applied electric field or electric field and/or force vector is insufficient to accomplish localization. The specific voltage levels and forces can be determined by iteratively solving the system kronecker-panner and schrodinger-poisson equations (as listed in U.S. patent 6,829,269, U.S. patent 7,026,641, and U.S. patent 6,627,809, which are now incorporated by reference for any purpose as if fully set forth herein), or by determining circuit parameters related to the circuit based on the physical design of the circuit, material properties, voltage levels, and other parameters (as listed in U.S. patent 5,608,231, U.S. patent 6,489,041, and U.S. patent application publication 2007/0162263a1, which are now incorporated by reference for any purpose as if fully set forth herein).
By selecting appropriate circuit parameters, electron transfer between the electron transfer devices 102 and 104 (or additional devices (as desired)) can be accomplished by either conducting electrons through one of the electron transfer devices 102 and 104 (in the case of a linear arrangement) or turning on one of the electron transfer devices 102 and 104 (in the case of a non-linear diode/schottky arrangement), respectively, as a function of the applied voltage value, force vector, and the values of the impedances 116 and 132 of the electron transfer devices 102 and 104. For example, when the impedances are balanced and the excitation fields, force vectors, and other design parameters of the electron transfer devices 102 and 104 are equal, the electron microstrip will not localize and other electron transfer mechanisms will not transfer more electrons to either device, resulting in low magnitude balanced currents (for linear operation) or balanced non-linear operation. When the output impedance of one device is lower than the output impedance of the other device (assuming the force and electric field vectors are balanced), the electron transport mechanism will still conduct electrons to the device, resulting in loss of electrons by the other device, increased current through the device with the lowest impedance (in linear operation) or additional increase of charge carriers that can turn the device on (in non-linear operation). After the transferred charge carriers are conducted out of the lowest impedance device, electron transfer between the devices can be reestablished until another discharge cycle occurs.
The excitation vectors of the electron transfer devices 102 and 104 can be varied by varying the value of V + applied to the anodes 108 and 124, rather than varying the impedances 116 and 132, where anodes with higher applied electric fields can result in electron localization of the electron microstrips. Likewise, force vectors or other variables may also be modified. The circuit 100 may be extended from two electron transfer devices 102 and 104 to a large number of electron transfer devices as long as the electron transfer parameters produce suitable electron transfer characteristics to support electron transfer switching.
In another exemplary embodiment, the materials of the anodes 108 and 124 and cathodes 110 and 126 may be selected to produce a schottky diode using indium tin oxide and aluminum, gold and aluminum, or other suitable combinations disclosed in U.S. patent 8,574,685B1 (for any purpose incorporated herein by reference as if fully set forth herein). By biasing the device at a value at which the rectified current through the device is slightly below its initial increase, electron transfer between the devices allows electrons of the electron transfer mechanism to be transferred to the device with the lowest output impedance, which increases the number of charge carriers and the corresponding current of the device, allowing it to move further into the conduction region and conduct a current exponentially greater than that of the other devices. Localizing electrons from the electronic microstrip or using other electron transfer mechanisms, such as controlling the values of impedances 116 and 132, can control transfer because electrons will be localized in the electron transfer device 102 or 104 with the lowest ground path impedance. Localization of electrons in one of the electron transfer devices 102 or 104 pushes the device into a conducting mode, thereby increasing the current associated with localization that might otherwise be of lower magnitude and more difficult to detect. In this manner, the schottky diode structure can be used to both amplify current and increase the sensitivity of the electron transfer devices 102 and 104. Thus, to reduce sensitivity, the bias levels of the electron transfer devices 102 and 104 may be reduced uniformly or separately, as appropriate. Likewise, a transistor structure may be used in appropriate circumstances, for example by providing control terms and control voltages at intermediate positions between the anode and the cathode or in other appropriate ways.
In addition, the applied voltage level may be selected to create an electronic microstrip using a material that creates excitons at the applied voltage level. The particular voltage levels required to produce the electronic microstrip can be determined by solving the schrodinger equation for the klenesch-penney potential as a function of the material properties and spacing between the selected quantum dots and the associated material (e.g., the conjugated polymer matrix of the electron transfer devices 102 and 104). Other examples of similar materials and structures are disclosed in U.S. patent application publication 2007/0162263a1, except that the semiconductor material selected for the quantum dots of the present invention may advantageously include an indirect bandgap, rather than a direct bandgap, to prevent the generation of photons and the corresponding loss of energy.
In addition to or instead of calculating the voltage at which electron transfer occurs, a controllable bias source such as that shown in FIG. 4 as a microstrip controller 402 or 404 may be used to empirically determine the excitation level associated with electron transfer. Such voltage level control may be used to adjust for pitch and material property variations of the quantum dots and elements of the electron transfer device 102/104.
Fig. 2 is a schematic diagram of a multiple quantum dot/conjugated polymer nanoparticle (QD/CPNP) configuration 200 according to an example embodiment of the invention. Quantum dot configurations 202-218 include different Quantum Dot (QDs) combinations formed from different materials, such as neural melanin or other polymers, ferritin or other proteins, semiconductors (silicon, germanium, cadmium sulfide, cadmium selenide, indium, diamond, pyrite, boron nitride, gallium arsenide, aluminum gallium arsenide, copper (I) oxide, amorphous silicon, graphene, zinc oxide, silicon carbide, gallium arsenide, copper (II) chloride, gallium nitride, copper indium gallium selenide, copper (II) oxide, black silicon, uranium dioxide, mercury telluride, molybdenum disulfide, iron (II, III) oxide, tin dioxide, cadmium oxide, lead (II) sulfide, gallium selenide (II), indium (III) oxide, antimony, aluminum nitride, zinc sulfide, zinc telluride, aluminum phosphide, bismuth telluride, mercury selenide, zinc selenide, indium nitride, silicon germanium, lead telluride, indium phosphide, indium gallium nitride, indium nitride, zinc selenide, indium phosphide, zinc selenide, silicon germanium, lead telluride, indium phosphide, zinc telluride, zinc nitride, zinc selenide, gallium phosphide, indium arsenide, lead (ii) iodide, indium gallium arsenide, indium sulfide (iii), boron arsenide, lead selenide, mercury (ii) iodide, molybdenum disilicide, aluminum antimonide, tungsten disilicide, boron phosphide, indium gallium phosphide, cadmium zinc telluride, aluminum arsenide, tin telluride, silver telluride, indium gallium phosphide, cadmium arsenide, gallium antimonide, antimony indium gallium arsenide phosphide, indium aluminum arsenide, float zone silicon, platinum silicide, aluminum gallium nitride, gallium arsenide phosphide, beryllium telluride, mercury zinc telluride, iron phosphide, aluminum gallium phosphide, indium tin oxide, or other suitable inorganic materials (all porous, polycrystalline, single crystal, nanocrystalline, or other suitable forms of inorganic materials). In addition, organic materials such as Conjugated Polymer Nanoparticles (CPNPs), poly-P-phenylene vinylene (PPE), poly-P-phenylene vinylene (PPV), tri-n-octylphosphine oxide (TOPO), poly-3-hexylthiophene (P3HT), or other suitable materials may also be used to form the organic quantum dots (QOD) shown in fig. 2, including materials for the ligand passivation layer or other suitable additional materials. While these are commonly shown as Inorganic Quantum Dots (IQDs) and Organic Quantum Dots (OQDs) in the Quantum Dot (QD) configuration 200, certain multilayer Quantum Dots (QDs), such as ferritin or ligand passivated Quantum Dots (QDs), may be classified as either Inorganic Quantum Dots (IQDs) or Organic Quantum Dots (OQDs) depending on the other organic and inorganic quantum dots used. Two or more different Inorganic Quantum Dots (IQDs) or Organic Quantum Dots (OQDs) may also or alternatively be used. To facilitate the generation of electron transfer, Inorganic Quantum Dots (IQDs) and/or Organic Quantum Dots (OQDs) may have an indirect bandgap to prevent energy from being converted into photons, rather than generating electron transfer and conduction.
Configuration 202 and 218 shown in fig. 2 are examples, and other suitable quantum dot arrangements and configurations or other exciton confinement structures may be used or selected for use in effecting electron transfer conversion. For example, each of the quantum dots illustrated for electron transfer devices 102 and 104 may be replaced with quantum dots having configurations 202 and 218 such that the number of quantum dots disposed between anode 108/124 and cathode 110/126 may be different from the illustrated example embodiment. In addition, other materials, such as solid or amorphous conjugated polymers, may be used to fill the spaces between Inorganic Quantum Dots (IQDs), Organic Quantum Dots (OQDs), and combinations of Inorganic Quantum Dots (IQDs), or other suitable materials.
Fig. 3 is a schematic diagram of an Electron Transfer (ET) gate circuit 300 with an associated impedance network, according to an example embodiment of the invention. The Electron Transfer (ET) gate circuit 300 includes an Electron Transfer (ET) device 302, two main gating resistors R1 and R2, which are gated by T1 and T2 and drive the gates of T3 and T4. In series with R2 is T5-T16, which gates R3-R8 and is driven by R3-R8 (e.g., R3 is gated by T10 and drives the gate of T11, R4 is gated by T9 and drives the gate of T9, and so on). The circuit, used with the Electron Transfer (ET) devices and associated output impedances in an array of Electron Transfer (ET) devices forming an Electron Transfer (ET) gate, can be used both to select the Electron Transfer (ET) device to be driven based on the lowest impedance, and to generate additional indicators or drive additional circuitry (and also to omit or select the omission of transistors T3, T4, T11-T16 and associated circuitry that may use the indicators/controls) by applying gate voltages to transistors T3, T4, T11-T16, as appropriate. Additional resistive layers may also be provided or selected to provide switching, for example to increase the selectivity of an Electron Transfer (ET) gate relative to other gates. For example, if there are N Electron Transfer (ET) gates, where N is an integer, then there may be N different resistance levels, so that different resistance levels may be assigned to each Electron Transfer (ET) gate where appropriate. Similar circuits of the same or other suitable combinations of impedances, drive gates and drivers may also be used or selected for use. For example, while resistors are shown for simplicity, other suitable linear, nonlinear, passive, or active impedance combinations may be used or alternatively used.
In an example embodiment, a suitable controller may control the gate voltages applied to T1, T2, and T5-T10 to adjust the impedance of the Electron Transfer (ET) device 302 as a function of external variables, using similar configurations among a large number of electron transfer devices connected by an electron transfer mechanism, and the like. In this example embodiment, the operational Electron Transfer (ET) devices are determined by a number of independent operations or parallel processes with complex non-linear relationships, such as feedback controllers, neural networks, or other suitable control arrangements. The neural network output may include a plurality of digital registers for selecting which of the transistors T1, T2, and T5-T10 (or other suitable transistors coupled to the Electron Transfer (ET) device) drives one or more external circuits or devices that generate signals, where such signals are used as inputs to the neural network, in the case where the drive of one of the Electron Transfer (ET) devices is used as a neural network feedback signal, or other suitable configurations may also be used or selected for use.
FIG. 4 is a schematic diagram of a coupled electron transfer device system 400, according to an example embodiment of the invention. The system 400 includes electronic transfer switches 406 and 408, which are connected in series by conductors as shown. Alternatively, electronic transfer switches 406 and 408 may be coupled by one or more capacitive connectors, one or more inductive connectors, or a suitable combination of capacitive, inductive, and/or resistive connectors, or in other suitable manners. Likewise, additional electron transfer devices, electron transfer switches, or other suitable electron transfer structures may be coupled to one or both of electron transfer switches 406 and 408 in such a manner that the coupling modifies the input of one or more electron transfer devices, one or more impedances, or a combination of electron transfer device inputs and associated impedances to affect the operation of electron transfer switches 406 and/or 408.
The electron transfer switch 406 includes electron transfer devices ET11-ET1N that are similarly configured to the electron transfer devices 102 or 104 or other suitable devices, are separated from each other by a barrier layer B, and have respective variable or fixed impedances S11-S1N. The barrier layer B may be a quantum dot array, insulator, other quantum device, or other suitable non-metallic structure that functionally separates the electron transfer devices ET11-ET1N from one another. The electron transfer switch 408 includes electron transfer devices ET21-ET2N that are similarly configured to the electron transfer devices 102 or 104 or other suitable devices, are separated from each other by a barrier layer B, and have respective variable or fixed impedances S21-S2N. The barrier layer B may be a quantum dot array, insulator, other quantum device, or other suitable non-metallic structure that functionally separates the electron transfer devices ET21-ET2N from one another. Microstrip controllers 402 and 404 are used to control the voltage applied to electronic transfer switches 406 and 408, respectively, to control the formation of electronic microstrips or other electronic transfer mechanisms.
In operation, the states of the electron transfer devices ET11-ET1N, ET21-ET2N, impedances S11-S1N, and impedances S21-S2N determine whether electron microstrips are formed in the electron transfer switches 406 and 408 and whether a conductive path is formed in the electron microstrips through which electrons pass. Since the electrons are positioned on the respective electron transfer device that provides the lowest impedance path, the electronic state in the electron transfer switches 406 and 408 varies with the input, output and associated impedance of the electron transfer device. The simulation system may be modeled by selecting the number and arrangement of electron transfer devices ET11-ET1N, ET21-ET2N, and values of impedances S11-S1N and impedances S21-S2N to find optimal routes, solve quantum algorithms, or for other suitable purposes.
The microstrip controllers 402 and 404 may be implemented in hardware or a suitable combination of hardware and software and are used to control the bias voltages applied to the electronic transfer switches 406 and 408, respectively. As previously described, the sensitivity of the electron transfer switches 406 and 408 may be increased or decreased by adjusting the applied bias voltage. The microstrip controllers 402 and 404 may modify the bias voltages of all electron transfer devices ET11-ET1N and ET21-ET2N, and the bias voltages of the individual electron transfer devices ET11-ET1N and ET21-ET2N, or may perform other suitable functions.
In one exemplary embodiment, the bias voltages of selected electron transfer devices ET11-ET1N and ET21-ET2N may be increased to increase the sensitivity of the electron transfer devices, while the bias voltages of other electron transfer devices ET11-ET1N and ET21-ET2N may be decreased to decrease the sensitivity thereof. In this way, when the voltage input to the other electron transfer device having a higher bias voltage is insufficient to drive the device, the device is still driven because the voltage input to the electron transfer device having a lower bias voltage is higher. The bias voltage may be adjusted according to the settings of the external system to prevent the safety system from operating in low level transient conditions while still allowing the safety system to operate in the event of receiving a signal having a value greater than a predetermined threshold of the electronic pass device.
FIG. 5 shows a diagram of a coupled electron transfer device system 500 with neural network control, according to an example embodiment of the present invention. The system 500 includes a neural network 502 coupled to the electronic transfer switch 406 and an electronic transfer switch 408 serially coupled to the electronic transfer switch 406 through the neural network 504. Electronic transfer switches 406 and 408 may also be coupled or otherwise suitably coupled by one or more capacitive connectors, one or more inductive connectors, and suitable combinations of capacitive, inductive, and/or resistive connectors. The neural networks 502 and 504 may be constructed in accordance with the disclosure of U.S. patent 9,129,221 (shown incorporated by reference for any purpose as if fully set forth herein) or other suitable neural network structures that can receive a plurality of different inputs (e.g., bee-value forming, analog and digital inputs) and produce one or more outputs. The neural networks 502 and 504 include a plurality of nodes N1-N1N, N2-N2N, and Nn-Nnn (shown explicitly at 502) arranged in the network, each of which may contain data storage, for example, in various stages of the node, may be used to perform related functions, and may store state data. Also, the nodes may have other suitable functions. The nodes may be implemented in hardware (with dedicated circuitry for associated memory, data storage, state and processing functions) using a neural network parallel processor running under programmable control of one or more algorithms or otherwise suitably operated.
The neural network 502 receives the input 506 and controls the input to the electron transfer device ET11-ET1N, wherein the electron transfer device is configured similar to the electron transfer device 102 or 104 or other suitable device, separated by a barrier layer B, and has a corresponding variable or fixed impedance S11-S1N. The neural network 502 may also be coupled to one or more variable or fixed impedances S11-S1N, and the values of the one or more variable impedances may be adjusted. The barrier layer B may be an array of quantum dots, insulators, other quantum devices, or other suitable non-metallic structures that functionally separate the electron transfer devices ET11-ET1N from one another. The neural network 502 also receives one or more feedback signals from the output of the electronic transfer switches 406 and/or 408. In an example embodiment, the feedback signal may be provided from a predetermined node of one neural network to other nodes of the same neural network, may be provided from a predetermined node of one neural network to a node of another neural network, may be provided from an output node of one neural network to a node of the same or different neural network, may be provided from an output of the electronic transfer switch 406 and/or 408 to a node of the same or different neural network, or may be provided in other suitable manners.
The neural network 504 receives inputs 508 and inputs of the electron transfer switch 402 and controls inputs to the electron transfer switch 408, and includes electron transfer devices ET21-ET2N, wherein the electron transfer devices are configured similar to the electron transfer devices 102 or 104 or other suitable devices, are separated from each other by a barrier B, and have respective variable or fixed impedances S21-S2N. The neural network 502 is coupled to one or more variable or fixed impedances S21-S2N, and may adjust the values of the one or more variable impedances. The barrier layer B may be an array of quantum dots, insulators, other quantum devices, or other suitable non-metallic structures that functionally separate the electron transfer devices ET21-ET2N from one another.
The microstrip controllers 402 and 404 are used to control the voltage applied to the electronic transfer switches 406 and 408 through neural networks 502 and 504, respectively. In one example embodiment, the output nodes of the neural networks 502 and 504 may include a multi-bit output that determines whether the voltage of the microstrip controllers 402 and 404 is applied to the output (i.e., a digital 1 or 0) of a particular electron transfer device (ET11-ET1N or ET21-ET2N) and determines the voltage level to be applied, or provides other suitable functionality to control the formation of an electronic microstrip or other electron transfer mechanism. The neural network 504 also receives one or more feedback signals output by the electronic transfer switch 404 and may work in conjunction with the neural network 502 to control the input of one or more variable impedance and electronic transfer devices.
In operation, the states of neural networks 502 and 504, electron transfer devices ET11-ET1N, electron transfer devices ET21-ET2N, impedances S11-S1N, and impedances S21-S2N determine whether electron microstrips are formed in electron transfer switches 406 and 408 and whether a conductive path is formed in the electron microstrips through which electrons pass. Since the electrons are positioned on the respective electron transfer device that provides the lowest impedance path, the electronic state in the electron transfer switches 406 and 408 varies with the input, output and associated impedance of the electron transfer device.
The simulation system may be modeled by selecting training of the neural networks 502 and 504, the number and arrangement of the electron transfer devices ET11-ET1N and ET21-ET2N, and values of impedances S11-S1N and impedances S21 to S2N to find optimal routes, solve quantum algorithms, or achieve other suitable objectives. The neural networks 502 and 504 may be used to control the voltages applied to the electron transfer devices ET11-ET1N and ET21-ET2N, as well as the values of the impedances S11-S1N and S21-S2N, for example by providing additional input conversion devices to the elements controlled by the neural networks 502 and 504.
Additionally, one or more outputs of the switches S11-S1N, S21-S2N may be used to control external systems or devices, for example, where inputs to the neural networks 502 and 504 may include optical inputs and outputs, or outputs for controlling the motion of the robotic system by controlling motors, where inputs include process variable measurements, and outputs for controlling the operation of process-related devices or other suitable devices. In this example embodiment, the system 500 may be used to select a single best output from a plurality of different options, where each option has an associated impedance and the output with the lowest impedance is the best output. Thus, the system 500 effectively enables multiple parallel paths to be modeled using the neural networks 502 and 504, where the neural network 504 may provide state continuity or state storage functionality with respect to the output of the neural network 504. Likewise, additional neural networks and electronic transfer switches may also be provided or alternatively provided in series-parallel with the elements of system 500 to enable additional state control in more complex systems.
For example, U.S. patent 6,324,532 discloses a pyramid of neural networks with a "coarse-to-fine" processing structure, which is incorporated by reference for any purpose, as if fully set forth herein. The present invention may be used in conjunction with the feedback mechanisms disclosed in us 6,324,532 and us 9,129,221 for detecting objects in image data and selecting motion in response to the detected objects, wherein feedback may be generated indicating whether the correct object was selected. In this example embodiment, the neural network 502 may be used to generate motion controls to select an object, and the neural network 504 may be used to determine whether the object selected according to the input criteria is the correct object. The nodes 1002, 1012, 1070, 1074, and the nodes of figure 10, figure 10A, and other figures in us patent 9,129,221, etc. may act as nodes in the neural networks 502 and 504 and may be coupled between the neural networks 502 and 504 to provide a feedback connection. Likewise, feedback connections between the neural network nodes of fig. 10, 11 and 12 in U.S. patent 6,324,532 may couple feedback to other neural networks, as shown by neural networks 502 and 504 in fig. 5, or may also implement or select to implement other suitable functions.
In an example embodiment, the inputs 506 and 508 may represent different sensory data inputs, status data inputs, motor control data inputs, and other suitable inputs to effectively form a plurality of sensing circuits, status circuits, motor control circuits, and other suitable circuits in conjunction with the individual nodes of the neural networks 502 and 504. Further, the inputs 506 and 508 may include common inputs to the neural networks 502 and 504, outputs of other neural networks, or other suitable inputs. In another example embodiment, the mapped image data may be provided as one or more inputs 506 and 508, and may also be provided as one or more inputs to electron transfer devices ET11-ET1N and ET21-ET2N to train neural networks 502 and 504 to recognize image data of objects, where the inputs from the mapped image data to electron transfer devices ET11-ET1N and ET21-ET2N enhance the relevant outputs of neural networks 502 and 504 (associated with the identification and logical import of relevant objects of the peripheral image data signals). For example, if image data having surfaces of cubes, spheres, and pyramids is received and the system needs to generate control signals to obtain one of the objects, the neural networks 502 and 504 may process the mapped image data signals to generate outputs associated with the cubes, spheres, and pyramids, and in conjunction with additional inputs identifying the object to be obtained, the associated mapping profile may be used to activate electron transfer devices ET11-ET1N and ET21-ET2N to generate an electron transfer mechanism and drive one of electron transfer devices ET11-ET1N and ET21-ET2N associated with motor control to obtain the corresponding object. In this regard, the electron transfer devices ET11-ET1N and ET21-ET2N may associate the mapped image data inputs with neural network outputs that identify the object as a cube, sphere, or pyramid, the neural network outputs being used to drive the controller to obtain the cube, sphere, or pyramid and the electron transfer devices ET11-ET1N, the electron transfer devices ET21-ET2N, other suitable inputs of the neural networks 502 and 504, and the outputs of the neural networks 502 and 504. In this regard, when a single input is shown to occur from the neural networks 502 and 504 to the electron transfer devices ET11-ET1N and the electron transfer devices ET21-ET2N, the node output register may be used to generate a plurality of different inputs from the neural networks 502 and 504 output nodes to the electron transfer devices ET11-ET1N and the electron transfer devices ET21-ET 2N.
Fig. 6 is a diagram 600 of a node output register 604 with voltage and impedance control according to an example embodiment of the invention. The nodes 602 of the neural network are coupled to a node output register 604 and provide a 7-bit value or other suitable number of bits to the node output register 604. As shown in this exemplary embodiment, two bits are provided for the voltage controller 606 and five bits are provided for the impedance controller 608, where transistors, logic gates, or other devices may be suitably arranged to generate control signals for controlling the voltage applied to the electronic pass device and the impedance at the output of the electronic pass device to provide an output that may be compared to a desired value (e.g., training), to provide a control output for controlling external devices, to provide an input for electronic pass switches, and to provide an input for other suitable purposes.
As used herein, "hardware" may include a combination of discrete components, an integrated circuit, an application specific integrated circuit, a field programmable gate array, or other suitable hardware. As used herein, "software" may include one or more objects, agents, threads, lines of code, subroutines, standalone software applications, two or more lines of code or other suitable software structures running in two or more software applications, on one or more processors (where a processor includes one or more microcomputers or other suitable data processing units, memory devices, input-output devices, display screens, data input devices (e.g., keyboard or mouse), peripheral devices (e.g., printer and speakers), associated drivers, control cards, power supplies, network devices, expansion devices, or other suitable devices running under the control of a software system with a processor or other device), or other suitable software structures. In an example embodiment, the software may include one or more lines of code or other suitable software structures running in a general-purpose software application, such as an operating system, and one or more lines of code or other suitable software structures running in a special-purpose software program. As used herein, the term "coupled" and its cognate terms (e.g., "couples" and "coupled") may include physical connections (e.g., copper conductors), virtual connections (e.g., through randomly allocated memory locations of a data storage device), logical connections (e.g., through logic gates of a semiconductor device), other suitable connections, or other suitable combinations of such connections. The term "data" may refer to suitable structures for using, transmitting, or storing data, such as data fields, data buffers, control messages having data values and sender/receiver address data, control messages having data values, and one or more operators that cause a receiving system or element to perform the function of using the data, or other suitable hardware or software components for electronically processing the data.
All documents cited herein are, unless otherwise specified, for fulfillment purposes only and are incorporated by reference as if fully set forth herein, except where cited for fulfillment purposes. The analysis set forth herein is not intended to explain complex neural processes occurring in a biological organism, but rather involves potentially useful mechanisms that can be used to help model those complex neural processes and make neuroprosthetic devices or other neural interfaces available to interact with those complex neural processes. Likewise, electronic microstrip formation, entanglement, coherence, tunneling, etc. isobaric mechanical effects are based on potential mechanisms that may exist in SN and LC neurons, but the present invention is intended to encompass such effects insofar as different quantum mechanical effects are responsible for transferring energy between QS gates using the same structures and materials disclosed.
It should be emphasized that the above-described embodiments are merely examples of possible implementations. Many variations and modifications may be made to the above-described embodiments of the invention without departing from the principles thereof. All such modifications and variations are intended to be included herein within the scope of this disclosure and protected by the following claims.

Claims (49)

1. A circuit, comprising: a first electrode, a second electrode, a plurality of quantum dot devices disposed between the first electrode and the second electrode; and the second electrode is coupled to an impedance that is selectable to a value that conducts current or prevents conduction of current when the one or more quantum dot devices and the one or more external quantum device form a coherent electronic conduction band.
2. The circuit of claim 1, wherein the plurality of quantum electrical devices further comprises a plurality of ferritin molecules.
3. The circuit of claim 1, wherein the plurality of quantum electrical devices further comprises a plurality of neural melanin molecules.
4. The circuit of claim 1, wherein the plurality of quantum electrical devices further comprises a plurality of ferritin molecules and neural melanin molecules.
5. The circuit of claim 1, wherein the plurality of quantum electrical devices further comprises a plurality of semiconductor quantum dot devices.
6. The circuit of claim 1, wherein the plurality of quantum electrical devices further comprises a conjugated polymer.
7. The circuit of claim 1, wherein the plurality of quantum electrical devices further comprises a plurality of quantum dot devices configured to form coherent electron conduction bands.
8. The circuit of claim 1, wherein the plurality of quantum electrical devices further comprises a plurality of quantum dot devices configured to form coherent electron conduction bands that bind ferritin in vivo.
9. The circuit of claim 1, wherein the plurality of quantum electrical devices further comprises a plurality of quantum dot devices configured to form coherent electron conduction bands that combine with neural melanin in vivo.
10. The circuit of claim 1, further comprising: a conjugated polymer.
11. The circuit of claim 1, wherein the plurality of quantum electrical devices further comprises a plurality of conjugated polymer quantum dot devices.
12. The circuit of claim 1, wherein the plurality of quantum electrical devices further comprises a plurality of conjugated polymer quantum dot devices and a plurality of at least partially inorganic quantum dot devices.
13. The circuit of claim 1, further comprising: a physical stress-creating device coupled to the circuit.
14. The circuit of claim 1, further comprising: a physical stress-creating device coupled to the electrical circuit and configured to apply physical stress to the electrical circuit to localize electrons.
15. The circuit of claim 1, further comprising: a piezoelectric device coupled to the circuit.
16. The circuit of claim 1, further comprising: a control circuit coupled to the circuit.
17. The circuit of claim 1, further comprising: a control circuit coupled to the circuitry and configured to apply an electrical signal to the first electrode.
18. The circuit of claim 1, further comprising: a control circuit coupled to the circuitry and configured to apply electrical signals to the first and second electrodes.
19. The circuit of claim 1, further comprising: a control circuit coupled to the circuitry and configured to sense the in-vivo signal and apply an electrical signal to the first electrode in synchronization with the in-vivo signal.
20. The circuit of claim 1, further comprising: a control circuit coupled to the circuitry and configured to apply an electrical signal to the first electrode.
21. The circuit of claim 1, further comprising: a sensor coupled to the circuit.
22. The circuit of claim 1, further comprising: a sensor coupled to the circuit and configured to measure a time-varying signal of the circuit.
23. The circuit of claim 1, further comprising: a sensor coupled to the circuit and configured to measure a time-varying signal related to the coherent electron conduction band.
24. The circuit of claim 1, further comprising: a plurality of additional circuits, each additional circuit comprising: a first electrode, a second electrode, and a plurality of quantum dot devices disposed between the first and second electrodes. The second electrode is coupled to an impedance, and the impedance is selected to be a value that conducts current or prevents current from conducting when one or more quantum dot devices (e.g., quantum dot devices in adjacent circuits) form a coherent electronic conduction band.
25. The circuit of claim 23, wherein the impedance of the one or more additional circuits is a controllable impedance.
26. The circuit of claim 23, further comprising: a network coupled to a plurality of additional circuits.
27. The circuit of claim 25, wherein the network is a neural network.
28. The circuit of claim 23, further comprising: one or more sensing circuits coupled to one or more additional circuits.
29. The circuit of claim 23, further comprising: one or more sensing circuits coupled to each additional circuit.
30. The circuit of claim 23, further comprising: one or more status circuits coupled to the one or more additional circuits.
31. The circuit of claim 23, further comprising: one or more status circuits coupled to each additional circuit.
32. The circuit of claim 23, further comprising: one or more data circuits coupled to the one or more additional circuits.
33. The circuit of claim 23, further comprising: one or more data circuits coupled to each additional circuit.
34. The circuit of claim 23, further comprising: one or more motor control circuits coupled to the one or more additional circuits.
35. The circuit of claim 23, further comprising: one or more motor control circuits coupled to each additional circuit.
36. The circuit of claim 23, further comprising: one or more sensing circuits coupled to one or more additional circuits; one or more status circuits coupled with the one or more additional circuits; one or more data circuits coupled to the one or more additional circuits; one or more motor control circuits coupled to the one or more additional circuits.
37. The circuit of claim 23, further comprising: one or more sensing circuits coupled to each additional circuit; one or more status circuits coupled to each additional circuit; one or more data circuits coupled to each additional circuit; one or more motor control circuits coupled to each additional circuit.
38. The circuit of claim 1, further comprising: a first neural network coupled to the first electrode.
39. The circuit of claim 37, further comprising: a second neural network coupled to the second electrode.
40. The circuit of claim 38, wherein the first neural network is coupled with the second neural network.
41. The circuit of claim 38, wherein a node of the first neural network is coupled with a node of the second neural network.
42. The circuit of claim 40, wherein a second node of the second neural network is coupled to a second node of the first neural network and provides an output to the second node of the first neural network.
43. The circuit of claim 38, further comprising: a plurality of electron transfer devices, each of the electron transfer devices comprising: a first electrode, a second electrode, and a plurality of quantum dot devices disposed between the first and second electrodes. The second electrode is coupled to an impedance, and the impedance is selected to be a value that conducts current or prevents conduction of current when one or more quantum dot devices in combination with any one or more of the quantum dot devices of claim 1, or the plurality of electron transfer devices, form a coherent electron conduction band.
44. The circuit of claim 1 forming an electron transfer device and the external quantum dot apparatus is disposed in one or more additional electron transfer devices.
45. The circuit of claim 43, further comprising: a neural network coupled to the electron transfer device and one or more additional electron transfer devices.
46. The circuit of claim 44, further comprising: a first set of image data inputs provided to the neural network, and a second set of image data inputs provided to the electronic delivery device and one or more additional electronic delivery devices.
47. The circuit of claim 44 further comprising: a first set of image data inputs provided to the neural network, and a second set of image data inputs provided to the electronic delivery device and one or more additional electronic delivery devices. Wherein the first set of image data inputs is the same as the second set of image data inputs.
48. The circuit of claim 37, wherein the first neural network comprises a plurality of discrete circuits.
49. A circuit comprising: a first electrode, a second electrode, a plurality of quantum dot devices disposed between said first electrode and said second electrode, a controllable impedance coupled to said second electrode, a third electrode, a fourth electrode, a plurality of quantum dot devices disposed between said third electrode and said fourth electrode, a controllable impedance coupled to said fourth electrode, an electron transfer mechanism formed by the combination of the plurality of quantum dot devices disposed between said first electrode and said second electrode and the plurality of quantum dot devices disposed between said third electrode and said fourth electrode, a controller coupled to said first controllable impedance and said second controllable impedance, and, when the first controllable impedance is approximately equal to the second controllable impedance, said controller is configured to adjust the first controllable impedance and the second controllable impedance to create an equilibrium state to prevent electron localization, when the first controllable impedance is not equal to the second controllable impedance, the controller is configured to create an unbalanced state to localize electrons between the first and second electrodes; further comprising a first neural network coupled to the first electrode and the third electrode, the first neural network comprising a plurality of nodes, a plurality of inputs, and a plurality of outputs; a second neural network coupled to the second electrode and the fourth electrode, the second neural network comprising a plurality of nodes, a plurality of inputs, and a plurality of outputs; further comprising a set of image data inputs coupled to the first neural network, the second neural network, and the first controllable impedance; further comprising a plurality of feedback connections between the second neural network and the first neural network; wherein the first neural network comprises a plurality of discrete circuits.
CN201880070919.4A 2017-10-29 2018-10-29 Electron transfer gate circuit and methods of making, operating and using the same Pending CN111357118A (en)

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