CN111356907A

CN111356907A - Thermal detector and thermal detector array

Info

Publication number: CN111356907A
Application number: CN201880070853.9A
Authority: CN
Inventors: 阿波·瓦普拉; 郭斌
Original assignee: Valtion Teknillinen Tutkimuskeskus
Current assignee: Valtion Teknillinen Tutkimuskeskus
Priority date: 2017-08-31
Filing date: 2018-08-31
Publication date: 2020-06-30
Anticipated expiration: 2038-08-31
Also published as: JP2023184524A; JP2020531861A; CN111356907B; WO2019043299A1; EP3676584A1; JP7438936B2; US11199455B2; US20200309603A1

Abstract

A wafer-level integrated thermal detector includes first and second wafers (W1, W2) bonded together. The first wafer (W1) comprises a dielectric or semiconductor substrate (100), a sacrificial layer (102) of a dielectric deposited on the substrate, a support layer (104) deposited on the sacrificial layer or substrate, a suspended active element (108) disposed within an opening (106) in the support layer, a first vacuum-tight cavity (110) and a second vacuum-tight cavity (106) located opposite the suspended active element. The first vacuum-tight cavity (110) extends into the sacrificial layer (102) at the location of the suspended active element (108). The second vacuum-tight chamber (106) comprises an opening of the support layer (104), the bonded second wafer closing the opening. The thermal detector further includes front optics (120) for externally entering radiation into the first and second vacuum-sealed cavities, a back reflector (112) arranged to reflect radiation back to the other of the first and second vacuum-sealed cavities, and electrical connections (114) for connecting the suspended active elements to readout circuitry (118).

Description

Thermal detector and thermal detector array

Technical Field

The present invention relates to a thermal sensor or detector, and in particular to a suspended thermal sensor or detector, such as a resistance bolometer or a pyroelectric bolometer.

Background

In a thermal detector, a thermally isolated detector element absorbs incident infrared photons, causing the element to change temperature. The resulting temperature rise is a function of the radiant energy impinging on the bolometer. The temperature change changes the temperature sensitive electrical characteristic of the probe, which can be measured externally, for example using the pyroelectric temperature sensing principle, the resistance temperature sensing principle or other temperature sensing principles. The circuitry used to perform the measurements is commonly referred to as a read-out integrated circuit (ROIC), which is typically fabricated as an integrated circuit on a silicon substrate. The thermal detector may be arranged to absorb various types of electromagnetic radiation, such as Ultraviolet (UV) light, visible light, Infrared (IR) light, terahertz (THz) radiation and X-rays.

Thermal detectors require temperature changes to produce a signal and, in contrast to photodetectors that minimize noise by cooling, cooling is generally not required. Since these detectors rely on temperature changes caused by incident radiation, they must be thermally isolated from the surrounding environment, and they must have a low thermal capacity to respond quickly to radiation.

For example a microbolometer, a conventional suspended detector is shown in fig. 1. The electromagnetic radiation is typically absorbed by an absorbing film 10, which is suspended above the reflective metal layer 12 by a thermally insulating arm 9, which thermally insulating arm 9 is fixed on a substrate 13 via an anchoring point or supporting bolt 8. The absorbing film 10 is thermally isolated from the substrate to increase the sensitivity of the microbolometer. The absorbed incident radiation causes the absorbing film of the thermally isolated bolometer to increase in temperature. The temperature change is related to the energy of the absorbed radiation and is measured by a change in a measurable electrical parameter, such as the resistance of the bolometer thermistor material in the absorbing film. A resonant cavity 11 is formed between the absorption film 10 and the reflective metal layer 12. The resonant cavity 11 is used to amplify and absorb incident infrared radiation and provide thermal insulation.

A microbolometer detector array may be used to sense the focal plane of incident radiation (typically infrared). The collection of thermal detectors in a two-dimensional array is referred to as a Focal Plane Array (FPA). With each microbolometer as a pixel, a two-dimensional image or picture of the incident infrared radiation can be generated by converting the change in resistance of each microbolometer into a time-division multiplexed electrical signal that can be displayed on a monitor or stored in a computer. The circuitry used to perform this conversion is commonly referred to as a read-out integrated circuit (ROIC), which is typically fabricated as an integrated circuit on a silicon substrate. The array of microbolometers may then be disposed on top of the ROIC.

Since the microbolometer does not perform any cooling, the absorptive material must be thermally isolated from the underlying ROIC, and the suspension structure allows this to occur. After the pixel array is created, the microbolometers are packaged under vacuum to increase the useful life of the device. In some cases, the entire manufacturing process is performed without breaking vacuum. An important advantage of micro-electromechanical system (MEMS) based bolometer arrays is that the technology can provide low cost wafer level vacuum packaging. One approach is wafer level packaging, which forms a lid with a silicon infrared window over the bolometer pixels or over the pixel array (focal plane array) formed on a ROIC substrate wafer.

In the article "MEMS-Based Uncooled Infrared Bolometer Arrays-A Review, FNiklaus et al, MEMS/MOEMS Technologies and Applications III, Proc. of SPIEVol.6836, 68360D, (2007)", the historical development of Uncooled Infrared Bolometer technology, the historical development of different technical concepts, and the historical development of Bolometer design methods and Bolometer materials are summarized.

Review articles: "Integrating MEMS and ICs, AC Fischer et al, Microsystems & Nanoengineering (2015)1, 15005; 10.1038/microano.2015.5; 28May 2015 ", discloses different methods for integrating and packaging microelectromechanical system (MEMS) devices and Integrated Circuit (IC) components. These methods include methods based on multi-chip hybrid integration (multi-chip solutions) and system-on-chip solutions based on wafer-level monolithic integration techniques and heterogeneous integration techniques.

A Direct wafer bonding process is disclosed in the article "Direct wafer bonding for MEMS and microelectronics, Sun T., VTTPublications 609, Espoo 2006, ISBN 951-38-6851-6".

Examples of the concept, structure and fabrication process of MEMS Fabry-Perot interferometers (FPIs) are disclosed in the article "Silicon-based surface micro interferometric modulators for infraredwavelentgths, Mikko Tuohiniemi, Aalto University visualization servers, sectorial degenerations 54/2015, 18March 2015, ISBN 978-. The FPI is a tunable optical bandpass filter. The structure of the dielectric multilayer mirror, Distributed Bragg Reflector (DBR), is also disclosed, especially outlining the production of micro FPIs using micro-electromechanical systems (MEMS) based on a specific type of silicon-air multilayer film DBR.

The article "Suspended Large-Area Mems-Based Optical Filters, Tripathi et al, Journal of MicroElectromechanical Systems, August 2015, p.1102-1110" discloses a tunable Fabry-Perot cavity in hybrid combination with a detector or imaging FPA.

Disclosure of Invention

It is an aspect of the present invention to provide a new wafer level integrated suspended thermal detector structure. The invention comprises a wafer level integrated suspended thermal detector, a detector array and a prefabricated intermediate product according to the independent claims. Preferred embodiments of the invention are disclosed in the dependent claims.

One aspect of the invention is a wafer-level integrated thermal probe comprising:

a first wafer and a second wafer bonded together, wherein the first wafer comprises a substrate of dielectric or a substrate of semiconductor, a sacrificial layer of dielectric deposited on the substrate in wafer-wide or partially patterned, a support layer deposited on the sacrificial layer of dielectric or the sacrificial layer of semiconductor or the substrate, a suspended active element disposed within an opening of the support layer,

a first vacuum-tight cavity and a second vacuum-tight cavity are provided on opposite sides of the suspended active element, wherein the first vacuum-tight cavity extends into the sacrificial layer at the location of the suspended active element, the second vacuum-tight cavity comprises an opening of the support layer, which opening is closed by the bonded second wafer,

a front optic as an entrance for external radiation into one of the first and second vacuum-sealed cavities,

a rear reflector arranged to reflect radiation back to the other of the first and second vacuum-sealed cavities, an

Electrical connections for connecting the suspended active element to a readout circuit.

In an embodiment of the thermal detector, the first and second wafers are bonded using a fusion activated bonding process, a plasma activated bonding process, a thermocompression bonding process, or other metal-based wafer bonding process.

In an embodiment of the thermal detector the electrical connections are arranged for connection to a read-out circuit integrated on the third wafer, preferably by means of a thermocompression bonding method, other metal-based bonding methods or a die bonding method.

In an embodiment of the thermal detector, the front optics comprise: a transparent substrate, a window on the substrate, an anti-reflection coating, a lens, a filter, a front mirror, a controllably movable front mirror, a fabry-perot interferometer, a tunable fabry-perot interferometer.

In an embodiment of the heat detector, the rear reflector comprises: one or more of a back mirror, a metal back mirror, a distributed Bragg reflector, a controllably movable back mirror, a Fabry-Perot interferometer, and an adjustable Fabry-Perot interferometer.

In an embodiment of the heat detector, the rear reflector is arranged inside the other of the first and second wafers, or outside the other of the first and second wafers behind a transparent substrate or window, or in an opening provided by the other of the first and second wafers.

In an embodiment of the heat detector, the support layer further comprises a thin shoulder on the periphery of the opening for mechanical and electrical connection with the suspended active element, and preferably the thin shoulder is offset from the bonding surface of the first wafer.

In an embodiment of the thermal detector, the thermal detector further comprises a movable reflector of a fabry-perot interferometer, the movable reflector being provided within one of the first and second vacuum-tight cavities, wherein vacuum spaces are present on both sides of the movable reflector.

In an embodiment of the thermal detector, the fixed reflector of the fabry-perot interferometer and the movable reflector of the fabry-perot interferometer are both arranged in the same one of the first and second vacuum-tight cavities, the fixed reflector of the fabry-perot interferometer and the movable reflector of the fabry-perot interferometer being located at a front side of the suspended active element.

In an embodiment of the heat detector, the movable reflector is arranged in one of the first and second vacuum-tight chambers, the movable reflector being located at a rear side of the suspended active element.

In an embodiment of the heat detector, the movable reflector is configured to act as the back reflector.

In an embodiment of the thermal detector, a fixed reflector of a fabry-perot interferometer is arranged at the front side of the suspended active element.

In an embodiment of the heat detector, the heat detector further comprises a support structure for mechanically supporting the movable reflector within one of the first and second vacuum-tight cavities.

In an embodiment of the thermal detector, the thermal detector further comprises an electrical connection for connecting the movable reflector with a drive controller for adjusting the fabry-perot interferometer.

In an embodiment of the heat detector, the electrical connection of the movable reflector comprises a pair of electrostatic actuation electrodes.

In an embodiment of the thermal detector, the thermal detector is configured to absorb one of the following wavelength ranges of electromagnetic radiation: ultraviolet (UV) light, visible light, Infrared (IR) light, terahertz (THz) radiation, and X-rays.

An aspect of the invention is an integrated thermal detector array comprising a plurality of thermal detectors according to any of the embodiments.

An aspect of the invention is a pre-fabricated intermediate product for use in fabricating an integrated thermal detector in any embodiment or an integrated thermal detector array in any embodiment, comprising the first wafer pre-fabricated to comprise the substrate, the suspended active devices, the support layer and the sacrificial layer supporting a dielectric of the suspended active devices.

In an embodiment of the prefabricated intermediate product, the first wafer is also prefabricated to comprise a fabry-perot interferometer, a fixed reflector of the fabry-perot interferometer or a movable reflector of the fabry-perot interferometer on an inner side of the first wafer.

An aspect of the invention is a pre-fabricated intermediate product for manufacturing an integrated thermal detector in any embodiment or an integrated thermal detector array in any embodiment, comprising the second wafer, pre-fabricated to comprise a substrate of a dielectric or a substrate of a semiconductor on an inner side of the second wafer, and a movable reflector of a fabry-perot interferometer.

Drawings

The invention will be described in more detail hereinafter by means of exemplary embodiments and with reference to the accompanying drawings, in which,

fig. 1 shows a schematic view of an exemplary conventional hanging probe.

Fig. 2A and 2B show schematic views of an exemplary hanging probe in accordance with an aspect of the present invention.

FIGS. 3A, 3B, and 3C illustrate schematic diagrams of an exemplary suspended detector array in accordance with an aspect of the present invention.

FIGS. 4A, 4B, 4C, 4D, 4E and 4F illustrate examples of anterior optics that may be provided in a thermal detector or thermal detector array according to an aspect of the present invention.

Fig. 5A, 5B, 5C, and 5D show examples of achieving electrical connection with the suspended active thermal element in the first wafer W1.

Fig. 6A, 6B and 6C show schematic views of an exemplary suspended probe (wafer level integrated thermal probe 20) provided using a fusion activated wafer bonding process or a plasma activated wafer bonding process in accordance with an aspect of the present invention.

Fig. 7 shows a schematic diagram of an exemplary hanging probe having a rear reflector 112 located on the back side of a second wafer W2.

Fig. 8A, 8B and 8C show schematic diagrams of exemplary suspended detectors in which the rear reflector acts as a Distributed Bragg Reflector (DBR).

Fig. 9A, 9B and 9C show schematic views of an exemplary suspended prober 20 provided using a thermocompression wafer bonding process in accordance with an aspect of the present invention.

Fig. 10 illustrates a schematic view of another exemplary suspended prober 20 resulting from use of a thermal compression wafer bonding process in accordance with an aspect of the present invention.

FIG. 11 illustrates a schematic diagram of an exemplary suspended detector array including a plurality of thermal detectors using a thermal compression wafer bonding process in accordance with an aspect of the present invention.

FIG. 12 illustrates a schematic diagram of an exemplary suspended detector array including a plurality of thermal detectors using a thermal compression wafer bonding process in accordance with an aspect of the present invention.

Fig. 13A and 13B show a schematic view of an exemplary suspended probe 20 provided using a fusion activated wafer bonding process or a plasma activated wafer bonding process in accordance with an aspect of the present invention.

Fig. 14A and 14B show schematic diagrams of an exemplary wafer-level integrated thermal detector 20 having a movable reflector of a fabry-perot interferometer (FPI) provided in a vacuum, in accordance with an aspect of the present invention.

Fig. 15 illustrates a more detailed schematic view of an exemplary hanging probe 20 resulting from use of a fusion activated wafer bonding process or a plasma activated wafer bonding process in accordance with an aspect of fig. 14B. And

fig. 16 illustrates a more detailed schematic diagram of an exemplary suspended prober 20 resulting from use of a thermal compression wafer bonding process in accordance with an aspect of fig. 14B.

Detailed Description

It should be understood that the schematic diagrams presented herein may not show various optional, alternative, and preferred features and details that may be present in the detector, such as electrically insulating layers, vacuum sealing layers, protective layers, anti-reflective layers, adhesive layers, and the like. Examples of these features are given in the different further embodiments below. Examples of detailed fabrication processes and materials for fabricating MEMS devices and for wafer bonding on dielectric or semiconductor substrates are given in Silicon-based surface micro-machined interferometers for induced wafers "by Tuohiniemi and" Direct wafer bonding for MEMS and microelectronics "by Suni, which publications are incorporated herein by reference. Embodiments of the present invention may be applicable to a wide range of wavelengths, including Ultraviolet (UV) light, visible light, Infrared (IR) light, terahertz (THz) radiation, and X-rays. Examples of the dielectric substrate material include silicon oxide (SiO2) and aluminum oxide (Al2O 3). SiO2 or Al2O3 are particularly suitable for wavelengths smaller than 4 μm. Examples of substrate materials for semiconductors are monocrystalline or polycrystalline silicon, germanium (Ge), and compound semiconductors such as CdTe, ZnSe and ZnS, polycrystalline silicon also known as polymerized silicon or polysilicon. Embodiments of the present invention may be applicable to any type of suspended active thermal element, such as a pyroelectric element, a resistive thermal element or an active semiconductor element based thermal element, where temperature is sensed using a temperature dependent electrical characteristic (e.g., current-voltage curve). Fig. 2A and 2B illustrate schematic diagrams of exemplary hanging detectors illustrating some basic principles according to an aspect of the present invention. The wafer level integrated heat detector 20 includes a first wafer W1 and a second wafer W2 bonded together. The first wafer W1 includes a first substrate 100, a wafer-wide or partially patterned sacrificial layer 102 of dielectric deposited on the dielectric or semiconductor first substrate 100, a dielectric or semiconductor support layer 104 deposited on the dielectric sacrificial layer 102 or surrounding the partially patterned dielectric sacrificial layer 102 deposited on the first substrate 100, a suspended active thermal element 108, the suspended active thermal element 108 disposed within an opening (recess) 106 in the support layer 104. As schematically shown in fig. 2A, the suspended thermal element 108 may initially be located on a wafer-wide or partially patterned dielectric sacrificial layer 102 that supports and protects the suspended active thermal element 108 during fabrication. The second wafer W2 may include a back reflector 112, the back reflector 112 being configured to reflect light back toward the suspended thermal element 108.

In an embodiment of the present invention, at least one of the first and second wafers W1 and W2 may include a prefabricated intermediate product.

According to an embodiment of the invention, said first wafer W1 may comprise a prefabricated intermediate product comprising at least a first substrate 100 of dielectric or semiconductor, a sacrificial layer 102 of dielectric at least partially deposited on said first substrate 100, and a suspended active thermal element 108 on said sacrificial layer of dielectric, preferably also comprising a supporting layer 104 of dielectric or semiconductor.

In an embodiment of the invention, the first wafer W1 may comprise a prefabricated intermediate product to further comprise suitable front optics 120 to allow radiation to enter the suspended active thermal element 108 from the outside.

In an embodiment of the present invention, the second wafer W2 may include a pre-fabricated intermediate product that includes at least the back reflector 112.

As schematically shown in fig. 2B, the sacrificial layer 102 may be designed to be removed from the location of the suspended active elements 108 to release the active elements 108 before the complete wafer-level manufacturing process is finished. A first vacuum-tight cavity 110 is provided extending in the sacrificial layer 102, preferably completely or at least partially on the portion of the dielectric from which the sacrificial layer 102 is removed from the position of the suspended active element 108. A second vacuum-tight chamber is provided on the opposite back side of the suspended active thermal element 108, for example in an opening of the support layer 104, which is closed by the bonded second wafer W2. The front optics 120 are arranged to transfer radiation from the outside into the first vacuum-tight chamber 110. The back reflector 112 is arranged to reflect light into the second vacuum-tight cavity (opening (groove) 106).

In addition, electrical connections 114 may be provided to connect the suspended active element 108 to external circuitry, such as a read-out integrated circuit (ROIC) or other type of read-out device. In the example shown in fig. 2A and 2B, a detector chip (wafer level integrated thermal detector 20) is mounted on top of and connected to the ROIC.

Fig. 3A, 3B and 3C show schematic diagrams of exemplary suspended detector arrays illustrating some basic principles in accordance with an aspect of the invention the detector array may be considered to comprise a plurality of thermal detectors, such as detectors in accordance with an aspect of the invention illustrated in fig. 2A and 2B, thus, a wafer level integrated thermal detector array chip 200 comprises a first wafer W1 and a second wafer W2 bonded together-the array (array chip 200) may be a one-dimensional array or a two-dimensional M × N array, where M and N are positive integers-the first wafer W1 comprises a dielectric or semiconductor first substrate 100, a wafer-wide or partially patterned sacrificial layer of dielectric 102 deposited on the first substrate 100, a dielectric or semiconductor support layer 104 deposited on the sacrificial layer of dielectric 102 or on the first substrate 100, an M × N array of active thermal sensitive elements 108, the M × N array of the suspended active thermal sensitive elements 108 being provided by a corresponding M × array of openings (recesses 106) in the sacrificial layer 104 to provide the second array of suspended thermal sensitive elements 108 to reflect light back to the wafer 2.

According to an embodiment of the invention, said first wafer W1 comprises a prefabricated intermediate product comprising at least a first substrate 100 of dielectric or semiconductor, a sacrificial layer 102 of dielectric deposited on said first substrate 100 of wafer-wide or locally patterned dielectric and an MxN array of suspended active thermal elements 108 on said sacrificial layer of dielectric, preferably further comprising a support layer 104 of dielectric or semiconductor.

In an embodiment of the invention, the first wafer W1 may comprise an intermediate product that is prefabricated to further comprise suitable front optics 120 to allow radiation to enter the suspended active thermal element 108 from the outside.

In an embodiment of the present invention, the second wafer W2 may comprise an intermediate product that is pre-fabricated to further comprise a one-dimensional array or a two-dimensional M × N array of back reflectors 112.

As schematically shown in FIG. 3A, each suspended thermal element 108 is initially located on top of a wafer-wide or partially patterned sacrificial layer 102 that supports and protects the suspended thermal element 108 during the fabrication process, as schematically shown in FIG. 3B, the sacrificial layer 102 may be arranged to be removed from the location of the suspended active element 108 of M × N before the end of the complete wafer-level fabrication process to release the active element 108. A first vacuum-sealed cavity 110 may also be provided extending in the sacrificial layer 102, preferably the first vacuum-sealed cavity 110 is defined fully or partially in the portion of the sacrificial layer 102 removed from the location of each suspended active element 108. As shown in FIG. 3B, a first vacuum-sealed cavity 110 forming a one-dimensional array or a two-dimensional M × N array may be provided and separated from each other by an intermediate remaining portion of the sacrificial layer 102, or separated from each other by the supporting layer 104 deposited on the substrate. As shown in FIG. 3C, the suspended thermal-sealed cavities 102 may be arranged to be separated from each other by a second vacuum-sealed cavity 120 (e.g., a second vacuum-sealed cavity 106) arranged to be connected to each other by a second vacuum-sealed cavity 120, such as a one-dimensional array of suspended thermal-dimensional optical elements 108, such as a two-dimensional array of suspended thermal-dimensional optical semiconductor wafer-sealed cavities 120, such as a two-dimensional array or two-dimensional array of suspended thermal-dimensional optical semiconductor wafer-dimensional back-sealed cavities 120, such as a two-dimensional array, a two-dimensional array of suspended thermal-one-dimensional array, or two-dimensional array of suspended active elements similar to be provided by two-dimensional array of suspended thermal-one-vacuum-dimensional optical semiconductor wafer-vacuum-sealed cavities 120, or two-vacuum-one-sealed cavities 120, e.g. vacuum-one-vacuum-sealed cavities 120, e.g., a second vacuum.

Furthermore, electrical connections 114 may be provided to connect each suspended active element 108 individually to external circuitry, such as to a read-out integrated circuit (ROIC) or other type of read-out device. In the example shown in fig. 3A, 3B and 3C, the detector array chip 200 is mounted on top of and connected to the ROIC.

As in fig. 4A, 4B, 4C, 4D, 4E and 4F, examples of front optics 120 that may be provided in a thermal detector or thermal detector array of any aspect of the present invention are shown. It should be understood that these schematic representations may not show the various optional, alternative, and preferred features and details that may be present in various applications of anterior optics. In examples, front optics for two arrays of thermal detectors are shown, but similar front optics may be applied to any thermal detector array or a single thermal detector in any aspect and embodiment of the invention.

In an embodiment, the front optics 120 may include an anti-reflective coating on the front surface of the first wafer W1 to reduce reflections. In fig. 4A, an exemplary antireflective coating with a single film 400 is shown. In fig. 4B, an exemplary antireflective coating is shown with a stacked multilayer film (a first film 402, a second film 404, and a third film 406). The stacked multilayer film may include alternating layers of opposite refractive index (low index material and high index material) such that the stacked dielectric films or layers may form a distributed bragg reflector DBR. The thickness of each film or layer is preferably one quarter of the target wavelength λ. Examples of suitable materials for the IR wavelength include Si, Ge, CdTe, ZnSe, and ZnS. The anti-reflective coating may be deposited on the front surface of the first wafer W1 at a suitable stage in a pre-fabrication process or manufacturing process.

In an embodiment, the front optics 120 comprise an anti-reflection structure on the front surface of the first wafer W1 to reduce reflections. As shown in fig. 4C, one example of an anti-reflection structure is a multiple air distributed bragg reflector having a multi-layered structure including alternating polysilicon layers (first polysilicon layer 410, second polysilicon layer 414) and air gaps (first air gap 412, second air gap 416).

As schematically shown in fig. 4D, in an embodiment, the front optics 120 may comprise at least one microlens 420 arranged to focus and concentrate radiation onto the suspended active element 108. There are also single element lenses or microlens arrays (also referred to as micro lens arrays or lenslet arrays). The microlens array includes a one-dimensional array or a two-dimensional array formed with a plurality of lenses. Microlenses may be grown or disposed on the front surface of the first wafer W1 at the appropriate stage of the pre-fabrication or manufacturing process.

In an embodiment, the front optics 120 may include at least one grating, for example, a groove-shaped or other embossed pattern provided on the front surface of the first wafer W1 at an appropriate stage of the fabrication or manufacturing process.

In an embodiment, as schematically illustrated in fig. 4E, the front optics 120 may comprise at least one fresnel microlens arranged to focus and concentrate the radiation onto the suspended active element 108. The fresnel microlens may be composed of a number of separate annular zones (first annular zone 30, second annular zone 32, third annular zone 34, fourth annular zone 36, and fifth annular zone 38), each having a smooth contour. A grating (e.g., a groove-shaped or other embossed pattern), a preformed single-element lens or a microlens array may be provided on the front surface of the first wafer W1 at a suitable stage of a preforming process or a manufacturing process to implement fresnel microlenses.

As shown in fig. 4F, in an embodiment the front optics 120 may comprise at least one fabry-perot interferometer. A fabry-perot interferometer (FPI) is a band-pass filter for electromagnetic radiation at optical frequencies that produces a narrow pass-band, called the transmission peak. This operation is based on optical interference between two facing and parallel reflectors (mirrors) (a first reflector (mirror) 450 and a second reflector (mirror) 452), which are generally flat plates, and located in an intermediate cavity 454, which intermediate cavity 454 forms an optical one-dimensional resonator. The outgoing signal, i.e. the transmission signal, leaks out at the resonance wavelength, i.e. the transmission wavelength, where the spectrum of the transmission peak propagates in the initial direction of the incoming signal. In order to couple the incoming signal and to emit the transmitted signal, the reflector (mirror) may be a semi-transparent reflector, which does not have a reflectivity of 100% but has a limited transmissivity. The main design factor for the transmission peak or transmission wavelength is the spacing or gap between the facing reflectors. In an embodiment, a front optic with a tunable fabry-perot interferometer is provided, wherein one of the parallel reflectors (mirrors) is movable to tune the spectral position of the transmission peak.

Fig. 5A, 5B, 5C and 5D schematically illustrate examples of making electrical connections 114 from the suspended active thermal element 108 in the first wafer W1 to external circuitry, such as a read-out integrated circuit (ROIC) or other type of read-out device.

In an embodiment, the support layer 104 may be made of a conductive material or a semiconductor material, such as metal or polysilicon, also referred to as poly-silicon or polysilicon. Thus, the electrical connection 114 in the first wafer W1 may be achieved through the support layer 104 without the need for separate wiring. The support layer 104 of the first wafer W1 may then be connected to electrical connections on the second wafer W2 or to external circuitry such as ROICs.

In fig. 5A, a first wafer W1 may include a front optic 120 (e.g., an anti-reflective layer), a dielectric or semiconductor first substrate 100, a wafer-wide or partially patterned dielectric sacrificial layer 102 deposited on the first substrate 100 and a dielectric or semiconductor support layer 104 deposited on the dielectric sacrificial layer 102 or the first substrate 100, a suspended active thermal element 108 disposed within an opening (recess) 106 of the support layer 104. The support layer 104 may be made of a conductive or semiconductive material, such as polysilicon. The support layer 104 may further comprise a thin shoulder 104a on the periphery of the opening (groove) 106, the thin shoulder 104a being used for mechanical and electrical connection of the suspended active element 108. Thus, especially when the first wafer W1 and the second wafer W2 are wafer bonds activated by fusion or plasma, the thin shoulder 104a and the support layer 104 will provide an electrical connection 114 from the suspended active thermal element 108 to the second wafer W2. In an embodiment, the thin shoulder 104a may preferably be offset from the inner surface of the first wafer W1, and more preferably, the support layer 104 may be deposited on the sacrificial layer 102 at the bottom of the opening (groove) 106. The thin shoulder 104a being offset allows mechanical and electrical connection of the suspension element 108 to the handle layer 104 without compromising the inside smoothness of the first wafer W1 and thus the bonding quality of the wafer to the second wafer W2.

In fig. 5B, the outer diameter of the suspended active thermal element 108 may be equal to the diameter of the opening (groove) 106, such that the suspended active thermal element 108 may be directly connected to the support layer 104. The support layer 104 may be made of a conductive or semiconductive material, such as polysilicon. Therefore, especially when the first wafer W1 and the second wafer W2 are fusion-activated wafer bonds or plasma-activated wafer bonds, the support layer 104 will provide an electrical connection 114 from the suspended active thermal element 108 to the second wafer W2.

Fig. 5C shows a first wafer W1, similar to the first wafer W1 shown in fig. 5A, further comprising a conductive layer or wire 502, the conductive layer or wire 502 being disposed to extend from the inner surface of the thin shoulder 104a to the inner surface of the suspended active thermal element 108. The conductive layer or wire 502 may be made of any conductive material, for example, a metal or other conductive material, such as polysilicon. The mechanical and electrical connection of the suspension element 108 to the support layer 104 may be achieved without depositing a conductive material on the inner surface of the opening (groove) 106 or on the inner side of the first wafer W1. Therefore, the smoothness of the inner side of the first wafer W1 may not be impaired, and thus the bonding quality of the wafer with the second wafer W2 may not be impaired.

Fig. 5D shows a first wafer W1, similar to the first wafer W1 shown in fig. 5B, further including a conductive layer or wire disposed to extend from the inner surface of the thin shoulder 104a to the inner surface of the suspended active thermal element 108. The conductive layer or wire may be made of any conductive material, for example metal or other conductive material, such as polysilicon. The mechanical and electrical connection of the suspension element 108 to the handle layer 104 can be achieved without depositing material inside the first wafer W1. Therefore, the smoothness of the inner side of the first wafer W1 may not be impaired, and thus the bonding quality of the wafer with the second wafer W2 may not be impaired. However, it is more challenging to control the deposition of the conductive layer so that the inner surface of the first wafer W1 is not affected than in the embodiment shown in fig. 5.

In an embodiment of the present invention, the first wafer W1 and the second wafer W2 may be bonded using a fusion activation bonding method or a plasma activation bonding method or a thermocompression bonding method or other metal-based bonding methods.

In an embodiment of the invention, the electrical connections 114 may be connected to a readout integrated circuit ROIC118, preferably provided on the third wafer, preferably by thermo-compression bonding or other metal-based bonding or die bonding.

Fig. 6A, 6B and 6C show schematic views of an exemplary suspended probe 20 provided using a fusion activated wafer bonding process or a plasma activated wafer bonding process in accordance with an aspect of the present invention.

In fig. 6A, the first wafer W1 and the second wafer W2 are attached and bonded together. The first wafer W1 includes a dielectric or semiconductor first substrate 100, a wafer-wide or partially patterned dielectric sacrificial layer 102 deposited on the inside of the first substrate 100, a dielectric or semiconductor support layer 104 deposited on the inside of the dielectric sacrificial layer 102 or on the first substrate 100, and a suspended active thermal element 108 disposed in an opening (recess) 106 of the support layer 104. As schematically shown in fig. 6A, the suspended thermal element 108 may initially be located on a wafer-wide or partially patterned sacrificial layer 102 that supports and protects the suspended thermal element 108 during the manufacturing process. The second wafer W2 may include a dielectric or semiconductor second substrate 116, a back reflector 112 disposed inside the second substrate 116. Optionally, a second sacrificial layer 601 of dielectric is provided outside the back reflector 112, on the inside of the second substrate 116. The second sacrificial layer 601 may be used to facilitate or improve a subsequent fusing process and/or to provide electrical insulation between the first wafer W1 and the second W2. Alternatively, a corresponding sacrificial layer may be provided inside the support layer 104 on the first wafer W1 instead of or in addition to the second sacrificial layer 601 on the second wafer W2.

In an embodiment of the invention, the support layer 104 further comprises a thin shoulder 104a provided on the periphery of the opening (groove) 106, the thin shoulder 104a being used for mechanical and optionally electrical connection of the suspended active element 108. Preferably, the thin shoulder 104a is offset from the inner surface of the first wafer W1, and more preferably, the thin shoulder 104a is deposited on the sacrificial layer 102 at the bottom of the opening (groove) 106.

In an embodiment of the present invention, the support layer 104 is made of a conductive or semiconductive material, such that the support layer 104 including the thin shoulder 104a provides a mechanical and electrical connection to the suspension element 108 without the need for separate wiring. In embodiments of the present invention, one or more trenches 600 are etched or otherwise retained in the support layer 104 to provide electrically isolated localized areas on the support layer 104 surrounding the suspended element 108.

As indicated by the arrows in fig. 6A, the first wafer W1 and the second wafer W2 may then be bonded together using fusion wafer bonding or plasma activated wafer bonding. In the example shown, the inner side or surface of the first wafer W1 and the inner side or surface of the second wafer W2 are bonded together to form the detector chip 20 as shown in fig. 4B. The inner surface of the support layer 104 may be bonded to the inner surface of the second sacrificial layer 601.

The sacrificial layer 102 may be removed from at least the location of the suspended active element 108 to release the active element 108 before the complete wafer-level manufacturing process is finished (e.g., before the vacuum sealing layer 605 is deposited as described below). The first vacuum-tight chamber 110 and the second vacuum-tight chamber (opening (recess) 106) may be in fluid communication through or around the suspended active element 108. Thereby, the sacrificial layer 102 may be etched from the backside of the detector chip and by one process the active element 108 is released and the first vacuum-tight cavity 110 and the second vacuum-tight cavity (opening (recess) 106) are formed. A release hole is etched in the backside of the second wafer W2 to release the etching of the active element 108.

In an embodiment of the present invention, the electrical connection 114 includes a Through Substrate Via (TSV)606 etched to extend from the outer surface of the second substrate 116 to the inner surface of the second sacrificial layer 601. Preferably, the substrate via 605 has a substantially constant diameter throughout the length of the substrate via. When high resolution is required, the diameter of the TSV must be small. The ratio of the diameter to the length of the substrate via is preferably about 1:10, which means that the second substrate 116 must also be very thin. When processing the second wafer W2, the second substrate 116 needs to be thicker before wafer bonding and the second substrate 116 is thinned after wafer bonding to obtain the small thickness required for small pixel (high resolution) applications.

In an embodiment, the substrate vias 606 may be filled with a conductive material, e.g., deposited thereon, to provide electrical connections to the conductive support layer 104 or to electrical lines disposed in the support layer 104. In addition, a conductive layer 607 may be deposited on the outside or backside of the second wafer W2. Furthermore, a vacuum sealing layer 605 may be deposited on the outer side or back side of the second wafer W2, for example on the conductive layer 607. For example, the vacuum sealing layer 605 may be locally deposited to seal the release hole.

In an embodiment of the invention, a third trench 604 is etched into the second sacrificial layer 601 from the backside in the second wafer W2 to electrically isolate the connection region (e.g. the substrate via 606) of the second wafer W2 from the rest of the second wafer W2.

In an embodiment of the invention, second trenches 602 are etched into the second vacuum-tight cavity (opening (recess) 106) in the second wafer W2 from the backside or the vacuum-tight layer 105 to electrically isolate the connection regions (e.g. through-substrate vias) of the second wafer W2 from each other and/or to electrically isolate the connection regions (e.g. through-substrate vias) of the second wafer W2 from the portion of the second substrate 116 supporting the back reflector 112.

In an embodiment of the present invention, in the conductive third layer 406 and optionally the vacuum sealing conductive layer (conductive layer 607), fourth trenches 608 are provided, for example by etching, to provide electrical isolation of the connection regions of the second wafer W2, for example the substrate vias 606, from each other.

In an embodiment of the present invention, the detector chip 20 may be flip chip bonded to the readout integrated circuit ROIC 118. In the example of fig. 6C, flip-chip bonding bumps 610 with a seed layer are provided between the connection regions (substrate vias 606, conductive layer 607) of the second wafer W2 and the readout integrated circuits 118.

In an embodiment, for example as shown in fig. 7, the rear reflector 112 may be located on the back side of the second wafer W2. The hanging detector 20 of fig. 6C and 7 have similar structure to each other except for the placement of the back reflector 112.

In the example shown herein, the back reflector 112 is a back mirror. However, it should be understood that the back reflector 112 may be implemented in a variety of different configurations. Examples of back reflectors may include one or more of the following: a rear mirror, a metallic rear mirror, a distributed Bragg reflector, a controllably movable rear mirror, a Fabry-Perot interferometer, an adjustable Fabry-Perot interferometer.

The rear reflector may be made of a variety of materials or combinations thereof. For example, the rear mirror may be a metal rear mirror. For example, the metal mirror may be made of titanium nitride (TiN), aluminum (Al), silver (Ag), tungsten (W), titanium (Ti), titanium Tungsten (TiW), or molybdenum (Mo). The metal mirror may be protected by a protective layer such as alumina Al2O3, silica SiO2, or silicon nitrate SiNx. The rear mirror may also be made of a heavily doped semiconductor material, such as monocrystalline or polycrystalline silicon.

Fig. 8A, 8B and 8C illustrate schematic diagrams of exemplary suspended detectors illustrating some basic principles according to an aspect of the present invention, wherein the second rear reflector 812 is a distributed bragg reflector DBR.

The first wafer W1 shown in FIGS. 8A, 8B, and 8C is similar to the first wafer W1 shown in FIGS. 6A, 6B, and 6C. In the example of fig. 8A-8C, a second sacrificial layer 601 of dielectric is deposited on the inside of the support layer 104 on the first wafer W1 instead of on the inside of the second substrate 116. The second sacrificial layer 601 of dielectric may also initially extend along the inner surface of the opening (recess) 106 to the suspended thermal element 108.

The second wafer W2 shown in fig. 8A, 8B, and 8C is similar to the second wafer W2 shown in fig. 6A, 6B, and 6C, except for the type of back reflector. The DBR (second rear reflector 812) may be disposed in the recess 800 of the substrate to secure a sufficient space for the second vacuum sealed cavity (opening (groove) 106) when the first and second wafers W1 and W2 are bonded together.

The distributed bragg reflector DBR (second rear reflector 812) may include stacked alternating layers of opposite refractive index (low index material and high index material). Preferably the thickness of each film or layer is one quarter of the target wavelength lambda. Examples of suitable materials for the IR wavelength include Si, Ge, CdTe, ZnSe, and ZnS. The DBR (second rear reflector) 812 may be deposited on the inner surface of the second wafer W2 in a pre-fabrication process or at an appropriate stage in the manufacturing process.

In the exemplary embodiment shown in fig. 8A-8C, the back reflector is a multiple air distributed bragg reflector (second back reflector 812) with a multilayer structure of alternating polysilicon layers 805 and air gaps 804. Initially, as shown in fig. 8A and 8B, the DBR (second rear reflector 812) may include alternating polysilicon layers 805 and a third sacrificial layer 802. The third sacrificial layer 802 supports and protects the bragg reflector structure during fabrication. The third sacrificial layer 802 is removed to release the multi-air distributed bragg reflector (second back reflector 812) before the complete wafer level manufacturing process is finished, for example before depositing the vacuum sealing layer 605. The first vacuum-tight chamber 110 and the second vacuum-tight chamber (opening (recess) 106) may be in fluid communication through or around the suspended active element 108. Thus, the sacrificial layer 102 may be etched from the back side of the detector chip, and the releasing of the active element 108, the releasing of the multi-air distributed bragg reflector (second back reflector 812), and the forming of the first vacuum-sealed cavity 110 and the second vacuum-sealed cavity (opening (groove) 106) may be accomplished by one process. If there is a portion of the third sacrificial layer 601 extending to the second vacuum-tight chamber (opening (groove) 106), this portion can also be removed at the same time. Release holes may be etched in the backside of the second wafer W2 to release the etching of the active elements 108 and the bragg reflector (second back reflector 812).

In an embodiment of the present invention, the electrical connection 114 includes a Through Substrate Via (TSV)606 etched from an outer surface of the second substrate 116 to an inner surface of the support layer 104. In an embodiment, the substrate vias 606 may be filled with a conductive material, for example, a conductive material may be deposited on the substrate vias to provide electrical connections to the conductive support layer 104 or to electrical lines disposed within the support layer 104. Further, a conductive layer 607 may be deposited on the outer side or backside of the second wafer W2. Furthermore, a vacuum sealing layer 605 may be deposited on the outer side or the backside of the second wafer W2, for example on the conductive layer 607. For example, the vacuum sealing layer 605 may be locally deposited to seal the release hole. One or more trenches (second trench 602, third trench 604 and fourth trench 608) may be etched in the backside of the second wafer W2 to provide electrical isolation between the connection regions (e.g., substrate via 606) of the second wafer W2 and the rest of the second wafer W2, between the connection regions (e.g., substrate via 606) of the second wafer W2, and/or between the connection regions (e.g., substrate via 606) of the second wafer W2 and the second back reflector 812. The detector chip 20 may be flip-chip connected to a readout integrated circuit 118. In the example of fig. 80C, flip-chip bonding bumps 610 with a seed layer are provided between the connection regions (substrate via 606, conductive layer 607) of the second wafer W2 and the readout integrated circuits 118.

Fig. 9A, 9B and 9C show schematic diagrams of providing an exemplary suspended probe 20 according to an aspect of the present invention using thermocompression bonding or other metal-based wafer bonding. Thermocompression bonding is a wafer bonding technique in which two specific materials (usually metals) are present on the wafer surfaces to be bonded, and force and heat are simultaneously applied to the two specific materials to achieve atomic contact. Diffusion requires atomic contact between surfaces due to atomic motion. Atoms migrate from one lattice to another according to lattice vibrations. This atomic interaction bonds the interfaces together. Examples of suitable materials for the thermocompression bonding method include gold/gold (Au/Au), copper/copper (Cu/Cu), aluminum/aluminum (Al/Al), silver/silicon (Au/Si), and copper/tin (Cu/Sn). In silver/silicon (Au/Si) bonding, the silicon material may be a silicon substrate or a polysilicon substrate itself.

The first wafer W1 may include a dielectric or semiconductor first substrate 100, a wafer-wide or partially patterned dielectric sacrificial layer 102 deposited on the inside of the first substrate 100, a dielectric or semiconductor support layer 104 deposited on the inside of the dielectric sacrificial layer 102 or on the first substrate, a suspended active thermal element 108 disposed within an opening (recess) 106 of the support layer 104. As schematically shown in FIG. 9A, the suspended thermal element 108 may initially be positioned on top of the sacrificial layer 102, which supports and protects the suspended thermal element 108 during the manufacturing process.

The second wafer W2 may include a dielectric or semiconductor second substrate 116, a back reflector 112 disposed inside the second substrate 116, and an insulating layer 901 (e.g., SiO2) deposited inside the second substrate 116. The insulating layer 901 may provide electrical insulation between the first wafer W1 and the second wafer W2. Alternatively, an insulating layer is provided on the inner side of the support layer 104 on the first wafer W1 in place of or in addition to the insulating layer 901 on the second wafer W2. Alternatively, electrical isolation may be achieved by appropriately positioned trenches or a combination of trenches and an insulating layer.

A patterned bonding material layer of a first bonding material may be disposed on the inner surface of the first wafer W1, and a corresponding patterned bonding material layer of a second bonding material may be disposed on the inner surface of the first wafer W1. For example, a first plurality of metal bonding bumps or pads or leads (first wafer first bump 902A, first wafer second bump 903A) may be disposed on an inner surface of the first wafer W1, and a second, matching plurality of metal bonding bumps or pads or leads (second wafer first bump 902B, second wafer second bump 903B) may be disposed on an inner surface of the second wafer W2. The patterned bonding material layers in the example embodiments shown in fig. 9A-9C have different materials, but the bonding material layers may have the same material. Examples of suitable bonding material pairs are given above.

In an embodiment of the invention, the support layer 104 further comprises a thin shoulder 104a at the periphery of the opening (groove) 106 for mechanical and optionally electrical connection of the suspended active element 108. Preferably, the thin shoulder 104a may be offset from the inner surface of the first wafer W1, and more preferably, the thin shoulder 104a may be deposited on the sacrificial layer 102 at the bottom of the opening (groove) 106.

In embodiments of the present invention, the support layer 104 may be made of an electrically conductive material, such that the support layer 104 including the thin shoulder 104a may provide a mechanical and electrical connection to the suspension element 108 without the need for separate wiring. In embodiments of the present invention, one or more trenches 600 are etched or otherwise retained in the support layer 104 to provide electrically isolated localized areas on the support layer 104 surrounding the suspended element 108.

As indicated by the arrows in fig. 9A, the first and second wafers W1, W2 may then be bonded together using thermocompression bonding or other metal-based wafer bonding methods. In the example shown, the inner side or surface of the first wafer W1 and the inner side or surface of the second wafer W2 are bonded together to form a detector chip 20 as shown in fig. 9B. A patterned metal bonding layer, such as a metal bonding bump or pad or wire (first wafer first bump 902A, first wafer second bump 903A) on the inner surface of the first wafer W1 may be in common with a corresponding incident metal bonding bump or pad or wire (second wafer first bump 902B, second wafer second bump 903B) on the inner surface of the second wafer W2.

The sacrificial layer 102 may be removed at least from the location of the suspended active element 108 to release the active element 108 before the complete wafer-level manufacturing process is finished, e.g. before the vacuum sealing layer 605 is deposited. The first vacuum-tight chamber 110 and the second vacuum-tight chamber (opening (recess) 106) may be in fluid communication through or around the suspended active element 108. The sacrificial layer 102 can thus be etched from the backside of the detector chip and the release of the active element 108 and the formation of the first vacuum-tight cavity 110 and the second vacuum-tight cavity (opening (recess) 106) can be done by one process. Release holes, such as release holes 909, may be etched into the backside of the second wafer W2 to release the etching of the active elements 108.

In an embodiment of the present invention, the electrical connection 114 includes a second Through Substrate Via (TSV)906 etched from an outer surface of the second substrate 116 extending to an inner surface of the insulating layer 901 to contact a metal bonding bump (second wafer first bump 902B).

In an embodiment, an insulating coating is deposited over the second through substrate via 906 (TSV). In an embodiment, a second insulating layer 908 may be deposited on the back side of the second substrate 116.

In an embodiment, the second substrate via 906 may be filled with a conductive material, for example, a deposited conductive material, to provide an electrical connection with the patterned bonding metal layer, for example, with a bonding metal bump (second wafer first bump 902B), thereby being electrically connected with the conductive support layer 104 or with a wire provided in the support layer 104. Further, a second conductive layer 907 may be deposited on the outer side or rear side of the second wafer W2, preferably on the second insulating layer 908. Furthermore, a vacuum sealing layer 605 may be deposited on the outer or backside of the second wafer W2, for example on the conductive layer 607. The vacuum sealing layer 605 may be locally deposited to seal the release holes, such as release hole 909.

In an embodiment of the present invention, the detector chip 20 may be flip-chip bonded to the readout integrated circuit 118. In the example of fig. 9C, flip chip bonding bumps 610 with a seed layer are provided between the connection regions (second substrate vias 906, second conductive layer 907) of the second wafer W2 and the readout integrated circuits 118.

In an embodiment, the rear reflector 112 may also be provided on the back side of the second wafer W2, for example in an embodiment using a thermocompression bonding or other metal based wafer bonding method, in a manner similar to that shown in figure 7. This detector chip 20 is similar to that shown in fig. 9A-9C, except for the arrangement of the back reflector 112.

In an embodiment, the back reflector may also be implemented by a distributed bragg reflector in embodiments using a thermocompression bonding process or other metal-based wafer bonding process, for example, in a manner similar to the distributed bragg reflector shown in fig. 8A-8C. This detector chip 20 is similar to the detector chip shown in fig. 9A-9C, except for the type of back reflector.

It should be understood that the schematic representation may not show various optional, alternative and preferred features and details that may be present in the detector, such as electrically insulating layers, vacuum sealing layers, protective layers, anti-reflection layers, adhesive layers, etc.

Fig. 10 illustrates a schematic diagram of another exemplary suspended probe 20 provided using a thermocompression bonding process or other metal-based wafer bonding process in accordance with an aspect of the present invention. This exemplary probe is similar to the probe shown in fig. 9C, with some modifications. A front optical device 120 including an anti-reflective coating having a single film 400 may be disposed on the front surface of the first wafer W1 to reduce reflection, and a wafer-wide or partially patterned anti-reflective coating 1001 may be disposed between the opposite side of the first substrate 100 and the first vacuum sealed chamber 110 to further reduce reflection. Furthermore, the support layer 104 may now be in the form of a conductive or semiconductor film having a thickness approximately equal to or even smaller than the thickness of the suspended active element 108. A vacuum chamber 1002 is defined by the patterned layer of bonding material, for example by metal bonding bumps, pads or wires (first wafer first bump 902A and second wafer first bump 902B), said vacuum chamber 1002 being disposed between said suspended active element 108 and said rear reflector 108.

FIG. 11 shows a schematic diagram of an exemplary suspended detector array comprising thermal detectors (two detectors are shown in FIG. 11) obtained using the thermal compression bonding method or other metal-based wafer bonding method of the present invention. The detector 20 in the array is similar to the detector shown in figure 9C with some modifications. A front optical device 120 including an anti-reflective coating having a single film 400 may be disposed on the front surface of the first wafer W1 to reduce reflection, and a wafer-wide or partially patterned anti-reflective coating 1001 may be disposed between the opposite side of the first substrate 100 and the first vacuum sealed chamber 110 to further reduce reflection.

Fig. 12 shows a schematic diagram of an exemplary suspended detector array comprising a plurality of thermal detectors (two detectors are shown in fig. 12) of the present invention using thermocompression bonding or other metal-based wafer bonding. The detector 20 of the array is similar to the detector shown in figure 10.

Fig. 13A and 13B show a schematic view of an exemplary suspended probe 20 provided using a fusion activated wafer bonding process or a plasma activated wafer bonding process in accordance with an aspect of the present invention. The wafer level integrated heat detector 20 includes a first wafer W1 and a second wafer W2 bonded together. However, in the present exemplary embodiment, the second wafer W2 forms the front side of the detector through which radiation enters the detector. The second wafer W2 may include a dielectric or semiconductor second substrate 116 and, optionally, a dielectric second sacrificial layer 601. The second wafer W2 may also include front optics 120, for example, in a similar manner to the first wafer W1 described in the exemplary embodiments above. The first wafer W1 includes a first substrate 100 of dielectric or semiconductor, a sacrificial layer 102 of wafer-wide or partially patterned dielectric deposited on the first substrate 100, a support layer 104 of dielectric or semiconductor deposited on the sacrificial layer 102 of dielectric or on the sacrificial layer 102 of dielectric surrounding the partially patterned dielectric deposited on the first substrate 100, and a suspended active thermal element 108 disposed within an opening (recess) 106 of the support layer 104. As shown schematically in FIG. 13A, the suspended thermal element 108 is initially positioned on top of a wafer-wide or partially patterned sacrificial layer 102 that supports and protects the suspended thermal element 108 during the manufacturing process. The second sacrificial layer 601 may be used to facilitate or improve a subsequent fusion process, and/or to provide electrical insulation between the first wafer W1 and the second wafer W2. Alternatively, a corresponding sacrificial layer is provided on the first wafer W1 on the inner side of the support layer 104 instead of or in addition to the second sacrificial layer 601 on the second wafer W2.

The first wafer W1 further includes a rear reflector 112 prefabricated on the opposite or rear side of the first substrate 100. A back reflector 112 may also be provided on the opposite or back side of the first substrate 100 during fabrication of the detector. The material of the second substrate 116 may be transparent to radiation. In an embodiment, an opening may be provided in the second substrate 116 at the location of the back reflector 112 during manufacture of the probe 20.

As indicated by the arrows in fig. 13A, the first wafer W1 and the second wafer W2 may be bonded together using a melt activated wafer bonding method or a plasma activated wafer bonding method. In the example shown, the inner side or surface of the first wafer W1 and the inner side or surface of the second wafer W2 are bonded together to form a detector chip 20 as shown in fig. 13B. The inner surface of the support layer 104 may be bonded to the inner surface of the second sacrificial layer 601.

The sacrificial layer 102 may be removed at least from the location of the suspended active element 108 to release the active element 108 before the complete wafer-level manufacturing process is finished, e.g. before depositing the vacuum sealing layer 605. The portion of the sacrificial layer 102 removed at the suspended active element 108 also forms a first vacuum-tight cavity 110. The opening (recess) 106 of the support layer 104 is closed by the bonded second wafer W2, forming a second vacuum-tight chamber on the opposite side of the suspended active thermal element 108. The second vacuum-tight cavity (opening (groove) 106) may be enlarged by removing a portion of the second sacrificial layer 601. The first vacuum sealed cavity 110 and the second vacuum sealed cavity 106 may be in fluid communication through or around the suspended active element 108. Thereby, the first sacrificial layer 102 and the second sacrificial layer 106 are etched from the backside of the detector chip, and then the release of the active element 108 and the formation of the first vacuum-tight cavity 110 and the second vacuum-tight cavity (opening (groove) 106) are achieved by one process. Release holes may be etched in the backside of the second wafer W2 to release the etching of the active elements 108.

In an embodiment, the electrical connection may include a Through Substrate Via (TSV)606 etched to extend from an outer surface to an inner surface of the first substrate 100. Preferably the substrate via 605 has a substantially constant diameter over the length of the substrate via. When high resolution is required, the diameter of the substrate through-hole must be small. Preferably the ratio of the diameter to the length of the substrate via is about 1:10, which means that the first substrate 100 must also be very thin. When processing the second wafer W2, the second substrate 116 needs to be thicker before wafer bonding and the second substrate 116 is thinned after wafer bonding to obtain the small thickness required for small pixel (high resolution) applications.

In an embodiment, the substrate vias 606 may be filled with a conductive material, e.g., deposited with a conductive material, to provide electrical connections to the conductive support layer 104 or to electrical lines in the support layer 104. Furthermore, a conductive layer 607 may be deposited on the outer or backside of the first wafer W1. Furthermore, a vacuum sealing layer 605 may be deposited on the outer or backside of the first wafer W1, for example on the conductive layer 607. For example, the vacuum sealing layer 605 may be locally deposited to seal the trenches or release holes.

In an embodiment of the invention, a third trench 604 may be formed in the first wafer W1 etched from the back side into the sacrificial layer 102 to electrically isolate the connection region of the first wafer W1 (e.g., the substrate via 606) from the rest of the first wafer W1.

In an embodiment of the present invention, a second trench 602 is etched into the second vacuum-tight chamber (opening (recess) 106) from the backside or the vacuum-tight layer 105 in the second wafer W2 to electrically isolate the connection regions (e.g., through-substrate vias) of the second wafer W2 from each other and/or to electrically isolate the connection regions (e.g., through-substrate vias) of the second wafer W2 from the portion of the first substrate 100 supporting the back reflector 112.

In an embodiment of the present invention, the detector chip 20 may be flip chip bonded to the readout integrated circuit 118. In the example of fig. 13B, flip chip bonding bumps 610 with a seed layer are provided between the connection regions (substrate vias 606, conductive layers 607) of the first wafer W1 and the readout integrated circuits 118.

According to the present invention, a fabry-perot interferometer (FPI) is integrated with a thermal detector. A method of providing a fabry-perot interferometer in the front optic 120 is discussed in conjunction with figure 4F above.

In accordance with the present invention, a movable reflector of a fabry-perot interferometer (FPI) is provided under vacuum conditions within a wafer-level integrated thermal detector chip. A movable reflector, such as a movable mirror, provided in a vacuum may be moved and operated more quickly, so that a fabry-perot interferometer (FPI) may be adjusted more quickly.

Fig. 14A and 14B show schematic diagrams of an exemplary wafer-level integrated thermal detector 20 having a movable reflector of a fabry-perot interferometer (FPI) provided in a vacuum, in accordance with an aspect of the present invention. For example, in a manner similar to that described above for the exemplary embodiment without an FPI, the wafer level integrated heat detector 20 may include a first wafer W1 and a second wafer W2, the first wafer W1 and the second wafer W2 may be bonded by a fusion activated wafer bonding method or a plasma activated wafer bonding method or a metal compression bonding method or other metal based wafer bonding methods. It should be understood that the schematic representation may not show various optional, alternative and preferred features and details that may be present in the detector, such as electrically insulating layers, vacuum sealing layers, protective layers, anti-reflection layers, adhesive layers, etc. Examples of the above features are given in different embodiments herein. In fig. 14A and 14B, the front optics 120, in particular an anti-reflection layer (single film 400), is shown.

In the example of fig. 14A, a fabry-perot interferometer (FPI) includes a fixed reflector 1450 and a movable reflector 1452 and an intermediate vacuum chamber 1454. The movable reflector 1452 of the FPI is arranged on a vacuum-sealed cavity on the front side of the suspended active element 108 within the wafer-level integrated heat detector 20. A first vacuum sealed cavity 110 is provided between the moveable reflector 1452 and the suspended active element 108 of the FPI, separating the moveable reflector and the suspended active element from each other. In the wafer-level integrated heat detector 20, the fixed reflector 1450 of the FPI may be disposed at a front side of the movable reflector 1452 of the FPI, for example, at an inner side of the first substrate 100 of the first wafer W1. The intermediate vacuum cavity 1454 of the FPI is disposed between the fixed reflector 1450 of the FPI and the movable reflector of the FPI. The operation of the FPI is based on optical interference between the fixed reflector 1450 (mirror) and the movable reflector 1452, in an intermediate vacuum chamber 454 which forms an optical one-dimensional resonator. Incident radiation or light enters the resonator through the fixed reflector 1450 of the FPI, undergoes multiple reflections producing a resonance peak at the resonance wavelength of the resonator, and transmitted radiation or light leaks out of the resonator through the movable reflector 1452 of the FPI at the resonance wavelength (i.e., at the transmitted wavelength) to the first vacuum sealed cavity 110 to the suspended active element 108. To achieve incident signal coupling and transmitted signal rejection, the reflector (mirror) may be a semi-transparent reflector, not having 100% reflectivity but having limited transmissivity. The length L of the intermediate vacuum chamber 1454 of the FPI, i.e., the interval between the mirrors (the fixed reflector 1450 and the movable reflector 1452) of the FPI, is an integer of a half wavelength λ/2, i.e., L ═ m λ/2, where λ is a resonance wavelength and m is a positive integer. The first wafer W1 has a support structure for mechanical support of the moveable reflector 1452 of the FPI and the first wafer W1, and electrical connections for connecting tuning or driving signals from an external control source (e.g., external to the readout integrated circuit ROIC) to the moveable reflector 1452 of the FPI. The tuning or actuation signal controls the motion of the movable reflector 1452 of the FPI and controls the separation gap (the length L of the intermediate vacuum chamber 1454) between the fixed 1450 and movable reflector 1452 of the FPI, thereby controlling the spectral position of the transmission peak delivered to the suspended active element 108.

The suspended active element 108 may be disposed in an opening of the support layer 104 of the first wafer W1, and the suspended active element is electrically and mechanically connected to the support layer 104. With regard to the suspended active elements 108, the support layer 104 and the electrical and mechanical connections, for example the first wafer W1, may be realized in a similar manner as described in the above exemplary embodiment referring to a wafer-level integrated thermal detector 20 without FPI. Also, the movable reflector 1452 of the FPI may be mechanically and electrically connected to the support layer 104 or similar structure. However, the electrical connections of the suspended active element and the movable reflector 1452 of the FPI should be electrically isolated from each other.

The suspended thermal element 108 may initially be located on top of a wafer-wide or partially patterned sacrificial layer (not shown) deposited on the back of the movable reflector 1452 of the FPI, which supports and protects the suspended thermal element 108 and the movable reflector 1452 of the FPI during the manufacturing process. Similarly, the movable reflector 1452 of the FPI is initially located on top of a wafer-wide or partially patterned sacrificial layer (not shown) deposited on the backside of the fixed reflector 1450 of the FPI, which supports and protects the movable reflector 1452 of the FPI during fabrication. The sacrificial layer may be removed at least at the location of the suspended active element 108 before the complete wafer-level manufacturing process is finished (e.g. before final vacuum sealing) to release the active element 108 and optionally the movable reflector 1452 of the FPI. The first vacuum sealed cavity 110 may be provided in place of the removed portion of the sacrificial layer between the suspended active element 108 and the movable reflector 1452 of the FPI. Similarly, an intermediate vacuum cavity 1454 of the FPI may be provided instead of a removed portion of an artificial layer located between said movable reflector 1452 of the FPI and said fixed reflector 1450 of the FPI.

The second wafer W2 may include a dielectric or semiconductor second substrate 116 and a back reflector 112 positioned to reflect light back toward the suspended heat sensitive element 108. For example, the second wafer W2 may be implemented in a manner similar to that described in the above exemplary embodiment, which refers to a wafer-level integrated heat detector 20 without an FPI. In addition, there are electrical connections to the first wafer W1 for tuning or drive signals belonging to the movable reflector of the FPI from an external control source, for example a read-out integrated circuit ROIC.

For example, a detector chip 20 with an FPI may be flip-chip or otherwise connected to a read-out integrated circuit ROIC in a similar manner as described in the above exemplary embodiment, which refers to a detector chip 20 without an FPI. However, the suspended active element 108 electrical connections and the electrical connections of the moveable reflector 1452 of the FPI should be electrically isolated from each other.

In the example of fig. 14B, within the wafer-level integrated thermal detector 20, a fixed reflector 1450 of a fabry-perot interferometer (FPI) may be disposed in the first vacuum-sealed cavity 110 on the front side of the suspended active element 108, for example inside the first substrate 100 of the first wafer W1. In the wafer-level integrated thermal detector 20, a movable reflector 1452 of a fabry-perot interferometer (FPI) may be disposed in the second vacuum-sealed cavity (opening (groove) 106), which is located at the back side of the suspended active element 108, for example, at the inner side of the second wafer W2. The first vacuum-tight chamber 110 and the second vacuum-tight chamber (opening (recess) 106) together form a vacuum resonant cavity 1054 for the FPI. It can also be said that the suspended active element 108 is arranged in a vacuum cavity 1054 of the FPI, which is formed within the wafer level integrated thermal detector, between said fixed reflector 1450 of the FPI and said movable reflector 1452 of the FPI. The movable reflector 1452 of the FPI may also serve as the back reflector 112 of the suspended active element 108, and an additional back reflector may be omitted. Further, an additional vacuum chamber 106b may be disposed at a rear surface of the movable reflector 1452 of the FPI, for example, between the movable reflector 1452 of the FPI and the second substrate 116 of the second wafer W2.

The operation of the FPI is based on optical interference between the fixed reflector 1450 (mirror) and the movable reflector 1452, which are located in an intermediate vacuum cavity 1454 (the first and second hermetically sealed cavities 110, 106 (opening (recess)) forming an optical one-dimensional resonator. Incident radiation or light enters the resonator through the fixed reflector 1450 of the FPI, undergoes multiple reflections and produces a resonant peak of radiation or a resonant peak of light at the resonant wavelength of the resonator. The length L of the intermediate vacuum chamber 1454 of the FPI, i.e., the interval between the fixed reflector 1450 and the movable reflector 1452 of the FPI, is an integer multiple of a half wavelength λ/2, i.e., L ═ m λ/2, where λ is the resonance wavelength and m is a positive integer. Since the suspended active element 108 is disposed within the vacuum cavity 1054 of the FPI between the fixed reflector 1450 of the FPI and the movable reflector 1452 of the FPI, the suspended active element 108 will detect radiation or light at resonant wavelengths. The suspended active element 108 will absorb a portion of the radiant energy, but the resonance will be maintained when the losses in the intermediate vacuum cavity 1454 are less than the radiant energy entering the vacuum cavity 1454. In order to couple the incident signal into the intermediate vacuum chamber 1454, the fixed reflector 1450 (mirror) of the FPI is a semi-transparent reflector that does not have 100% reflectivity but has limited transmittance. The movable reflector 1452 of the FPI is an opaque reflector having a reflectivity of about 100% because the movable reflector does not need to transmit a signal and energy loss in the movable reflector of the FPI can be minimized.

In addition to the fixed reflector 1450 of the FPI, the first wafer W1 may be implemented as described in the above embodiments referring to the wafer-level integrated heat detector 20 without an FPI, for example. The suspended active element 108 is arranged at an opening (recess) 106 of a dielectric or semiconducting support layer 104, the support layer 104 being a support layer of the first wafer W1, and the active element being mechanically and electrically connected to the support layer 104. The suspended thermal element 108 is initially positioned on top of a wafer-wide or partially patterned sacrificial layer (not shown) deposited on the back of the fixed reflector 1450 of the FPI, which supports and protects the suspended thermal element 108 during manufacturing. The first vacuum sealed cavity 110 may be provided in place of the removed portion of the sacrificial layer between the suspended active element 108 and the fixed reflector 1450 of the FPI.

The second wafer W2 may include a dielectric or semiconductor second substrate 116 and the movable reflector 1452 of the FPI. The movable reflector 1452 of the FPI may be electrically and mechanically connected to a support structure (not shown) located at an inner side of the second wafer W2, so that the additional vacuum chamber 106b is disposed at a rear surface of the movable reflector of the FPI. The movable reflector 1452 of the FPI is initially located on top of a wafer-wide or locally patterned sacrificial layer (not shown) deposited on the back side of the substrate, which supports and protects the movable reflector 1452 of the FPI during fabrication. Before the complete wafer-level manufacturing process is finished, e.g. before final vacuum sealing, the sacrificial layer may be removed at least at the location of the movable reflector 1452 to release the movable reflector 1452 of the FPI, preferably simultaneously with the release of the suspended active element 108. An additional vacuum chamber 106b may be provided instead of the removed part of the sacrificial layer between the movable reflector 1452 of the FPI and the second substrate 116. The movable reflector 1452 of the FPI can also be used as the back reflector 112 of the suspended active element 108, and an additional back reflector can be omitted. When the movable reflector 1452 of the FPI is substituted for the rear reflector, for example, the second wafer W2 may be disposed in a substantially similar manner as described in the above exemplary embodiment referring to the wafer-level integrated thermal detector 20 without the FPI. For example, electrical connections may be provided in a similar manner through the second wafer W2 from the suspended active element 108 to external circuitry such as a read-out integrated circuit ROIC. In addition, an electrical connection may be provided for connecting a tuning signal or a driving signal belonging to said movable reflector 1452 of the FPI, coming for example from an external control source of the read-out integrated circuit ROIC. The electrical connections of the suspended active element 108 and the electrical connections of the movable reflector 1452 of the FPI should be electrically isolated from each other.

The detector chip 20 with the FPI may be flip-chip or otherwise bonded to the read-out integrated circuit ROIC in a similar manner as described in the above embodiments, which refer to the detector chip 20 without the FPI. The electrical connection of the suspended active element 108 and the electrical connection of the movable reflector 1452 of the FPI should be electrically isolated from each other.

Fig. 15 shows a more detailed schematic of an exemplary suspended detector 20 obtained using a fusion activated wafer bonding process or a plasma activated wafer bonding process according to one aspect of fig. 14B.

In fig. 15, the first wafer W1 and the second wafer W2 are attached and bonded together. The first wafer W1 comprises a dielectric or semiconductor first substrate 100, a semi-transparent FPI fixed reflector 1450 (mirror) disposed inside the first substrate 100, a wafer-wide or partially patterned sacrificial layer 102 of dielectric deposited on the first substrate 100 (preferably the sacrificial layer is initially deposited inside the fixed reflector 1450 of FPI), a dielectric or semiconductor support layer deposited on the inside of the sacrificial layer 102 of dielectric or on the first substrate 100, a suspended active thermal element 108 disposed within an opening (recess) 106 of the support layer 104. The suspended thermal element 108 is initially located on top of a wafer-wide or partially patterned sacrificial layer 102 that supports and protects the suspended active element 108 during the fabrication process. In an embodiment of the present invention, the support layer 104 further comprises a thin shoulder 104a provided on the periphery of the opening (groove) 106 for enabling mechanical and optionally electrical connection of the suspended active element 108. Preferably, the thin shoulder 104a may be offset from the inner surface of the first wafer W1, and more preferably, the thin shoulder 104a may be deposited on the sacrificial layer 102 at the bottom of the opening (groove) 106.

In an embodiment of the present invention, the support layer 104 is made of an electrically conductive material, such that the support layer 104 including the thin shoulder 104a may be mechanically and electrically connected to the suspension element 108 without the need for separate wiring. In embodiments of the present invention, one or more trenches 600 may be etched or otherwise retained in the support layer 104 to provide electrically isolated localized areas on the support layer 104 surrounding the suspended elements 108.

The second wafer W2 includes a dielectric or semiconductor second substrate 116 and a movable reflector 1452 (mirror) of FPI supported by the inside of the second substrate 116. In the exemplary embodiment shown in fig. 15, the movable reflector 1452 of the FPI is supported by conductive connection elements 1502 protruding inwardly from the inner side of the second substrate 116, thereby positioning an additional vacuum cavity 106b between the back surface of the movable reflector of the FPI and the inner side of the second substrate 116. The lower end of the connection element 1502 is connected to the second substrate 116, and the protruding free end of the connection element is provided to support the movable reflector 1452 of the FPI at the peripheral region. The movable reflector 1452 of the connecting element 1502 and/or the FPI is arranged to initially lie on top of a locally patterned sacrificial layer deposited on the back side of the second substrate, which supports and protects the connecting element 1502 and the movable reflector 1452 of the FPI during manufacturing. Before the complete wafer-level manufacturing process is finished, e.g. before final vacuum sealing, at least the sacrificial layer may be removed from the position of the movable reflector 1452 to release the movable reflector 1452 of the FPI, preferably simultaneously with the release of the suspended active element 108. An additional vacuum cavity 106b is provided instead of the removed part of the sacrificial layer between the movable reflector 1452 of the FPI and the second substrate 116. A portion of the third sacrificial layer 1506 may remain under the free end of the connecting element 1502 to strengthen the support structure. The conductive elements or layers or conductive wiring may be made of any conductive material, for example metal or other conductive material such as polysilicon. The connecting element 1502 can serve as a first electrode for movement or driving of the movable reflector 1452 of the FPI. In an embodiment, the driving comprises electrostatic driving. However, other types of drive may alternatively be used, for example using piezoelectric drive.

In the example shown, an additional connection layer 1504 for electrostatic actuation is deposited on the inside of the second substrate 116. Alternatively, if the second substrate 116 is made of a conductive material or a semiconductor material (e.g., polysilicon), the second substrate 116 may serve as a lower electrode for electrostatic driving. Optionally, a second sacrificial layer 601 of dielectric may be deposited on the inner side of the second substrate 116 to facilitate or improve the subsequent fusion process and/or to provide electrical insulation between the first wafer W1 and the second wafer W2. Alternatively, a corresponding sacrificial layer is disposed on the first wafer W1 on the inner side of the support layer 104, instead of or in addition to the second sacrificial layer 601 on the second wafer W2.

The first wafer W1 and the second wafer W2 may be bonded together using a fusion activated wafer bonding method or a plasma activated wafer bonding method to form the detector chip 20. The inner surface of the support layer 104 may be bonded to the inner surface of the second sacrificial layer 601. The first and second vacuum-tight cavities (openings (recesses) 106) 110 and the optional additional vacuum cavity 106b may be in fluid communication through or around the suspended active element 108 and optionally through or around the movable reflector 1502 of the FPI. Thus, the sacrificial layer 102 and the movable reflector 1502 of the optional FPI can be etched from the backside of the detector chip, thereby completing the demonstration of the active element 108 and the formation of the first vacuum-tight cavity 110, the formation of the second vacuum-tight cavity (opening (recess) 106) and optionally the formation of the additional vacuum cavity 106b by one process. A release hole (fourth trench 608) may be etched in the backside of the second wafer W2 to release the etching of the active device 108. Further, a vacuum sealing layer 605 is deposited on the outer or backside of the second wafer W2. For example, the vacuum sealing layer 605 may be locally deposited to seal the release hole (fourth groove 608).

In an embodiment of the present invention, the electrical connections connecting the suspended active elements 108 include Through Substrate Vias (TSVs) 606 etched extending from the outer surface of the second substrate 116 to the inner surface of the second sacrificial layer 601. A fourth through-substrate via 1509 is provided for the connection element 1502 (as driving electrode) and a third through-substrate via 1508 is provided for the additional connection layer 1504 (as driving electrode), respectively. Preferably the dimensions of the substrate via are similar to those described above for the embodiment without the FPI. In embodiments, the substrate vias may be filled with a conductive material, e.g. deposited, to provide electrical connections to the conductive support layer 104 or to the connection elements 1502 and the additional connection layer 1504 provided in the support layer 104. In addition, a conductive layer 607 may be deposited on the outside or back side of the second wafer W2.

In an embodiment, a third trench 604 is etched in the second wafer W2 from the backside to the second sacrificial layer 601 to electrically isolate the connection region (e.g. the substrate via 606) of the second wafer W2 from the rest of the second wafer W2.

In an embodiment, a fifth trench 1510 is etched into the second sacrificial layer 601 from the backside in the second wafer W2 to electrically isolate the connection areas (e.g. through substrate via 606) of the suspended active element 108 from the connection areas (e.g. third through substrate via 1508, fourth through substrate via 1509) of the driving electrodes (connection element 1502 and additional connection layer 1502).

In an embodiment, second trenches 602 are etched into the additional vacuum chambers 106b from the backside in the second wafer W2 to electrically isolate the connection areas (e.g., the third through substrate via 1508 and the fourth through substrate via 1509) of the driving electrodes (the connection elements 1502 and the additional connection layers 1502) from each other.

The detector chip 20 with FPI may be flip-chip or otherwise connected with a readout integrated circuit ROIC. In the example of fig. 15, flip-chip bonding bumps 610 with a seed layer are provided between the connection areas (substrate vias 606, conductive layer 607) of the second wafer W2 and the read-out integrated circuits 118 for connecting the suspended active elements 108. Similarly, flip-chip second and

third bonding bumps

1512, 1514 are provided between the connection regions (third and fourth through-substrate vias 1508, 1509) of the second wafer W2 and the readout integrated circuits 118 to connect the driving electrodes (connecting elements 1502 and additional connecting layers 1504), respectively.

In electrostatic driving of the movable reflector 1452 of the FPI, a driving potential difference is connected between the driving electrodes (between the connecting element 1502 and the additional connecting layer 1504). For example, an electrostatic pull applied through a potential difference may cause the movable reflector of an FPI to be closer to the second substrate 116 and farther from the fixed reflector 1502 of an FPI. The FPI gap increases and the spectral position of the formants shifts to longer wavelengths. An electrostatic pull applied by a potential difference moves the movable reflector 1504 of the FPI away from the second substrate 116 and toward the fixed reflector 1502 of the FPI. The FPI gap shrinks and the spectral position of the formants shifts to shorter wavelengths.

Fig. 16 shows a more detailed schematic of an exemplary suspended detector 20 resulting from the use of thermocompression bonding or other metal-based wafer bonding in accordance with the present invention of fig. 14B.

The first wafer W1 is substantially similar to the first wafer described above with reference to fig. 15, except that a patterned layer of bonding material of a first bonding material is provided on the inner surface of the first wafer W1, and a corresponding patterned layer of bonding material of a second bonding material is provided on the inner surface of the first wafer W1. For example, a first type of metallic bonding bump or pad or lead (first wafer first bump 902A, first wafer second bump 903A) may be provided on the inner surface of the first wafer W1, and a matching second type of metallic bonding bump or pad or lead (second wafer first bump 902B, second wafer second bump 903B) may be provided on the inner surface of wafer W2. In the exemplary embodiment shown in fig. 9A-9C, the patterned bonding material layers are shown as being made of different materials, but the two bonding material layers may be the same material. Examples of suitable bonding material pairs are given above with reference to fig. 9A-9C.

The second wafer W2 is substantially similar to the second wafer W2 described above with reference to fig. 15, except that an insulating layer 901 (e.g., SiO2) deposited on the inside of the second substrate 116 is different. The insulating layer 901 may provide electrical insulation between the first wafer W1 and the second wafer W2. Alternatively, an insulating layer is provided inside the support layer 104 on the first wafer W1 instead of or in addition to the insulating layer 901 on the second wafer W2. Alternatively, electrical insulation may be provided by appropriately positioned trenches or a combination of trenches and an insulating layer. The second wafer W2 includes a dielectric or semiconductor second substrate 116 and an FPI movable reflector 1452 (mirror) supported by the inside of the second substrate 116. In the exemplary embodiment shown in fig. 16, the movable reflector 1452 of the FPI is supported by electrically conductive connection elements 1502 protruding inwards from the inner side of the insulating layer 901, such that an additional vacuum cavity 106b is provided between the back surface of the movable reflector of the FPI and the inner side of the second substrate 116. The movable reflector 1452 of the connecting element 1502 and/or the FPI is arranged on top of a sacrificial layer, initially located locally patterned, deposited on the back side of the second substrate, which supports and protects the connecting element 1502 and the movable reflector 1452 of the FPI during manufacturing. Before the complete wafer-level manufacturing process is finished (e.g., before final vacuum sealing), at least the sacrificial layer may be removed from the position of the movable reflector 1452 to release the movable reflector 1452 of the FPI, preferably while simultaneously releasing the suspended active elements 108. An additional vacuum cavity 106b is provided instead of the removed part of the sacrificial layer between the movable reflector 1452 of the FPI and the second substrate 116. A portion of the third sacrificial layer 1506 may remain under the free end of the connecting element 1502 to strengthen the support structure. The conductive elements or layers or conductive wiring may be made of any conductive material, for example metal or other conductive material such as polysilicon. The connecting element 1502 can serve as a first electrode for movement or driving of the movable reflector 1452 of the FPI. In an embodiment, the driving comprises electrostatic driving. In the example shown, an additional connection layer 1504 for electrostatic actuation is deposited inside the second substrate 116 at the bottom of the additional vacuum chamber 106 b. Alternatively, if the second substrate 116 is made of a conductive material (e.g., polysilicon), the second substrate 116 may be used as a lower electrode for electrostatic driving.

The first wafer W1 and the second wafer W2 may be bonded together by thermocompression bonding or other metal-based wafer bonding methods. In the example shown, the layer of matching bonding material of the first wafer W1 facing the inner side or surface of the second wafer W2 and the layer of matching bonding material of the second wafer W2 facing the inner side or surface of the first wafer W1 are bonded together to form a detector chip 20.

In an embodiment of the present invention, the electrical connection to the suspended active element 108 includes a second substrate via 906 etched from an outer surface of the second substrate 116 extending to an inner surface of the insulating layer 901 to contact the bonding material pattern (second wafer first bump 902B). Similarly, a fourth through substrate via 1509 and a third through substrate via 1508 may be provided for the drive electrode (the connection element 1502 and the additional connection layer 1504), respectively. In an embodiment, an insulating coating is deposited on the second through substrate via 906, the third through substrate via 1508 and the fourth through substrate via 1509. In an embodiment, a second insulating layer 908 is deposited on the back side of the second substrate 116.

In an embodiment, the second through substrate via 906, the third through substrate via 1508 and the fourth through substrate via 1509 may be filled, e.g. deposited, with a conductive material to provide electrical connection to the patterned layer of bonding material (e.g. the second wafer first bump 902B) and to the respective drive electrode (the connection element 1502 and the additional connection layer 1504). Further, a second conductive layer 907 is deposited on the outer side or the back surface of the second wafer W2 at the positions of the second through substrate via 906, the third through substrate via 1508 and the fourth through substrate via 1509, preferably on the second insulating layer 908. Further, a vacuum sealing layer 605 is deposited on the outer side or back side of the second wafer W2, for example on the second insulating layer 908. The vacuum seal layer 605 may be locally deposited to seal the release holes (e.g., release holes 909).

For example, in a manner similar to the example in fig. 15, the detector chip 20 with FPI may be flip-chip or otherwise connected with the readout integrated circuit 118.

In an embodiment, a suspended detector array with an FPI is provided in a similar manner, e.g., as described above for a suspended detector array without an FPI.

In an embodiment of the present invention, at least one of the first wafer W1 and the second wafer W2 may include a prefabricated intermediate product including one or more of the fixed reflector of an FPI, the movable reflector of an FPI, the support structure of the movable reflector of an FPI, the suspended active device, the support structure of the suspended active device, and the sacrificial layer for supporting the suspended active device.

The invention and its embodiments are not limited to the examples described above but may vary within the scope of the claims.

Claims

1. A wafer level integrated thermal detector, comprising:

a first wafer and a second wafer, said first and second wafers being bonded together, wherein said first wafer comprises a substrate of dielectric or semiconductor, a wafer-wide or locally patterned sacrificial layer of dielectric deposited on said substrate, a support layer deposited on said sacrificial layer of dielectric or sacrificial layer of semiconductor or said substrate, a suspended active element, said suspended active element being arranged in an opening of said support layer,

a first vacuum-tight cavity and a second vacuum-tight cavity, which are arranged at opposite sides of the suspended active element, wherein the first vacuum-tight cavity extends into the sacrificial layer at the location of the suspended active element, and the second vacuum-tight cavity comprises an opening of the support layer, which opening is closed by the bonded second wafer,

front optics for externally entering radiation into one of the first and second vacuum-sealed cavities,

a rear reflector disposed to reflect radiation back to the other of the first and second vacuumed cavities, an

An electrical connection for connecting the suspended active element to a readout circuit.

2. The integrated heat detector of claim 1, wherein the first and second wafers are bonded using a fusion activated bonding process or a plasma activated bonding process or a thermocompression bonding process or other metal based wafer bonding process.

3. An integrated heat detector according to claim 1 or 2, characterized in that the electrical connections are arranged to be connected to a readout circuitry integrated on the third wafer, preferably by thermo-compression bonding or other metal-based bonding or die bonding.

4. The integrated thermal detector of any of claims 1 to 3, wherein the front optics comprise: a transparent substrate, a window in the substrate, an anti-reflection coating, a lens, a filter, a front mirror, a controllably movable front mirror, a fabry-perot interferometer, an adjustable fabry-perot interferometer.

5. The integrated heat detector of any of claims 1 to 4, wherein the rear reflector comprises: a rear mirror, a metallic rear mirror, a distributed Bragg reflector, a controllably movable rear mirror, a Fabry-Perot interferometer, an adjustable Fabry-Perot interferometer.

6. The integrated heat detector of any of claims 1 to 5, wherein the rear reflector is disposed on an inner side of the other of the first and second wafers, or on an outer side of the other of the first and second wafers, behind a transparent substrate or window, or in an opening of the other of the first and second wafers.

7. The integrated heat detector of any of claims 1 to 6, wherein the support layer further comprises a thin shoulder on the periphery of the opening for mechanical and electrical connection with the suspended active element, wherein preferably the thin shoulder is offset from the bonding surface of the first wafer.

8. The integrated heat detector of any of claims 1 to 7, wherein the rear reflector is disposed on an inner side of the other of the first and second wafers, or on an outer side of the other of the first and second wafers, behind a transparent substrate or window, or in an opening of the other of the first and second wafers.

9. The integrated thermal detector of any of claims 1 to 8, comprising a movable reflector of a fabry-perot interferometer provided in one of the first and second vacuum-sealed cavities, wherein a vacuum space is present on both sides of the movable reflector.

10. The integrated thermal detector chip of claim 9, wherein a fixed reflector of a fabry-perot interferometer and the movable reflector of a fabry-perot interferometer are both disposed in a same one of the first and second vacuum-sealed cavities, the fixed reflector of a fabry-perot interferometer and the movable reflector of a fabry-perot interferometer being located on a front side of the suspended active element.

11. The integrated heat detector of claim 9, wherein the movable reflector is disposed in one of the first and second vacuum-sealed cavities, the movable reflector being located on a backside of the suspended active element.

12. The integrated heat detector of claim 11, wherein the movable reflector is configured to act as the back reflector.

13. Integrated thermal detector according to claim 11 or 12, characterized in that the fixed reflector of a fabry-perot interferometer is arranged at the front side of the suspended active element.

14. An integrated heat detector according to any of claims 9 to 13, comprising a support structure for mechanically supporting the movable reflector within one of the first and second vacuum-tight cavities.

15. An integrated thermal detector according to any of claims 9 to 14, comprising electrical connections for connecting the movable reflector with a drive controller to adjust the fabry-perot interferometer.

16. The integrated heat detector of claim 15, wherein the electrical connection of the movable reflector comprises a pair of electrostatic drive electrodes.

17. An integrated thermal detector according to any of claims 1 to 16, wherein the thermal detector is arranged to absorb one of the following wavelength ranges of electromagnetic radiation: ultraviolet (UV) light, visible light, Infrared (IR) light, terahertz (THz) radiation, and visible light.

18. An integrated thermal detector array comprising a plurality of thermal detectors according to any of claims 1 to 17.

19. A pre-fabricated intermediate product for manufacturing an integrated thermal detector according to any of claims 1 to 17 or an integrated thermal detector array according to claim 18, comprising the first wafer pre-fabricated to comprise the substrate, the suspended active devices, the support layer and the sacrificial layer supporting the dielectric of the suspended active devices.

20. The pre-fabricated intermediate product of claim 19, wherein the first wafer is further pre-fabricated to include a fabry-perot interferometer, a fixed reflector of a fabry-perot interferometer or a movable reflector of a fabry-perot interferometer on an inner side of the first wafer.

21. A prefabricated intermediate product for manufacturing an integrated thermal detector according to any of claims 1 to 17 or an integrated thermal detector array according to claim 18, comprising said second wafer prefabricated to comprise on its inner side a substrate of a dielectric or a substrate of a semiconductor, and a movable reflector of a fabry-perot interferometer.