CN111354819A - Photoelectric integrated device and preparation method thereof - Google Patents
Photoelectric integrated device and preparation method thereof Download PDFInfo
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Abstract
The invention relates to a photoelectric integrated device and a preparation method thereof, wherein the preparation method comprises the following steps: selecting an n-type doped Si substrate; sequentially growing an n-type Ge-doped layer, a p-type Si-doped layer and a protective layer on a substrate; etching the protective layer, forming a light-emitting device region, a waveguide region and a detector region which are sequentially isolated by the p-type doped Si layer and the n-type doped Ge layer; depositing waveguide SiN films on the waveguide region and two sides of the waveguide region; depositing detector SiN films on the substrate, the detector area and two sides of the detector area; and forming electrodes on the light-emitting device area, the substrate and the detector SiN film to finish the preparation of the photoelectric integrated device. According to the embodiment of the invention, the Si-based modified Ge material is used, and the light-emitting device, the waveguide and the detector are integrated on the same layer to form the photoelectric integrated device, and the photoelectric integrated device is easy to be compatible in process between optical and electronic devices, novel in structure, high in integration level, low in production cost and short in process period.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a photoelectric integrated device and a preparation method thereof.
Background
The concept of photovoltaic integration has been proposed for over twenty years to date. With the development of optical communication, optical information processing, optical computing, optical display, and other disciplines, there is a strong interest in Optoelectronic integration with small size, light weight, stable and reliable operation, low power consumption, and high-speed operation, and together with the progress of material science and advanced manufacturing technology, it is possible to integrate optical, optical/electrical, and electronic components on a single structure or monolithic substrate, and to construct Optoelectronic Integrated circuits (OEICs) with single or multiple functions.
In the existing preparation process, various photon and electronic elements are integrated on the same substrate, and materials meeting the performance requirements of the two elements are selected. In order to make different materials complementary, according to the requirements making optimum combination, a composite substrate material is developed, i.e. utilizing heteroepitaxy technique, on a substrate material a film of another substrate material is epitaxial-grown, for example on the silicon chip a heteroepitaxial gallium arsenide monocrystal film is made, on the silicon surface of the substrate an electronic component is made, and on the gallium arsenide film a photonic component is made. However, the prepared optical and electronic devices are not compatible in structure, high in production cost and long in process period, and further development of the optical and electronic devices is restricted.
Therefore, it is very important to prepare an optoelectronic integrated device that is compatible between optical and electronic devices.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a photovoltaic integrated device and a method for manufacturing the same. The technical problem to be solved by the invention is realized by the following technical scheme:
the embodiment of the invention provides a preparation method of a photoelectric integrated device, which comprises the following steps:
selecting an n-type doped Si substrate;
sequentially growing an n-type doped Ge layer, a p-type doped Si layer and a protective layer on the substrate;
etching the protective layer, the p-type doped Si layer and the n-type doped Ge layer to form a light-emitting device region, a waveguide region and a detector region which are isolated in sequence;
depositing waveguide SiN films on the waveguide region and two sides of the waveguide region;
depositing detector SiN films on the substrate, the detector area and two sides of the detector area;
and forming electrodes on the light-emitting device region, the substrate and the detector SiN film to finish the preparation of the photoelectric integrated device.
In one embodiment of the present invention, sequentially growing an n-type doped Ge layer, a p-type doped Si layer, and a protective layer on the substrate comprises:
epitaxially growing the n-type Ge-doped layer on the substrate by using a CVD (chemical vapor deposition) process at a temperature of 310-330 ℃ and with a doping concentration of 1019cm-3；
Annealing the n-type Ge-doped layer at 850 ℃;
growing the p-type doped Si layer on the n-type doped Ge layer by using a CVD (chemical vapor deposition) process at the temperature of 275-325 ℃, wherein the doping concentration is 1020cm-3；
Depositing the protective layer on the p-type doped Si layer using an LPCVD process.
In an embodiment of the present invention, etching the protective layer, the p-type doped Si layer, and the n-type doped Ge layer to form a light emitting device region, a waveguide region, and a detector region, which are sequentially isolated, includes:
introducing HF to etch the protective layer and the p-type doped Si layer by using a dry etching process;
by using a dry etching process, HF to HNO with the concentration ratio of 1:2.5:10 is adopted3:CH3And etching the n-type Ge-doped layer to the substrate by COOH to form the light-emitting device region, the waveguide region and the detector region which are sequentially isolated.
In one embodiment of the invention, HF is introduced to etch the protective layer and the p-type doped Si layer by using a dry etching process;
by using a dry etching process, HF to HNO with the concentration ratio of 1:2.5:10 is adopted3:CH3The COOH continuously etches the n-type Ge-doped layer to the substrate to form the light-emitting device region, the etching region and the detector region which are sequentially isolated, wherein the etching region is arranged between the etching region and the light-emitting device region, and the etching region is arranged between the etching region and the detectorIsolation trenches are respectively arranged between the regions;
depositing an isolation layer in the isolation trench;
and adding a covering layer on the etching area to form the waveguide area, wherein the etching area, the isolation layer and the covering layer form the waveguide area.
In one embodiment of the invention, depositing a waveguide SiN film on and on both sides of said waveguide region comprises:
introducing SiH under a first preset condition4And NH3And depositing waveguide SiN films on the waveguide region and two sides by using a PECVD process.
In one embodiment of the present invention, the first preset condition includes: the reaction temperature is 400-450 ℃, the pressure is 500mTorr, the low-frequency power is 150W, and the SiH4And said NH3The gas flow ratio of (2).
In one embodiment of the invention, depositing a detector SiN film on the detector region and on the substrate comprises:
introducing the SiH under a second preset condition4And said NH3And depositing detector SiN films on the substrate, the detector area and two sides by using a PECVD process.
In one embodiment of the present invention, the second preset condition includes: the reaction temperature is 240-280 ℃, the pressure is 1500mTorr, the radio frequency power is 200W, and the SiH4And said NH3The gas flow ratio of (2) is 0.75.
In one embodiment of the invention, a metal contact is formed by vapor deposition of metal Al on the light emitting device region, on the substrate, and on the detector SiN film to a thickness of 10-20 nm.
In one embodiment of the present invention, a photovoltaic integrated device is prepared by the method described in the above embodiment.
Compared with the prior art, the invention has the beneficial effects that:
according to the invention, the Si-based modified Ge material is used, and the light-emitting device, the waveguide and the detector are integrated on the same layer to form the photoelectric integrated device, and the photoelectric integrated device has the advantages of easily compatible structure between the optical device and the electronic device, novel structure, high integration level, low production cost and short process period.
Drawings
Fig. 1 is a schematic flow chart of a method for manufacturing a photovoltaic integrated device according to an embodiment of the present invention;
fig. 2a to 2e, fig. 2g, fig. 2i, fig. 2k, fig. 2p, and fig. 2t are schematic process flow diagrams of a method for manufacturing a optoelectronic integrated device according to an embodiment of the present invention;
fig. 2f is a schematic top view of the optoelectronic integrated device prepared by the process corresponding to fig. 2e according to an embodiment of the present invention;
fig. 2h is a schematic top view of the optoelectronic integrated device prepared by the process corresponding to fig. 2g according to an embodiment of the present invention;
fig. 2j is a schematic top view of the optoelectronic integrated device prepared by the process corresponding to fig. 2i according to an embodiment of the present invention;
fig. 2l is a schematic top view of the optoelectronic integrated device prepared by the process corresponding to fig. 2k according to an embodiment of the present invention;
fig. 2m is a schematic diagram of a right-view structure of a waveguide SiN film wrapping a waveguide region according to an embodiment of the present invention;
FIG. 2n is a schematic diagram illustrating a right-view principle of generating intrinsic compressive stress in a waveguide SiN film according to an embodiment of the present invention;
FIG. 2o is a schematic top view of an embodiment of the present invention illustrating the principle of generating intrinsic compressive stress in a waveguide SiN film;
fig. 2q is a schematic top view of the optoelectronic integrated device prepared by the process corresponding to fig. 2p according to an embodiment of the present invention;
FIG. 2r is a schematic diagram of a right-view structure of a SiN film wrapped on a detector region and a substrate according to an embodiment of the present invention;
FIG. 2s is a schematic diagram illustrating a right-view principle of generating intrinsic tensile stress in a detector SiN film according to an embodiment of the present invention;
fig. 2u is a schematic top view of a optoelectronic integrated device manufactured by the process corresponding to fig. 2t according to an embodiment of the present invention;
FIG. 3 shows SiO films with different thicknesses according to an embodiment of the present invention2A transmission degree simulation schematic diagram of the isolation layer under different wavelengths;
FIG. 4 is a graph showing simulated transmittance of a device at different wavelengths without α -Si capping layer and with α -Si capping layer according to an embodiment of the present invention;
FIG. 5-1 is a schematic top view of a linear tapered transition waveguide region according to an embodiment of the present invention;
fig. 5-2 is a schematic top view of a convex tapered transition waveguide region according to an embodiment of the present invention;
fig. 5-3 are schematic top-view structural diagrams of concave tapered transition waveguide regions according to embodiments of the present invention;
FIG. 6-1 is a schematic diagram illustrating a simulation of the effect of different tapered transition waveguide regions on transmittance at different wavelengths according to an embodiment of the present invention;
fig. 6-2 is a schematic simulation diagram of the effect of different shapes of tapered transition waveguide lengths on transmittance under different wavelength conditions according to an embodiment of the present invention;
fig. 7 is a schematic front view of an optoelectronic integrated device according to an embodiment of the present invention.
In the figure, 001-substrate, 002-buried layer, 0021-light emitting device buried layer, 0022-waveguide buried layer, 0023-detector buried layer, 003-top layer, 0031-light emitting device top layer, 0032-detector top layer, 004-protective layer, 0041-light emitting device protective layer, 0042-detector protective layer, 005-isolation layer, 006-cover layer, 007-waveguide SiN film, 008-detector SiN film, 009-light emitting device electrode, 010-detector electrode.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Referring to fig. 1, fig. 1 is a schematic flow chart of a method for manufacturing a photovoltaic integrated device according to an embodiment of the present invention. As shown in fig. 1, a method for manufacturing a photovoltaic integrated device includes:
s1, selecting a substrate 001;
specifically, referring to fig. 2a, fig. 2a is a schematic front view of a optoelectronic integrated device according to an embodiment of the present invention.
Wherein, step S1 includes:
an n + doped Si material is selected as a substrate 001 material, and the thickness of the substrate 001 is 30-750 nm.
S2, sequentially growing a buried layer 002, a top layer 003 and a protective layer 004 on the substrate;
referring to fig. 2b-2d, fig. 2b-2d are schematic process flow diagrams of a method for manufacturing a optoelectronic integrated device according to an embodiment of the present invention.
Wherein, step S2 includes:
s21, epitaxially growing a buried layer 002 on the substrate 001 by CVD (Chemical Vapor Deposition) process at a temperature of 310-330 ℃;
referring to fig. 2b, the buried layer 002 is formed of n + doped Ge material, the thickness of the buried layer 002 is 1000nm, and the doping concentration is 1019～1020cm-3。
The CVD process is a method of forming a thin film by performing a chemical reaction on a substrate using one or more gas-phase compounds or simple substances containing thin film elements.
S22, annealing the buried layer 002 at 850 ℃ and introducing 0.2% tensile stress.
Wherein annealing the buried layer 002 can reduce the dislocation density of the buried layer 002. The dislocation density is the total length of dislocation lines contained in a unit volume of crystal, and the unit is 1/square centimeter, so that the dislocation density of the buried layer 002 is reduced, the strength and the temperature of the material can be reduced, and the ductility of the material can be improved.
S23, growing a top layer 003 on the buried layer 002 by a CVD process at the temperature of 275-325 ℃;
specifically referring to fig. 2c, a CVD process is used to grow a top layer 003 on the buried layer 002 at 275-325 ℃, the top layer 003 is formed of p + doped Si material, the top layer 003 has a thickness of 300nm and a doping concentration of 1020cm-3。
S24, depositing a protection layer 004 on the top layer 003 by LPCVD (Low Pressure Chemical Vapor Deposition), as shown in fig. 2 d.
Wherein, step S24 includes:
depositing a first Ti layer on the top layer 003 by an LPCVD process, wherein the thickness of the first Ti layer is 300 nm;
depositing an Al layer on the first Ti layer by using an LPCVD (low pressure chemical vapor deposition) process, wherein the thickness of the Al layer is 300 nm;
and depositing a second Ti layer on the Al layer by an LPCVD process, wherein the thickness of the second Ti layer is 300 nm.
The basic principle of the LPCVD process is to activate one or more gaseous substances with heat energy under a relatively low pressure to cause thermal decomposition or chemical reaction, and deposit the substances on the surface of a material to form a desired thin film.
S3, an etching protective layer 004, a top layer 003 and a buried layer 002 form a light-emitting device region, a waveguide region and a detector region which are sequentially isolated;
specifically, referring to fig. 2e and fig. 2f, fig. 2e is a schematic process flow diagram of a method for manufacturing a optoelectronic integrated device according to an embodiment of the present invention, and fig. 2f is a schematic top view structure diagram of the optoelectronic integrated device manufactured by the process corresponding to fig. 2g according to the embodiment of the present invention.
Wherein, step S3 includes:
s31, introducing an HF etching protective layer 004 and a top layer 003 by using a dry etching process;
the dry etching refers to a technique of performing thin film etching using plasma.
S32, dry etching process is adopted, and HF: HNO with concentration ratio of 1:2.5:10 is adopted3:CH3And etching the buried layer 002 to the substrate 001 by COOH to form a light-emitting device region, a waveguide region and a detector region which are sequentially isolated.
Wherein the light emitting device region includes: a light emitting device buried layer 0021, a light emitting device top layer 0031, and a light emitting device protective layer 0041; the waveguide region comprises a waveguide buried layer 0022, and the thickness of the waveguide buried layer 0022 is 160-200 nm; the detector region includes: a detector buried layer 0023, a detector top layer 0032 and a detector protective layer 0042.
Here, the light emitting device is a laser.
In addition, step S3 may further include:
s31, introducing an HF etching protective layer 004 and a top layer 003 by using a dry etching process;
s32, dry etching process is adopted, and HF: HNO with concentration ratio of 1:2.5:10 is adopted3:CH3And continuously etching the buried layer 002 to the substrate 001 by COOH to form a light-emitting device region, an etching region and a detector region which are sequentially isolated, wherein isolation grooves are respectively arranged between the etching region and the light-emitting device region and between the etching region and the detector region.
Wherein the etched region includes the buried waveguide layer 0022.
S33, depositing SiO in the isolation trench2An isolation layer 005 having a thickness of 20nm to 50nm, preferably 20 nm;
specifically, referring to fig. 2g and fig. 2h, fig. 2g is a schematic process flow diagram of a method for manufacturing a optoelectronic integrated device according to an embodiment of the present invention, and fig. 2h is a schematic top view structure diagram of the optoelectronic integrated device manufactured by the process corresponding to fig. 2g according to the embodiment of the present invention.
Wherein, SiO2The isolation layer 005 isolates the light-emitting device region from the etching region and isolates the etching region from the detector region, so that the electrical isolation effect is achieved, and the photoelectric devices at two ends are prevented from generating parasitic effect.
FIG. 3 shows SiO films with different thicknesses according to an embodiment of the present invention2The transmittance of the isolation layer 005 is simulated schematically at different wavelengths, and as shown in fig. 3, the longer the wavelength, the less the influence of the interface; SiO of substantially 20nm thickness2The influence of the isolation layer 005 on the optical transmission is substantially the same as that in the absence of the isolation layer, and the influence on the whole optical transmission is very small and can be substantially ignored; when SiO is present2The transmittance is gradually decreased as the spacer 005 is gradually thickened, and the transmittance is more decreased as the thickness is increased.
The above conclusion is due to the fact that SiO increases with thickness2The greater scattering loss and reflection of the spacer layer 005 results in an increase in coupling loss. The wavelength is at 1.About 75 μm, no SiO2Barrier layer 005 and has SiO2005 and SiO spacer layer2The coupling efficiency between the device with the isolating layer 005 having the thickness of 20nm and the waveguide is 84% -85% basically, and the coupling efficiency between the SiO layer and the waveguide is 84% -85%2The coupling efficiency of the spacer layer 005 having a thickness of 50nm is substantially 81-82%. This indicates that SiO2The effect of the spacer layer 005 on the loss between the device and the waveguide is not negligible.
S34, a cladding layer 006 is added to the etched region, and the etched region, the spacer layer 005 and the cladding layer 006 form a waveguide region.
Referring to fig. 2i and fig. 2j specifically, fig. 2i is a schematic process flow diagram of a method for manufacturing a optoelectronic integrated device according to an embodiment of the present invention, and fig. 2j is a schematic top view structure diagram of the optoelectronic integrated device manufactured by the process corresponding to fig. 2i according to the embodiment of the present invention.
Further, a α -Si cap 006 is added on the etched region, wherein the α -Si cap 006 is 800-.
In addition, the waveguide region comprises a conical transition waveguide region and a rectangular waveguide region, and two sides of the conical transition waveguide region can be in different shapes, such as a linear type, a convex type and a concave type. As shown in figure 5-1 of the drawings,
fig. 5-1 is a schematic top-view structure diagram of a linear tapered transition waveguide region provided in an embodiment of the present invention, as shown in fig. 5-2, fig. 5-2 is a schematic top-view structure diagram of a convex tapered transition waveguide region provided in an embodiment of the present invention, as shown in fig. 5-3, and fig. 5-3 is a schematic top-view structure diagram of a concave tapered transition waveguide region provided in an embodiment of the present invention. The longer the length of the tapered transition waveguide, the smaller the change size in the propagation direction, but the nonlinear increase, and the loss decreases less and less with the increase of the length, so the transmission loss of light is less affected.
Fig. 6-1 is a schematic diagram illustrating simulation of influence of different shapes of tapered transition waveguide regions on the projection degree under different wavelength conditions according to an embodiment of the present invention, where as shown in fig. 6-1, a concave transition waveguide increases transmission loss, and a convex transition waveguide is advantageous in fixed transition length transmission, and a longer transition wavelength is selected as much as possible under the permission of practical application.
Fig. 6-2 is a schematic diagram illustrating simulation of influence of different tapered transition waveguide lengths on transmittance under different wavelength conditions according to an embodiment of the present invention, as shown in fig. 6-2, a tapered transition waveguide length L ranges from 5 μm to 15 μm, and transmittance is the best when the tapered transition waveguide length L is 15 μm, but in a device design process, the tapered transition waveguide length L is not too long, and therefore the tapered transition waveguide length L is preferably 10 μm.
S4, depositing waveguide SiN films 007 on the waveguide region and the two sides; specifically, referring to fig. 2k and fig. 2l, fig. 2k is a schematic process flow diagram of a method for manufacturing a optoelectronic integrated device according to an embodiment of the present invention, and fig. 2l is a schematic top view structure diagram of the optoelectronic integrated device manufactured by the process corresponding to fig. 2k according to the embodiment of the present invention.
Wherein, step S4 includes:
s41, introducing SiH under the first preset condition4And NH3 Waveguide SiN films 007 with a thickness of 10-20nm are deposited on and on both sides of the waveguide region by PECVD (Plasma Enhanced chemical vapor Deposition).
The first preset condition includes: the reaction temperature is 400-450 ℃, the pressure is 500mTorr, the low-frequency power is 150W, and SiH4And NH3The gas flow ratio of (2).
The PECVD process is a process in which a gas containing atoms constituting a thin film is ionized by microwaves or radio frequencies to locally form a plasma, which has strong chemical activity and is easily reacted to deposit a desired thin film on a substrate. In order to allow the chemical reaction to proceed at a relatively low temperature, the activity of the plasma is utilized to promote the reaction.
Fig. 2m is a schematic diagram of a right-view structure of a waveguide SiN film wrapping a waveguide region according to an embodiment of the present invention, and fig. 2n and 2o are a schematic diagram of a right-view principle and a schematic diagram of a top-view principle of the waveguide SiN film according to an embodiment of the present invention, respectively, as shown in fig. 2n and 2o, a low-frequency power source is used to introduce high-energy particle bombardment to cause atoms or ions of the waveguide SiN film 007 to be bonded or redistributed, that is, the waveguide SiN film 007 becomes compressive and stretches or expands to generate intrinsic compressive stress on the waveguide.
The intrinsic stress is also called internal stress, and is generated in the film deposition growth environment (such as temperature, pressure, gas flow rate, etc.). If the film has a tendency to shrink along the film surface, the matrix generates tensile stress on the film, and conversely, the expansion tendency of the film along the film surface causes compressive stress. The intrinsic stress is closely related to the preparation method and the process of the thin film, and is different with the difference of the thin film and the base material.
Under the condition that other process conditions are not changed, the higher the reaction temperature is, the larger the generated waveguide compressive stress is; under the condition that other process conditions are not changed, the higher the reaction pressure is, the smaller the generated waveguide pressure stress is; under the condition that other process conditions are not changed, the higher the low-frequency power is, the higher the generated waveguide compressive stress is. And the magnitude of the pressure stress has a certain linear relation with the reaction temperature, the reaction pressure, the low-frequency power and the gas flow ratio. The relationship between the compressive stress and each parameter is shown in the following formula:
the relation between the reaction temperature and the compressive stress is that Tc is-1.0 × T-463.6;
the relation between the reaction pressure and the pressure stress is that Tc is 1.03 × P-1363.5;
tc is-0.7 × R-813.4;
the relationship between the gas flow rate and the pressure stress is that Tc is 24 × X2-167×X-560。
Wherein Tc is compressive stress in Pa; t is the reaction temperature and the unit is; p is the reaction pressure in mTorr; r is low-frequency power and has the unit of W; and X is the gas flow ratio.
S5, depositing a detector SiN film 008 on the detector area and the substrate;
wherein, step S5 includes:
referring to fig. 2p and fig. 2q specifically, fig. 2p is a schematic process flow diagram of a method for manufacturing a optoelectronic integrated device according to an embodiment of the present invention, and fig. 2q is a schematic top view structure diagram of the optoelectronic integrated device manufactured by the process corresponding to fig. 2p according to the embodiment of the present invention.
S51, introducing SiH under a second preset condition4And NH3A PECVD process is used for depositing a detector SiN film 008 with the thickness of 10-20nm on the detector area and the substrate 001.
The second preset condition includes: reaction temperature, pressure, radio frequency power, reaction gas. Wherein the reaction temperature is 240-280 ℃, the pressure is 1500mTorr, the radio frequency power is 200W, and SiH4And NH3The gas flow ratio of (2) is 0.75.
Fig. 2r is a schematic diagram of a right-view structure of a detector region and a substrate 001 covered by the detector SiN film 008 according to the embodiment of the present invention, and fig. 2s is a schematic diagram of a right-view principle that the detector SiN film 008 according to the embodiment of the present invention generates tensile stress on the detector, as shown in fig. 2s, atoms or ions of the detector SiN film 008 are bonded or redistributed by introducing high-energy particle bombardment with a radio frequency power source, that is, the detector SiN film 008 becomes stretchable, so that intrinsic tensile stress is generated on the detector. Under the condition that other process conditions are not changed, the higher the reaction temperature is, the larger the tensile stress of the produced detector is; under the condition that other process conditions are not changed, the higher the reaction pressure is, the smaller the tensile stress of the produced detector is; under the condition that other process conditions are unchanged, the larger the radio frequency power is, the larger the tensile stress of the detector is generated. And the tensile stress is in a certain linear relation with the reaction temperature, the reaction pressure, the radio frequency power and the gas flow ratio. The relationship between the tensile stress and each parameter is shown in the following formula:
the relation between the reaction temperature and the tensile stress Ts is 1.2 × T-34.1;
the relation between the reaction pressure and the tensile stress Ts is 0.3 × P-28.5;
radio frequency power and tensile stress Ts relation, Ts (-2.48 × 10)-6)×R2+0.26×R+134.1；
Flow of gasRatio and tensile stress Ts relation, Ts ═ 265.4 × X2+574.6×X+140.3。
Wherein Ts is tensile stress with the unit of Pa; t is the reaction temperature and the unit is; p is the reaction pressure in mTorr; r is radio frequency power and has the unit of W; and X is the gas flow ratio.
Because the waveguide SiN film 007 wraps the waveguide region, stress directly acts on the waveguide, so that the waveguide is subjected to compressive stress, and the forbidden bandwidth of the waveguide is increased; because the detector SiN film 008 wraps the detector region and the substrate, the stress directly acts on the detector, so that the detector generates tensile stress along the direction perpendicular to the light transmission direction, and the forbidden bandwidth of the detector is reduced. Thereby satisfying the forbidden band relation: eg waveguide > Eg light emitting device > Eg detector, where Eg represents the forbidden band width. The integration of the light-emitting device, the waveguide and the detecting device is realized on the same layer by modulating the forbidden band relation of the light-emitting device, the waveguide and the detector, and the device has the advantages of novel structure, high integration level and low process cost.
S6, an electrode is formed on the light emitting device region, on the substrate 001, and on the detector SiN film 008.
Wherein, step S6 includes:
referring to fig. 2t and fig. 2u specifically, fig. 2t is a schematic process flow diagram of a method for manufacturing a optoelectronic integrated device according to an embodiment of the present invention, and fig. 2u is a schematic top view structure diagram of the optoelectronic integrated device manufactured by the process corresponding to fig. 2t according to the embodiment of the present invention.
S61, evaporating and depositing metal Al on the luminescent device area, the substrate 001 and the detector SiN film 008 by using an electron beam evaporation process, wherein the thickness is 10-20nm, and forming metal contact;
and S62, selectively etching the metal Al in the designated area by using an etching process to form a light-emitting device electrode 009 and a detector electrode 010 respectively.
The electron beam evaporation is a method of directly evaporating a material by using an electron beam under a vacuum condition, vaporizing the evaporated material and transporting the vaporized material to a substrate, and condensing the vaporized material on the substrate to form a thin film.
Fig. 7 is a schematic front view structure diagram of a photonic integrated device according to an embodiment of the present invention, where the photonic integrated device is manufactured by the above-mentioned method, and as shown in the figure, the photonic integrated device includes a substrate 001, a buried light emitting device layer 0021, a waveguide buried layer 0022, a detector buried layer 0023, a top light emitting device layer 0031, a top detector layer 0032, a protective light emitting device layer 0041, a protective detector layer 0042, an isolation layer 005, a cover layer 006, a waveguide SiN film 007, a detector SiN film 008, a photonic device electrode 009, a detector electrode 010, a substrate 001, a buried light emitting device layer 0021, a buried waveguide buried layer 0022, a detector buried layer 0023, a top light emitting device layer 0031, a top detector layer 0032, a protective light emitting device layer 0041, a detector protective layer 0042, an isolation layer 005, a cover layer 006, a waveguide SiN film 007, a detector SiN film 008, a photonic, the photoelectric integrated device is formed by a multilayer structure formed by vertically distributing from bottom to top.
The substrate 001 is formed by an n + doped Si material, and the thickness is 30-750 nm; the light-emitting device buried layer 0021 and the detector buried layer 0023 are formed by n + doped Ge materials, and the thicknesses of the n + doped Ge materials and the detector buried layer are both 1000 nm; the buried waveguide layer 0022 is formed by an n + Ge-doped material, and the thickness is 160-; the top layer 0031 of the light-emitting device and the top layer 0032 of the detector are formed by p + doped Si materials, and the thicknesses of the two layers are 300 nm; the thicknesses of the luminescent device protective layer 0041 and the detector protective layer 0042 are both 900 nm; the isolation layer 005 is made of SiO2The thickness of the cladding layer 006 is 20-50nm, the thickness of the cladding layer 006 is α -Si material and is 800-840nm, the thicknesses of the waveguide SiN film 007 and the detector SiN film 008 are 10-20nm, and the light-emitting device electrode 009 and the detector electrode 010 are both made of metal Al.
The photoelectric integrated device provided by the embodiment of the invention realizes the preparation of the light-emitting device, the waveguide and the detector at the same layer by utilizing the Si-based modified Ge material, thereby reducing the production cost of the device and shortening the process period.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (10)
1. A method for preparing a photoelectric integrated device is characterized by comprising the following steps:
selecting an n-type doped Si substrate;
sequentially growing an n-type doped Ge layer, a p-type doped Si layer and a protective layer on the substrate;
etching the protective layer, the p-type doped Si layer and the n-type doped Ge layer to form a light-emitting device region, a waveguide region and a detector region which are isolated in sequence;
depositing waveguide SiN films on the waveguide region and two sides of the waveguide region;
depositing detector SiN films on the substrate, the detector area and two sides of the detector area;
and forming electrodes on the light-emitting device region, the substrate and the detector SiN film to finish the preparation of the photoelectric integrated device.
2. The method of claim 1, wherein the sequentially growing an n-type doped Ge layer, a p-type doped Si layer, and a protective layer on the substrate comprises:
epitaxially growing the n-type Ge-doped layer on the substrate by using a CVD (chemical vapor deposition) process at a temperature of 310-330 ℃ and with a doping concentration of 1019cm-3；
Annealing the n-type Ge-doped layer at 850 ℃;
growing the p-type doped Si layer on the n-type doped Ge layer by using a CVD (chemical vapor deposition) process at the temperature of 275-325 ℃, wherein the doping concentration is 1020cm-3；
Depositing the protective layer on the p-type doped Si layer using an LPCVD process.
3. The method for manufacturing a photonic integrated device according to claim 1, wherein etching the protective layer, the p-type doped Si layer, and the n-type doped Ge layer to form a light emitting device region, a waveguide region, and a detector region which are sequentially isolated comprises:
introducing HF to etch the protective layer and the p-type doped Si layer by using a dry etching process;
by using a dry etching process, HF to HNO with the concentration ratio of 1:2.5:10 is adopted3:CH3And continuously etching the n-type Ge-doped layer to the substrate by COOH to form the light-emitting device region, the waveguide region and the detector region which are sequentially isolated.
4. The method for manufacturing a photonic integrated device according to claim 1, wherein etching the protective layer, the p-type doped Si layer, and the n-type doped Ge layer to form a light emitting device region, a waveguide region, and a detector region which are sequentially isolated comprises:
introducing HF to etch the protective layer and the p-type doped Si layer by using a dry etching process;
by using a dry etching process, HF to HNO with the concentration ratio of 1:2.5:10 is adopted3:CH3Etching the n-type Ge-doped layer on the substrate by COOH to form the light-emitting device region, the etching region and the detector region which are sequentially isolated, wherein isolation grooves are respectively arranged between the etching region and the light-emitting device region and between the etching region and the detector region;
depositing an isolation layer in the isolation trench;
and adding a covering layer on the etching area to form the waveguide area, wherein the etching area, the isolation layer and the covering layer form the waveguide area.
5. The method of claim 1, wherein depositing a waveguide SiN film on and on both sides of the waveguide region comprises:
introducing SiH under a first preset condition4And NH3And depositing waveguide SiN films on the waveguide region and two sides by using a PECVD process.
6. Method for preparing an optoelectronic integrated device according to claim 5, characterized in thatCharacterized in that the first preset condition comprises: the reaction temperature is 400-450 ℃, the pressure is 500mTorr, the low-frequency power is 150W, and the SiH4And said NH3The gas flow ratio of (2).
7. The method of claim 1, wherein depositing a detector SiN film on the substrate, on the detector region, and on both sides of the detector region comprises:
introducing the SiH under a second preset condition4And said NH3And depositing detector SiN films on the substrate, the detector area and two sides by using a PECVD process.
8. The method for manufacturing an optoelectronic integrated device according to claim 7, wherein the second preset condition comprises: the reaction temperature is 240-280 ℃, the pressure is 1500mTorr, the radio frequency power is 200W, and the SiH4And said NH3The gas flow ratio of (2) is 0.75.
9. The method for manufacturing an optoelectronic integrated device according to claim 1, wherein the forming of an electrode on the light emitting device region, on the substrate and on the detector SiN film comprises:
and evaporating and depositing metal Al on the luminescent device area, the substrate and the detector SiN film, wherein the thickness is 10-20nm, and metal contact is formed.
10. An optoelectronic integrated device prepared by the method of any one of claims 1 to 9.
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