CN111341840A - Field effect transistor device - Google Patents

Field effect transistor device Download PDF

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Publication number
CN111341840A
CN111341840A CN202010144306.XA CN202010144306A CN111341840A CN 111341840 A CN111341840 A CN 111341840A CN 202010144306 A CN202010144306 A CN 202010144306A CN 111341840 A CN111341840 A CN 111341840A
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passivation layer
field plate
effect transistor
layer
field effect
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CN111341840B (en
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马培培
郑军
成步文
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Institute of Semiconductors of CAS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/405—Resistive arrangements, e.g. resistive or semi-insulating field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention discloses a field effect transistor device, comprising: a composite passivation layer comprising: the first passivation layer is arranged on the gate dielectric layer of the field effect transistor and covers a source electrode, a drain electrode and a gate electrode of the field effect transistor; and a second passivation layer disposed on the first passivation layer; and a lateral field plate arranged in contact with the gate electrode and arranged in the first passivation layer; and the floating field plate is arranged on the second passivation layer. The field effect transistor device provided by the invention is designed with a composite passivation layer with a two-layer structure, wherein the structure of the composite passivation layer is a first passivation layer/a second passivation layer, the first passivation layer is used as a passivation layer of a transverse field plate, and the second passivation layer is used as a passivation layer of a floating field plate. According to the invention, through designing parameters of the transverse field plate, the floating field plate and the composite passivation layer, peak electric fields of the gate dielectric layer and the field plate passivation layer are effectively reduced, and the breakdown voltage of the gallium oxide single-pole device is improved.

Description

Field effect transistor device
Technical Field
The invention relates to the technical field of microelectronics, in particular to a high-voltage resistant field effect transistor device.
Background
Gallium oxide (Ga)2O3) The forbidden band width of the crystal is 4.2-4.9eV, and the crystal is a direct band gap III-V group ultra wide band gap semiconductor material with excellent chemical and thermal stabilityAnd (4) sex. Because of excellent physical properties and chemical stability, the material has great potential in the application aspects of optoelectronic devices such as high-voltage resistant, low-loss, high-power, high-temperature resistant and solar blind, such as high-power field effect transistors, semiconductor photodetectors and the like, and can play an important role in severe environments such as aviation, aerospace and the like. Ga2O3As a fourth generation semiconductor material, the material has the characteristics of large forbidden band width, high breakdown field strength, low conduction power consumption and the like, and is particularly suitable for preparing high-voltage high-power devices. And Ga2O3P-type doping cannot be realized at present, so Ga2O3Materials in the preparation of unipolar devices such as: field Effect Transistors (MOSFETs) and Schottky Barrier Diodes (SBDs) have great advantages.
With the expansion of application fields, in many fields such as electric vehicles and industrial engines, in order to effectively implement power conversion and control, a high-performance power device is urgently needed, that is, the device not only has low on-state power consumption, but also is expected to have strong high-voltage resistance in an off-state. Present Ga2O3The voltage endurance of the unipolar device is not yet satisfactory for practical applications and far from Ga2O3The ideal physical limits of the material.
In increasing Ga2O3In terms of the breakdown voltage of the MOSFET device, a lot of research is carried out, and it is found that the peak electric field of the device is mainly distributed on the side of the gate dielectric layer close to the drain electrode. Therefore, to increase the breakdown voltage of the device, the electric field in the gate-drain region must be redistributed, especially to reduce the peak electric field of the dielectric layer, and a method using a field plate structure has been proposed.
The field plate structure is formed by growing a dielectric film, such as a silicon oxide film, on the periphery of the schottky metal through the process steps of photoetching, deposition, etching and the like, and then extending the metal to the upper part of the dielectric and covering part of the insulating dielectric when preparing the schottky electrode. When reverse voltage is applied, the field plate can expand a depletion region of the Schottky junction in the horizontal direction, so that electric field lines concentrated on the edge of the Schottky junction become sparse, and an electric field extreme value becomes small.
Ga with field plate structure prepared in prior art2O3The breakdown voltage of the MOSFET device reaches 750V. Ga with field plate structure is also prepared in the prior art2O3And SBD, the breakdown voltage of the device reaches 1 kV. In the present Ga2O3In the research of the MOSFET and the SBD device, the field plate structure is added to improve the breakdown voltage of the device, so that a certain effect is achieved. A drawback of the existing field plate structure is that breakdown of the insulating medium (i.e. the field plate passivation layer) becomes a new limitation for the increase of the breakdown voltage of the device.
Disclosure of Invention
The invention aims to provide a high-voltage resistant field effect transistor device. To at least partially solve the above problems.
In order to achieve the purpose, the technical scheme of the invention is as follows:
the present invention provides a field effect transistor device comprising:
a composite passivation layer comprising:
the first passivation layer is arranged on the gate dielectric layer of the field effect transistor and covers a source electrode, a drain electrode and a gate electrode of the field effect transistor; and
a second passivation layer disposed on the first passivation layer; and
the transverse field plate is arranged in contact with the gate electrode and is arranged in the first passivation layer;
and the floating field plate is arranged on the second passivation layer.
In some embodiments, the floating field plate is tangential to the lateral field plate.
In some embodiments, the material of the first passivation layer or the second passivation layer includes silicon oxide, silicon nitride, aluminum oxide, zirconium oxide, or hafnium oxide, and the material of the first passivation layer and the second passivation layer is different.
In some embodiments, the field effect transistor device further comprises:
a semi-insulating substrate;
the buffer layer is arranged on the semi-insulating substrate;
the channel layer is arranged on the buffer layer;
the source electrode doping area and the drain electrode doping area are arranged on two sides of the channel layer;
and the channel layer is connected to the gate dielectric layer, the source electrode and the drain electrode are arranged on two sides of the gate dielectric layer, and the gate electrode is arranged on the gate dielectric layer.
In some embodiments, the first passivation layer has a thickness of 50nm to 500nm and the second passivation layer has a thickness of 20nm to 200 nm.
In some embodiments, the length of the lateral field plate is 1 μm to 20 μm, the length of the floating field plate is 1 μm to 20 μm, and the thickness of the lateral field plate and the floating field plate is 50nm to 1000 nm.
In some embodiments, the semi-insulating substrate is doped with Mg, Fe or N, and the channel layer is doped with Si, Ge or Sn at a doping concentration of 1 × 1017cm-3-9×1018cm-3The doped source region and the doped drain region are doped with Si, Ge or Sn at a doping concentration of 1 × 1019cm-3-1×1020cm-3。
In some embodiments, the buffer layer has a thickness of 300nm to 500nm, the channel layer has a thickness of 100nm to 300nm, the source doped region and the drain doped region have a thickness of 10nm to 200nm, the gate dielectric layer has a thickness of 5nm to 50nm, the source electrode and the drain electrode have a thickness of 50nm to 1000nm, and the gate electrode has a thickness of 50nm to 1000 nm.
The field effect transistor device has the following beneficial effects:
(1) the invention combines the floating field plate structure and the composite passivation layer structure, can effectively reduce the peak electric field intensity in the passivation layer, and improves the high-voltage resistance of the device;
(2) according to the invention, by designing parameters of the transverse field plate, the floating field plate and the composite passivation layer, peak electric fields of the gate dielectric layer and the field plate passivation layer can be effectively reduced, the leakage current of the device is reduced, and the breakdown voltage of the gallium oxide single-pole device is improved.
Drawings
For the purpose of illustrating the detailed technical content of the invention, the following detailed description is provided in conjunction with the drawings, in which:
fig. 1 is a schematic diagram of a field effect transistor device in accordance with an embodiment of the present invention;
fig. 2 is a breakdown characteristic curve of a field plate structure-free device, a lateral field plate structure device and a structural device according to an embodiment of the invention.
In the figure:
semi-insulating substrate a buffer layer b channel layer c
Grid dielectric layer g of source heavily doped region d drain heavily doped region e
Source electrode f drain electrode h gate electrode i
Lateral field plate j first passivation layer k second passivation layer l
Floating field plate m
Detailed Description
In order that the objects, technical solutions and advantages of the present invention will become more apparent, the present invention will be further described in detail with reference to the accompanying drawings in conjunction with the following specific embodiments.
An embodiment of the present invention provides a field effect transistor device having high voltage resistance, including:
a composite passivation layer comprising:
the first passivation layer is arranged on the gate dielectric layer of the field effect transistor and covers a source electrode, a drain electrode and a gate electrode of the field effect transistor; and
a second passivation layer disposed on the first passivation layer; and
the transverse field plate is arranged in contact with the gate electrode and is arranged in the first passivation layer;
and the floating field plate is arranged on the second passivation layer.
The effect transistor device provided by the embodiment designs a composite passivation layer with a two-layer structure, the structure of the composite passivation layer is a first passivation layer/a second passivation layer, the first passivation layer is used as a passivation layer of a transverse field plate, the second passivation layer is used as a passivation layer of a floating field plate, and parameters of the transverse field plate, the floating field plate and the composite passivation layer can be designed, so that peak electric fields of a gate dielectric layer and the field plate passivation layer are effectively reduced, and the breakdown voltage of a gallium oxide single-pole device is improved.
In some embodiments, the floating field plate is tangential to the lateral field plate. Preferably, in the embodiment, as shown in fig. 2, the left edge of the floating field plate is tangent to the right edge of the lateral field plate, but not limited thereto. When the gate electrode applies voltage to turn off the device, and meanwhile, the drain electrode applies positive high voltage, static charge can be induced between the floating field plate and the transverse field plate, and then electric field distribution at the edges of the channel and the transverse field plate is influenced. When the floating field plate is deviated to the right side, the static action is reduced due to the longer distance between the two field plates, and the regulation and control effect of the floating field plate on the electric field is reduced; when the floating field plate is deviated to the left, only the part exceeding the transverse field plate has the regulation and control function on the electric field. Therefore, when the floating field plate and the transverse field plate are tangent, the floating field plate has the best regulation and control effect on the electric field.
In some embodiments, the material of the first passivation layer or the second passivation layer comprises silicon oxide (SiO)2) Silicon nitride (Si)3N4) Alumina (Al)2O3) Zirconium oxide (ZrO)2) Or hafnium oxide (HfO)2) And the materials of the first passivation layer and the second passivation layer are different. Wherein the first passivation layer is made of SiO2Or Si3N4The passivation effect is good, and the interface state density is low; the material of the second passivation layer is Al2O3、HfO2Or ZrO2The material has larger dielectric constant, the larger the dielectric constant is, the stronger the coupling effect of the capacitor is, the more obvious the modulation effect on the electric field is, and the electric field peak value at the edge of the floating field plate can be weakened to a great extent, so that the breakdown voltage can be obviously improved.
In this embodiment, the composite passivation layer structure may be SiO2、Si3N4、Al2O3、ZrO2、HfO2Are combined into a first passivation layer/second passivation layer structure.
Further, referring to fig. 1, in some embodiments, the device structure sequentially includes, from bottom to top: ga2O3Semi-insulating substrate a, Ga2O3Buffer layer b, Ga2O3The two sides of the channel layer c are respectively heavily doped with source electrodesAnd a gate dielectric layer g is arranged on the channel layer c, a source electrode f and a drain electrode h are respectively arranged on two sides of the channel layer c, a gate electrode i, a transverse field plate j and a first passivation layer k are arranged on the gate dielectric layer g, and a second passivation layer l and a floating field plate m are arranged on the transverse field plate j.
In some embodiments, wherein:
said Ga being2O3The channel layer c is doped with Si, Ge or Sn at shallow energy level donor and the doping concentration is 1 × 1017cm-3-9×1018cm-3；
Said Ga being2O3The thickness of the buffer layer b is 300nm-500 nm. The thickness of the channel layer c is 100nm-300 nm.
The thickness of a first passivation layer k below a transverse field plate is 50nm-500nm, the length of a transverse field plate j is 1 mu m-20 mu m, the thickness of a second passivation layer l below a floating field plate m is 20nm-200nm, the length of the floating field plate m is 1 mu m-20 mu m, and the thicknesses of the transverse field plate j and the floating field plate m are 50nm-1000 nm;
said Ga being2O3The semi-insulating substrate a is doped with deep-level compensation acceptors such as Mg, Fe or N, and the crystal orientation of the substrate is (100), (010), (001) or (-201);
said Ga being2O3The channel layer c is doped with Si, Ge or Sn at a shallow energy level donor and has a doping concentration of 1 × 1017cm-3-9×1018cm-3；
The source heavily doped region d and the drain heavily doped region e are donor doped with Si, Ge or Sn at shallow energy level, and the doping concentration is 1 × 1019cm-3-1×1020cm-3；
Said Ga being2O3The thickness of the buffer layer b is 300nm-500nm, the thickness of the channel layer c is 100nm-300nm, the uniform doping thickness of the source heavily doped region d and the drain heavily doped region e is 10nm-200nm, and the thickness of the gate dielectric layer g is 5-50 nm;
the thickness range of the metal of the source electrode and the drain electrode (f, h) is 50nm-1000 nm;
the thickness range of the gate electrode i metal is 50nm-1000 nm.
Based on the field effect transistor device, another embodiment of the present invention provides a manufacturing process for implementing the field effect transistor device, which includes the steps of: (1) cleaning; (2) growing an epitaxial layer on the substrate; (3) ion implantation (4) is carried out on the source and drain regions to deposit a gate dielectric layer; (5) depositing a passivation layer I; (6) preparing a source drain electrode, a gate electrode and a transverse field plate; (7) depositing a passivation layer II; (8) and preparing a floating field plate.
The specific implementation mode comprises the following steps:
the manufacturing method of the high voltage resistant field effect transistor provided by the embodiment includes the following specific processes:
(1) cleaning a substrate: ga is mixed with2O3Boiling the semi-insulating substrate material with acetone and ethanol for 10min, cleaning with deionized water for 30 times, and blow-drying with high-purity nitrogen;
(2) and (3) epitaxial growth: putting the cleaned substrate into MOCVD equipment, and growing 100nm-300nm Si-doped Ga by controlling process parameters2O3A channel layer;
(3) ion implantation and annealing treatment: firstly, photoetching a sample wafer to form a source-drain region pattern window, then carrying out ion implantation on a source-drain ohmic contact region, and then carrying out annealing treatment at 950 ℃ for 30min in a nitrogen environment. Then cleaning the sample wafer according to the method in the step (1);
(4) preparing a gate dielectric layer: putting the cleaned sample wafer into atomic layer deposition equipment, and depositing 25nm Al at 250 DEG C2O3A gate dielectric layer is formed, and then annealing treatment is carried out for 5min at 450 ℃ in an oxygen environment;
(5) depositing a first passivation layer: placing the sample wafer into PECVD equipment, and depositing a first passivation layer, in this embodiment, depositing a 300nm passivation layer Si3N4As a first passivation layer;
(6) photoetching: will complete the passivation layer Si3N4Photoetching the grown sample wafer, and placing the sample wafer into RIE etching equipment to etch the source/drain electrode and gate electrode regions, wherein the first passivation layer/gate dielectric layer (represented as Si in the embodiment) is formed3N4/Al2O3) Is performed under process conditions having a selectivity greater than 50. Then the sample is steppedCleaning by the method of the step (1);
(7) preparing an electrode and a transverse field plate: placing the photoetched sample wafer into an electron beam evaporation table to deposit metal Ti/Au, stripping, finally performing 470 ℃ rapid thermal annealing for 1min in a nitrogen environment, and then cleaning the sample wafer according to the method in the step (1);
(8) preparing a second passivation layer: placing the sample wafer into an atomic layer deposition device, depositing a second passivation layer, in this embodiment, depositing 50nm passivation layer HfO2As a second passivation layer;
(9) preparing a floating field plate: and placing the sample wafer with the etched floating field plate region into an electron beam evaporation table for depositing metal and stripping, and adjusting the position of the floating field plate to ensure that the floating field plate is tangent to the transverse field plate, wherein the length of the floating field plate is equal to that of the transverse field plate. Then, the sample wafer is cleaned according to the method in the step (1).
Thus, the preparation of the high voltage resistant field effect transistor of the invention is completed.
Fig. 2 shows breakdown characteristic curves of a device without a field plate structure, a device with a lateral field plate structure, and a device with a structure according to an embodiment of the present invention. The parameters of the three devices in the figure, such as channel doping concentration, source gate spacing, gate drain spacing and the like, are kept consistent. Wherein when the drain voltage of the device without field plate structure is 100V, the leakage current reaches 10-5And A, the device breaks down. The breakdown voltage of the device with the transverse field plate structure is 400V. The structural device provided by the invention is not broken down at 2000V. The comparison shows that the structure provided by the invention can effectively improve the voltage endurance performance of the device.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A field effect transistor device, comprising:
a composite passivation layer comprising:
the first passivation layer is arranged on the gate dielectric layer of the field effect transistor and covers the source electrode, the drain electrode and the gate electrode of the field effect transistor; and
a second passivation layer disposed on the first passivation layer; and
the transverse field plate is arranged in contact with the gate electrode and is arranged in the first passivation layer;
and the floating field plate is arranged on the second passivation layer.
2. The field effect transistor device of claim 1, wherein the floating field plate is tangent to the lateral field plate.
3. The field effect transistor device of claim 1 or 2, wherein the material of the first passivation layer or the second passivation layer comprises silicon oxide, silicon nitride, aluminum oxide, zirconium oxide, or hafnium oxide, and the material of the first passivation layer and the second passivation layer is not the same.
4. The field effect transistor device of claim 3, further comprising:
a semi-insulating substrate;
the buffer layer is arranged on the semi-insulating substrate;
the channel layer is arranged on the buffer layer;
the source electrode doping area and the drain electrode doping area are arranged on two sides of the channel layer;
the channel layer is connected to the gate dielectric layer, the source electrode and the drain electrode are arranged on two sides of the gate dielectric layer, and the gate electrode is arranged on the gate dielectric layer.
5. The field effect transistor device of claim 3, wherein the first passivation layer has a thickness of 50nm to 500nm and the second passivation layer has a thickness of 20nm to 200 nm.
6. The field effect transistor device of claim 3, wherein the length of the lateral field plate is 1 μm-20 μm, the length of the floating field plate is 1 μm-20 μm, and the thickness of the lateral field plate and the floating field plate is 50nm-1000 nm.
7. The field effect transistor device of claim 4, wherein:
doping Mg, Fe or N into the semi-insulating substrate;
the channel layer is doped with Si, Ge or Sn, and the doping concentration is 1 × 1017cm-3-9×1018cm-3。
8. The field effect transistor device of claim 4, wherein the source doped region and the drain doped region are doped with Si, Ge, or Sn at a doping concentration of 1 × 1019cm-3-1×1020cm-3。
9. The field effect transistor device of claim 4, wherein the buffer layer has a thickness of 300nm-500nm, the channel layer has a thickness of 100nm-300nm, and the source doped region and the drain doped region have a thickness of 10nm-200 nm.
10. The field effect transistor device according to claim 4, wherein the gate dielectric layer has a thickness of 5 to 50nm, the source electrode and the drain electrode have a thickness of 50 to 1000nm, and the gate electrode has a thickness of 50 to 1000 nm.
CN202010144306.XA 2020-03-04 2020-03-04 Field effect transistor device Active CN111341840B (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101299437A (en) * 2007-05-01 2008-11-05 冲电气工业株式会社 Field effect transistor having field plate electrodes
CN105226093A (en) * 2015-11-11 2016-01-06 成都嘉石科技有限公司 GaN HEMT device and preparation method thereof
US20160268389A1 (en) * 2015-03-12 2016-09-15 Kabushiki Kaisha Toshiba Semiconductor device
CN107275385A (en) * 2017-06-23 2017-10-20 深圳市晶相技术有限公司 Gallium nitride semiconductor device and preparation method thereof
CN107316892A (en) * 2017-06-23 2017-11-03 深圳市晶相技术有限公司 Gallium nitride semiconductor device and preparation method thereof
US20180331186A1 (en) * 2017-05-12 2018-11-15 Puneet Srivastava Gallium nitride device for high frequency and high power applications

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101299437A (en) * 2007-05-01 2008-11-05 冲电气工业株式会社 Field effect transistor having field plate electrodes
US20160268389A1 (en) * 2015-03-12 2016-09-15 Kabushiki Kaisha Toshiba Semiconductor device
CN105226093A (en) * 2015-11-11 2016-01-06 成都嘉石科技有限公司 GaN HEMT device and preparation method thereof
US20180331186A1 (en) * 2017-05-12 2018-11-15 Puneet Srivastava Gallium nitride device for high frequency and high power applications
CN107275385A (en) * 2017-06-23 2017-10-20 深圳市晶相技术有限公司 Gallium nitride semiconductor device and preparation method thereof
CN107316892A (en) * 2017-06-23 2017-11-03 深圳市晶相技术有限公司 Gallium nitride semiconductor device and preparation method thereof

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