CN111341773A - Enhancement and depletion type integrated power device and manufacturing method thereof - Google Patents
Enhancement and depletion type integrated power device and manufacturing method thereof Download PDFInfo
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0883—Combination of depletion and enhancement field effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8236—Combination of enhancement and depletion transistors
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Abstract
The enhancement type and depletion type integrated power device and the manufacturing method thereof provided by the embodiment of the application comprise a substrate, and an enhancement type power device and a depletion type power device which are formed on the substrate. The enhancement type power device comprises a first epitaxial structure, a P-type nitride layer formed on the first epitaxial structure through first epitaxial growth, a first N-type semiconductor layer and a first P-type semiconductor layer formed on the first epitaxial structure through second epitaxial growth. The depletion mode power device comprises a second epitaxial structure, a second N-type semiconductor layer and a second P-type semiconductor layer which are formed on the second epitaxial structure through second epitaxial growth. Therefore, the charge balance structure of the N-type semiconductor layer and the P-type semiconductor layer formed based on the secondary epitaxial growth optimizes the interface state of the P-type nitride layer after etching, obtains excellent saturation current characteristics, can be used as a gate dielectric layer of a depletion type power device, and improves the gate stability of the depletion type power device.
Description
Technical Field
The present application relates to the field of semiconductor devices, and more particularly, to an enhancement and depletion integrated power device and a method for fabricating the same.
Background
The gallium nitride material has the advantages of wide forbidden bandwidth, high critical breakdown electric field, high electron saturation velocity, high thermal conductivity, high concentration of two-dimensional electron gas of a heterojunction interface and the like, and is a third-generation semiconductor material widely applied. The working modes of the traditional gallium nitride device are mostly depletion mode devices, the problems of high power consumption and complex design exist, and with the introduction of enhancement mode devices, the effects of simplifying circuits and reducing cost can be achieved. In an enhancement type and depletion type integrated device, a gallium nitride enhancement type HEML device mainly adopts an etching process to form a grid electrode pattern, the method is easy to damage an interface, more interface states are generated, and the parameter characteristics such as saturation current are poor. In addition, the existing E-D mode (enhancement-depletion mode) integrated gallium nitride device needs to be realized on the basis of the E-mode, the gate Metal contact of the formed D-mode device is a schottky contact or a Metal-Insulator-Semiconductor (MIS) D-mode device formed by using a passivation medium, and the gate stability and the gate voltage swing are low.
Disclosure of Invention
The present application provides an enhancement-mode and depletion-mode integrated power device and a method for fabricating the same, which can improve the interface damage problem and improve the gate stability and the gate voltage swing of the device.
The embodiment of the application can be realized as follows:
in a first aspect, an embodiment provides an enhancement-mode and depletion-mode integrated power device, including:
a substrate;
an enhancement mode power device and a depletion mode power device formed on the substrate;
wherein the enhancement mode power device comprises:
a first epitaxial structure formed on the substrate;
a P-type nitride layer formed on the first epitaxial structure by first epitaxial growth;
forming a first N-type semiconductor layer and a first P-type semiconductor layer on the other regions of the first epitaxial structure except the P-type nitride layer through second epitaxial growth;
the depletion mode power device includes:
a second epitaxial structure formed on the substrate;
and a second N-type semiconductor layer and a second P-type semiconductor layer formed on the second epitaxial structure by the second epitaxial growth.
In an optional embodiment, the first P-type semiconductor layer and the second P-type semiconductor layer are P-type gallium nitride layers or P-type aluminum gallium nitride layers, and the first N-type semiconductor layer and the second N-type semiconductor layer are N-type gallium nitride layers or N-type aluminum gallium nitride layers.
In an alternative embodiment, the P-type nitride layer is a P-type gallium nitride layer or a P-type aluminum gallium nitride layer.
In an alternative embodiment, the integrated power device further comprises:
and the isolating layers are formed between the first N-type semiconductor layer and the second N-type semiconductor layer and between the first P-type semiconductor layer and the second P-type semiconductor layer.
In an alternative embodiment, the enhancement mode power device further comprises:
a first passivation layer formed on the first P-type semiconductor layer;
a first gate electrode penetrating the first passivation layer and contacting the P-type nitride layer;
and a first source electrode and a first drain electrode penetrating the first passivation layer, the first N-type semiconductor layer, the first P-type semiconductor layer and contacting the first epitaxial structure, the first source electrode and the first drain electrode being located at two sides of the first gate electrode.
In an alternative embodiment, the depletion mode power device further comprises:
a second passivation layer formed on the second P-type semiconductor layer;
a second gate electrode penetrating the second passivation layer and contacting the second P-type semiconductor layer;
and a second source electrode and a second drain electrode penetrating the second passivation layer, the second N-type semiconductor layer, and the second P-type semiconductor layer and contacting the second epitaxial structure, wherein the second source electrode and the second drain electrode are located at two sides of the second gate electrode.
In an alternative embodiment, the first epitaxial structure and the second epitaxial structure each comprise:
a buffer layer formed on the substrate;
the channel layer is formed on one side, away from the substrate, of the buffer layer and is made of a gallium nitride material;
and the barrier layer is formed on one side of the channel layer, which is far away from the buffer layer, wherein the isolation layer extends and penetrates through the barrier layer.
In a second aspect, an embodiment provides a method for manufacturing an enhancement-mode and depletion-mode integrated power device, the method comprising:
providing a substrate, wherein the substrate comprises a first area and a second area;
forming a first epitaxial structure based on a first region of the substrate, and performing first epitaxial growth based on the first epitaxial structure to form a P-type nitride layer;
and performing second epitaxial growth on the region of the first epitaxial structure except the P-type nitride layer to form a first N-type semiconductor layer and a first P-type semiconductor layer so as to form an enhancement-type power device, wherein a second epitaxial structure is further formed on the basis of a second region of the substrate, and the second epitaxial growth is further performed to grow a second N-type semiconductor layer and a second P-type semiconductor layer which are formed on the second epitaxial structure so as to form a depletion-type power device.
In an alternative embodiment, the method further comprises:
and forming isolation layers between the first N-type semiconductor layer and the second N-type semiconductor layer and between the first P-type semiconductor layer and the second P-type semiconductor layer by ion implantation.
In an optional embodiment, the first P-type semiconductor layer and the second P-type semiconductor layer are P-type gallium nitride layers or P-type aluminum gallium nitride layers, and the first N-type semiconductor layer and the second N-type semiconductor layer are N-type gallium nitride layers or N-type aluminum gallium nitride layers.
The beneficial effects of the embodiment of the application include, for example:
the enhancement type and depletion type integrated power device and the manufacturing method thereof provided by the embodiment of the application comprise a substrate, and an enhancement type power device and a depletion type power device which are formed on the substrate. The enhancement type power device comprises a first epitaxial structure formed on a substrate, a P-type nitride layer formed on the first epitaxial structure through first epitaxial growth, and a first N-type semiconductor layer and a first P-type semiconductor layer which are formed in other areas except the P-type nitride layer of the first epitaxial structure through second epitaxial growth. The depletion mode power device comprises a second epitaxial structure formed on the substrate, a second N-type semiconductor layer and a second P-type semiconductor layer which are formed on the second epitaxial structure through second epitaxial growth. Therefore, the charge balance structure of the N-type semiconductor layer and the P-type semiconductor layer formed based on the secondary epitaxial growth optimizes the interface state of the P-type nitride layer after etching, obtains the characteristics of excellent saturation current and the like, can be used as a gate dielectric layer of a depletion type power device, and improves the gate stability of the depletion type power device.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a schematic structural diagram of an integrated power device provided in an embodiment of the present application;
fig. 2-6 are schematic structural diagrams of devices formed in various steps in a process of manufacturing an integrated power device according to an embodiment of the present disclosure;
fig. 7 is a flowchart of a method for manufacturing an integrated power device according to an embodiment of the present disclosure.
Icon: 10-a substrate; 21-a first epitaxial structure; 211-a first buffer layer; 212 — a first channel layer; 213-first barrier layer; 22-a second epitaxial structure; 221-a second buffer layer; 222 — a second channel layer; 223-a second barrier layer; 30-enhancement mode power devices; a 31-P type nitride layer; 32-a first N-type semiconductor layer; 33-a first P-type semiconductor layer; 34-a first gate electrode; 35-a first source electrode; 36-a first drain electrode; 40-depletion mode power devices; 41-a second N-type semiconductor layer; 42-a second P-type semiconductor layer; 43-a second gate electrode; 44-a second source electrode; 45-a second drain electrode; 50-a barrier layer; 61-a first passivation layer; 62-a second passivation layer; 70-isolating layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present application, it should be noted that if the terms "upper", "lower", "inner", "outer", etc. are used to indicate an orientation or positional relationship based on that shown in the drawings or that the application product is usually placed in use, the description is merely for convenience and simplicity, and it is not intended to indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and therefore should not be construed as limiting the present application.
Furthermore, the appearances of the terms "first," "second," and the like, if any, are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance. It should be noted that the features of the embodiments of the present application may be combined with each other without conflict.
Referring to fig. 1, the present application provides an enhancement mode and depletion mode integrated power device, which includes a substrate 10, where the substrate 10 may be any one of silicon, sapphire, silicon carbide, and the like. A depletion mode power device 40 and an enhancement mode power device 30 are formed on the substrate 10.
Wherein the depletion mode power device 40 and the enhancement mode power device 30 share the underlying substrate 10. It will be appreciated that the substrate 10 may be divided into a first substrate that is part of the enhancement mode power device 30 and a second substrate that is part of the depletion mode power device 40.
The enhancement mode power device 30 includes a first epitaxial structure 21 formed on the substrate 10, the first epitaxial structure 21 may be formed on the first substrate, and the depletion mode power device 40 includes a second epitaxial structure 22 formed on the substrate 10, the second epitaxial structure 22 may be formed on the second substrate.
In this embodiment, the enhancement mode power device 30 includes a P-type nitride layer 31 formed on the first epitaxial structure 21 by first epitaxial growth, and the P-type nitride layer 31 is formed by deposition and etching. The P-type nitride layer 31 may be a P-type gallium nitride layer or a P-type aluminum gallium nitride layer. The enhancement-type power device 30 further includes a first N-type semiconductor layer 32 and a first P-type semiconductor layer 33 formed by second epitaxial growth in the other regions of the first epitaxial structure 21 except for the P-type nitride layer 31. The first N-type semiconductor layer 32 may be an N-type gan layer or an N-type algan layer, and the first P-type semiconductor layer 33 may be a P-type gan layer or a P-type algan layer.
The depletion mode power device 40 includes a second N-type semiconductor layer 41 and a second P-type semiconductor layer 42 formed on the second epitaxial structure 22 by the second epitaxial growth described above. The second N-type semiconductor layer 41 may be an N-type gan layer or an N-type algan layer, and the second P-type semiconductor layer 42 may be a P-type gan layer or a P-type algan layer.
In the integrated device provided by this embodiment, the charge balance structure formed by the N-type semiconductor layer and the P-type semiconductor layer grown by the second epitaxy can optimize the interface state of the P-type nitride layer 31 after etching, and obtain excellent characteristics such as saturation current. In addition, the N-type semiconductor layer and the P-type semiconductor layer can be used as gate dielectric layers of the depletion type power device 40, and the gate stability of the depletion type power device 40 is improved.
In the present embodiment, referring to fig. 2, an epitaxial structure including a first epitaxial structure 21 and a second epitaxial structure 22 is first formed on a provided substrate 10. The first epitaxial structure 21 and the second epitaxial structure 22 respectively include a buffer layer formed on the substrate 10, a channel layer formed on a side of the buffer layer away from the substrate 10, and a barrier layer formed on a side of the channel layer away from the buffer layer. Specifically, the first epitaxial structure 21 may include a first buffer layer 211 formed on the first substrate, a first channel layer 212 formed on a side of the first buffer layer 211 away from the first substrate, and a first barrier layer 213 formed on a side of the first channel layer 212 away from the first buffer layer 211. And the second epitaxial structure 22 may include a second buffer layer 221 formed on the second substrate, a second channel layer 222 formed on a side of the second buffer layer 221 away from the second substrate, and a second barrier layer 223 formed on a side of the second channel layer 222 away from the second buffer layer 221. The channel layer may be made of a gallium nitride material, and the channel layer may be used to provide a channel for carrier movement. The barrier layer can play a role of a potential barrier and can prevent carriers in the channel layer from flowing to the barrier layer. The barrier layer may include gan and other gallium compound semiconductor materials, such as AlGaN, InGaN, etc., or may be a stack of the gallium compound semiconductor material and other semiconductor materials.
Referring to fig. 2 and 3 in combination, in the present embodiment, in fabricating the P-type nitride layer 31 for forming the enhancement mode power device 30, the P-type nitride layer 31 may be first formed on the basis of the epitaxial growth of the first epitaxial structure 21, and a barrier layer 50, typically a dielectric layer, may be deposited on the grown P-type nitride layer 31. An etching region is defined on the barrier layer 50 by means of photolithography and etching, and specifically, a photoresist layer may be formed on the barrier layer 50, and the photoresist layer may be formed on the barrier layer 50 by means of coating photoresist. The photoresist may be an inversion photoresist AE5214, an inversion photoresist SPR220, or other types of photoresist. The photoresist layer on the barrier layer 50 is then subjected to photolithography using a mask and developed, so that a partial region of the barrier layer 50 is exposed, and the barrier layer 50 is etched based on the exposed region.
The P-type nitride layer 31 is etched based on the etched barrier layer 50, and the photoresist layer remaining after exposure and development is removed, for example, N-methyl pyrrolidone or acetone may be used to remove the photoresist layer, so as to form the device structure of the P-type nitride layer 31 and the barrier layer 50 remaining after etching as shown in fig. 3.
In this embodiment, the first N-type semiconductor layer 32 and the first P-type semiconductor layer 33 of the enhancement-type power device 30, and the second N-type semiconductor layer 41 and the second P-type semiconductor layer 42 of the depletion-type power device 40 are formed together during the second epitaxial growth. Wherein the first N-type semiconductor layer 32 and the first P-type semiconductor layer 33 of the enhancement type power device 30 may be formed on the first epitaxial structure 21, and the second N-type semiconductor layer 41 and the second P-type semiconductor layer 42 of the depletion type power device 40 may be formed on the second epitaxial structure 22. Alternatively, in the second epitaxial growth, the growth of the N-type semiconductor layer is first performed to obtain the first N-type semiconductor layer 32 of the first epitaxial structure 21 and the second N-type semiconductor layer 41 formed on the second epitaxial structure 22. Since the P-type nitride layer 31 and the barrier layer 50 are formed on the first epitaxial structure 21 and the secondary epitaxial layer cannot be grown on the barrier layer 50, the first N-type semiconductor layer 32 is formed on the other region of the first epitaxial structure 21 except the P-type nitride layer 31.
The first P-type semiconductor layer 33 is continuously grown and formed based on the formed first N-type semiconductor layer 32, and the second P-type semiconductor layer 42 is continuously grown and formed on the second N-type semiconductor layer 41. Thereby constituting a charge balance structure of the first N-type semiconductor layer 32 and the first P-type semiconductor layer 33, and a charge balance structure of the second N-type semiconductor layer 41 and the second P-type semiconductor layer 42.
After the above fabrication is completed, the remaining barrier layer 50 is removed to form the device structure as in fig. 4.
On the basis of the above, referring to fig. 1 again, in the present embodiment, the integrated power device further includes a passivation layer, optionally, the enhancement type power device 30 includes a first passivation layer 61 formed on the first P-type semiconductor layer 33, and the depletion type power device 40 includes a second passivation layer 62 formed on the second P-type semiconductor layer 42.
Referring to fig. 5, the integrated power device further includes an isolation layer 70 formed between the first N-type semiconductor layer 32 and the second N-type semiconductor layer 41, and between the first P-type semiconductor layer 33 and the second P-type semiconductor layer 42. The isolation layer 70 extends downward and is isolated between the first barrier layer 213 and the second barrier layer 223.
In the present embodiment, on the basis of the device structure of fig. 4, passivation layers, including the first passivation layer 61 and the second passivation layer 62, may be formed by deposition. The Deposition method may include, but is not limited to, Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), and inductively coupled Enhanced Plasma Deposition (ICP-PECVD).
Then, the isolation layer 70 is formed by means of ion implantation, and optionally, the isolation layer 70 may be formed using any one of implantation elements H, He, F, Mg, Ar, Zn, Si, and the like. The lower end of the isolation layer 70 extends to and through the barrier layer to divide the barrier layer into a portion of the enhancement mode power device 30 and a portion of the depletion mode power device 40.
Referring to fig. 1 again, in the present embodiment, the enhancement-mode power device 30 further includes a first gate electrode 34 penetrating through the first passivation layer 61 and contacting the P-type nitride layer 31, and a first source electrode 35 and a first drain electrode 36 penetrating through the first passivation layer 61, the first N-type semiconductor layer 32, and the first P-type semiconductor layer 33 and contacting the first epitaxial structure 21, wherein the first source electrode 35 and the first drain electrode 36 are located at two sides of the first gate electrode 34.
The depletion mode power device 40 further includes a second gate electrode 43 penetrating the second passivation layer 62 and contacting the second P-type semiconductor layer 42, and a second source electrode 44 and a second drain electrode 45 penetrating the second passivation layer 62, the second N-type semiconductor layer 41, and the second P-type semiconductor layer 42 and contacting the second epitaxial structure 22, the second source electrode 44 and the second drain electrode 45 being located at both sides of the second gate electrode 43.
In this embodiment, referring to fig. 6, on the basis of the device structure shown in fig. 5, a photoresist is coated on the passivation layer, and ohmic metal electrode patterns are defined on the passivation layer through exposure and development, including a first source electrode pattern and a first drain electrode pattern on the first passivation layer 61, and a second source electrode pattern and a second drain electrode pattern on the second passivation layer 62.
And etching the passivation layer, the P-type semiconductor layer and the N-type semiconductor layer based on the defined ohmic metal electrode pattern, wherein the etching depth can be cut off from the surfaces of the first epitaxial structure 21 and the second epitaxial structure 22. Ohmic metal deposition is then performed based on the etched recess to form the device structure shown in fig. 6. Optionally, any one of a dry etching technique, an oxide etching technique, and a wet etching technique may be used for etching, and the embodiment is not limited in particular.
To avoid the presence of contaminants affecting the performance of the devices formed prior to ohmic metal deposition, a cleaning step may be performed to maintain the cleanliness of the device surfaces. Alternatively, cleaning may be performed using a hydrochloric acid solution or a hydrofluoric acid solution.
Referring to fig. 1, on the basis of the device structure shown in fig. 6, a gate pattern is continuously defined on the passivation layer, including a first gate pattern on the first passivation layer 61 and a second gate pattern on the second passivation layer 62. Wherein the first gate pattern is located on the P-type nitride layer 31. The first passivation layer 61 is etched based on the defined first gate pattern to a depth that is cut off from the surface of the P-type nitride layer 31. And the second passivation layer 62 is etched based on the defined second gate pattern, and the etching depth is cut off from the surface of the second P-type semiconductor layer 42. A gate metal deposition is performed based on the etched recesses to form the device structure as shown in fig. 1.
In the integrated device provided by this embodiment, the charge balance structure formed by the N-type semiconductor layer and the P-type semiconductor layer formed by the second epitaxial growth can optimize the interface state of the P-type nitride layer 31 after etching, so as to obtain excellent saturation current characteristics. In addition, a charge balance structure formed by the N-type semiconductor layer and the P-type semiconductor layer can be used as a gate dielectric layer of the depletion type power device 40, and the gate stability of the depletion type power device 40 is improved.
Referring to fig. 7, the present application further provides a method for manufacturing an enhancement-type and a depletion-type integrated power device, which is used for manufacturing the enhancement-type and the depletion-type integrated power devices, and it should be noted that the manufacturing method provided in this embodiment is not limited by the specific sequence shown in fig. 7 and described below. It should be understood that, the order of some steps in the manufacturing method described in this embodiment may be interchanged according to actual needs, or some steps may be omitted or deleted, and this embodiment is not limited herein.
Step S110, providing a substrate 10, where the substrate 10 includes a first region and a second region.
Step S120 is to form a first epitaxial structure 21 based on the first region of the substrate 10, and perform a first epitaxial growth based on the first epitaxial structure 21 to form a P-type nitride layer 31.
Step S130, performing a second epitaxial growth on a region of the first epitaxial structure 21 except the P-type nitride layer 31 to form a first N-type semiconductor layer 32 and a first P-type semiconductor layer 33, so as to form an enhancement-type power device 30, wherein a second epitaxial structure 22 is further formed on the basis of a second region of the substrate 10, and a second N-type semiconductor layer 41 and a second P-type semiconductor layer 42 formed on the second epitaxial structure 22 are further grown by the second epitaxial growth to form a depletion-type power device 40.
In this embodiment, on the basis of the above, the method for manufacturing an integrated power device further includes the following steps:
an isolation layer 70 is formed by ion implantation between the first N-type semiconductor layer 32 and the second N-type semiconductor layer 41, and between the first P-type semiconductor layer 33 and the second P-type semiconductor layer 42.
As a possible implementation manner, in this embodiment, the first P-type semiconductor layer 33 and the second P-type semiconductor layer 42 are P-type gallium nitride layers or P-type aluminum gallium nitride layers, and the first N-type semiconductor layer 32 and the second N-type semiconductor layer 41 are N-type gallium nitride layers or N-type aluminum gallium nitride layers.
It can be understood that the integrated power device shown in fig. 1 can be manufactured through the process flows given in the above steps, wherein the detailed description of the steps may refer to the description of the integrated power device in the above embodiments, and the description of the embodiment is not repeated here.
In summary, the enhancement-mode and depletion-mode integrated power device and the manufacturing method thereof provided by the embodiments of the present application include a substrate 10, an enhancement-mode power device 30 and a depletion-mode power device 40 formed on the substrate 10. The enhancement-mode power device 30 includes a first epitaxial structure 21 formed on a substrate 10, a P-type nitride layer 31 formed on the first epitaxial structure 21 by a first epitaxial growth, and a first N-type semiconductor layer 32 and a first P-type semiconductor layer 33 formed on other regions of the first epitaxial structure 21 except the P-type nitride layer 31 by a second epitaxial growth. The depletion mode power device 40 includes a second epitaxial structure 22 formed on the substrate 10, a second N-type semiconductor layer 41 and a second P-type semiconductor layer 42 formed on the second epitaxial structure 22 by a second epitaxial growth. Therefore, the charge balance structure of the N-type semiconductor layer and the P-type semiconductor layer formed based on the secondary epitaxial growth optimizes the interface state of the P-type nitride layer 31 after etching, obtains the characteristics of excellent saturation current and the like, can be used as a gate dielectric layer of the depletion type power device 40, and improves the gate stability of the depletion type power device 40.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. An enhancement mode and depletion mode integrated power device, comprising:
a substrate;
an enhancement mode power device and a depletion mode power device formed on the substrate;
wherein the enhancement mode power device comprises:
a first epitaxial structure formed on the substrate;
a P-type nitride layer formed on the first epitaxial structure by first epitaxial growth;
forming a first N-type semiconductor layer and a first P-type semiconductor layer on the other regions of the first epitaxial structure except the P-type nitride layer through second epitaxial growth;
the depletion mode power device includes:
a second epitaxial structure formed on the substrate;
and a second N-type semiconductor layer and a second P-type semiconductor layer formed on the second epitaxial structure by the second epitaxial growth.
2. The enhancement and depletion mode integrated power device according to claim 1, wherein said first and second P-type semiconductor layers are P-type gallium nitride layers or P-type aluminum gallium nitride layers, and said first and second N-type semiconductor layers are N-type gallium nitride layers or N-type aluminum gallium nitride layers.
3. The enhancement and depletion mode integrated power device according to claim 1, wherein the P-type nitride layer is a P-type gallium nitride layer or a P-type aluminum gallium nitride layer.
4. The enhancement and depletion mode integrated power device according to claim 1, further comprising:
and the isolating layers are formed between the first N-type semiconductor layer and the second N-type semiconductor layer and between the first P-type semiconductor layer and the second P-type semiconductor layer.
5. The enhancement-mode and depletion-mode integrated power device according to claim 1, further comprising:
a first passivation layer formed on the first P-type semiconductor layer;
a first gate electrode penetrating the first passivation layer and contacting the P-type nitride layer;
and a first source electrode and a first drain electrode penetrating the first passivation layer, the first N-type semiconductor layer, the first P-type semiconductor layer and contacting the first epitaxial structure, the first source electrode and the first drain electrode being located at two sides of the first gate electrode.
6. The enhancement-mode and depletion-mode integrated power device according to claim 1, wherein said depletion-mode power device further comprises:
a second passivation layer formed on the second P-type semiconductor layer;
a second gate electrode penetrating the second passivation layer and contacting the second P-type semiconductor layer;
and a second source electrode and a second drain electrode penetrating the second passivation layer, the second N-type semiconductor layer, and the second P-type semiconductor layer and contacting the second epitaxial structure, wherein the second source electrode and the second drain electrode are located at two sides of the second gate electrode.
7. The enhancement and depletion mode integrated power device according to claim 4, wherein said first epitaxial structure and said second epitaxial structure each comprise:
a buffer layer formed on the substrate;
the channel layer is formed on one side, away from the substrate, of the buffer layer and is made of a gallium nitride material;
and the barrier layer is formed on one side of the channel layer, which is far away from the buffer layer, wherein the isolation layer extends and penetrates through the barrier layer.
8. A method of fabricating an enhancement mode and depletion mode integrated power device, the method comprising:
providing a substrate, wherein the substrate comprises a first area and a second area;
forming a first epitaxial structure based on a first region of the substrate, and performing first epitaxial growth based on the first epitaxial structure to form a P-type nitride layer;
and performing second epitaxial growth on the region of the first epitaxial structure except the P-type nitride layer to form a first N-type semiconductor layer and a first P-type semiconductor layer so as to form an enhancement-type power device, wherein a second epitaxial structure is further formed on the basis of a second region of the substrate, and the second epitaxial growth is further performed to grow a second N-type semiconductor layer and a second P-type semiconductor layer which are formed on the second epitaxial structure so as to form a depletion-type power device.
9. The method of claim 8, further comprising:
and forming isolation layers between the first N-type semiconductor layer and the second N-type semiconductor layer and between the first P-type semiconductor layer and the second P-type semiconductor layer by ion implantation.
10. The method according to claim 8, wherein the first and second P-type semiconductor layers are P-type gallium nitride layers or P-type aluminum gallium nitride layers, and the first and second N-type semiconductor layers are N-type gallium nitride layers or N-type aluminum gallium nitride layers.
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