CN111337814A - Tolerance test device and method for semiconductor device - Google Patents
Tolerance test device and method for semiconductor device Download PDFInfo
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- CN111337814A CN111337814A CN202010315718.5A CN202010315718A CN111337814A CN 111337814 A CN111337814 A CN 111337814A CN 202010315718 A CN202010315718 A CN 202010315718A CN 111337814 A CN111337814 A CN 111337814A
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Abstract
The embodiment of the application provides a tolerance test device and method of a semiconductor device, a current impact unit inputs a current impact signal to a semiconductor device to be tested according to a set peak current value, a set current rise rate and a set pulse period, and after the current impact signal on the semiconductor device to be tested, the test pulse frequency of the current impact signal and the device state of the semiconductor device to be tested are tested through the test unit, a main control unit generates a current rise rate tolerance value of the semiconductor device to be tested according to the current impact signal on the semiconductor device to be tested, the test pulse frequency of the current impact signal and the device state of the semiconductor device to be tested. Therefore, the current rise rate tolerance of the semiconductor device can be effectively quantized, so that the current rise rate tolerance of the semiconductor device can be conveniently and accurately evaluated subsequently, and the failure proportion of the semiconductor device is reduced by adopting necessary means.
Description
Technical Field
The application relates to the technical field of testing of semiconductor devices, in particular to a device and a method for testing tolerance of a semiconductor device.
Background
During the application process of the high-power semiconductor device, the inventor of the application finds that the failure rate is higher due to the limited endurance capacity of the current rise rate (di/dt). Although the traditional means has related protective measures on the application circuit, it is extremely difficult to completely eliminate the phenomenon that the ultrahigh current rise rate does not occur under any special condition. Therefore, it is necessary for the semiconductor device to have an appropriate current rise rate withstanding capability within a certain range. Therefore, how to effectively quantify the current rise rate tolerance capability of the semiconductor device so as to conveniently and accurately evaluate the current rise rate tolerance capability of the semiconductor device subsequently, and further reduce the failure proportion of the semiconductor device by adopting necessary measures is a technical problem to be solved in the field.
Disclosure of Invention
In order to overcome the above-mentioned deficiencies in the prior art, the present application aims to provide a tolerance testing apparatus and method for a semiconductor device, which can effectively quantify the current rise rate tolerance capability of the semiconductor device, so as to subsequently and accurately evaluate the current rise rate tolerance capability of the semiconductor device, and further reduce the failure ratio of the semiconductor device by adopting necessary measures.
In order to achieve the above purpose, the embodiments of the present application employ the following technical solutions:
according to a first aspect of embodiments of the present application, an embodiment of the present application provides a tolerance test apparatus for a semiconductor device, which is in communication connection with a computer device, and includes:
the current impact unit is used for inputting a current impact signal to the semiconductor device to be tested according to a set peak current value, a set current rise rate and a set pulse period;
the test unit is used for testing a current surge signal on the semiconductor device to be tested, the test pulse frequency of the current surge signal and the device state of the semiconductor device to be tested;
and the main control unit is respectively electrically connected with the current impact unit and the test unit, is in communication connection with the computer equipment through the communication unit, is used for configuring a set peak current value, a set current rise rate and a set pulse period which are sent by the computer equipment to the current impact unit, generating a current rise rate tolerance value of the semiconductor device to be tested according to a current impact signal on the semiconductor device to be tested, the test pulse frequency of the current impact signal and the device state of the semiconductor device to be tested, and sending the current rise rate tolerance value to the computer equipment through the communication unit, wherein the device state comprises an effective state and a failure state.
In one possible implementation of the first aspect, the current surge unit includes:
the peak current control circuit is used for inputting the current impact signal of the set peak current value to the semiconductor device to be tested;
the di/dt control circuit is electrically connected with the peak current control circuit and is used for controlling the current rise rate of the current impact signal according to the set current rise rate;
and the trigger current control circuit is used for controlling the pulse period of the pulse trigger signal of the current impact signal according to the set pulse period.
In one possible implementation manner of the first aspect, the trigger current control circuit includes:
the trigger current control sub-circuit is used for controlling the pulse period of a pulse trigger signal of a current impact signal of the trigger current control sub-circuit according to the set pulse period.
In one possible implementation of the first aspect, the test unit comprises:
the test pulse counting circuit is used for testing the test pulse times of the current impact signal;
the impact current test circuit is used for testing a current impact signal on the semiconductor device to be tested;
and the device state testing circuit is used for testing the device state of the semiconductor device to be tested.
In one possible implementation of the first aspect, the test unit further includes:
the peak current test circuit is used for testing the peak current of the current impact signal;
the trigger current test circuit is used for testing a pulse trigger signal of a current impact signal on the semiconductor device to be tested;
the main control unit is further used for determining whether the current surge unit is abnormal or not according to the peak current of the current surge signal and a pulse trigger signal of the current surge signal on the semiconductor device to be tested, and outputting an abnormal result when the current surge unit is determined to be abnormal.
In a possible implementation manner of the first aspect, the main control unit is specifically configured to:
judging whether the device state corresponding to the current impact signal tested by the test unit is a failure state or not;
when the device state corresponding to the current impact signal is in a failure state when the current impact signal is tested at any time, acquiring the corresponding test pulse frequency before the current impact signal is tested at the time, and determining the test pulse frequency as the current rise rate tolerance value of the semiconductor device to be tested;
when the device state corresponding to the current impact signal is tested to be an effective state, whether the device state corresponding to the next time when the current impact signal is tested to be a failure state or not is continuously judged, until the device state corresponding to the current impact signal is tested to be the failure state, the corresponding test pulse frequency before the current impact signal is tested to be obtained, and the test pulse frequency is determined to be the current rise rate tolerance value of the semiconductor device to be tested.
In a possible implementation manner of the first aspect, the display device further includes a display unit electrically connected to the main control unit;
when the test pulse frequency reaches a set frequency and the device state of the semiconductor device to be tested is an effective state, the main control unit controls the display unit to display that the semiconductor device to be tested passes the test; and
and when the device state of the semiconductor device to be tested is in a failure state before the test pulse frequency does not reach the set frequency, controlling the display unit to display that the semiconductor device to be tested does not pass the test and displaying the test pulse frequency of the device state of the semiconductor device to be tested before the device state is in the failure state.
In a possible implementation manner of the first aspect, the main control unit is further configured to generate a trade-off value of the current rise rate tolerance value of the semiconductor device under test according to the current rise rate tolerance value of the semiconductor device under test respectively under different set peak current values, set current rise rates, and set pulse periods.
In a possible implementation manner of the first aspect, the set peak current value is determined according to a rated current value of the semiconductor device under test, and the set current rise rate and the set pulse period are determined according to a device usage scenario of the semiconductor device under test.
According to a second aspect of the embodiments of the present application, there is provided a method for testing tolerance of a semiconductor device, which is applied to the device for testing tolerance of a semiconductor device described in any one of the possible implementation manners in the first aspect, the method including:
inputting a current impact signal to the semiconductor device to be tested according to a set peak current value, a set current rise rate and a set pulse period;
testing a current impact signal on the semiconductor device to be tested, the test pulse frequency of the current impact signal and the device state of the semiconductor device to be tested;
generating a current rise rate tolerance value of the semiconductor device to be tested according to the current impact signal on the semiconductor device to be tested, the test pulse frequency of the current impact signal and the device state of the semiconductor device to be tested, and sending the current rise rate tolerance value to the computer equipment through the communication unit, wherein the device state comprises an effective state and a failure state.
Based on any one of the above aspects, with the implementation manner of the embodiment of the present application, after the current impact unit inputs the current impact signal to the semiconductor device to be tested according to the set peak current value, the set current rise rate, and the set pulse period, and the test unit tests the current impact signal on the semiconductor device to be tested, the test pulse frequency of the current impact signal, and the device state of the semiconductor device to be tested, the main control unit generates the current rise rate tolerance value of the semiconductor device to be tested according to the current impact signal on the semiconductor device to be tested, the test pulse frequency of the current impact signal, and the device state of the semiconductor device to be tested. Therefore, the current rise rate tolerance of the semiconductor device can be effectively quantized, so that the current rise rate tolerance of the semiconductor device can be conveniently and accurately evaluated subsequently, and the failure proportion of the semiconductor device is reduced by adopting necessary means.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and it will be apparent to those skilled in the art that other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is one of schematic block diagrams of an application scenario of a tolerance testing apparatus for a semiconductor device according to an embodiment of the present application;
fig. 2 is a schematic diagram illustrating a principle of a method for testing tolerance of a semiconductor device according to an embodiment of the present application;
fig. 3 is a second schematic block diagram of an application scenario of a tolerance testing apparatus for a semiconductor device according to an embodiment of the present application;
fig. 4 is a third schematic block diagram of an application scenario of a tolerance testing apparatus for a semiconductor device according to an embodiment of the present application;
fig. 5 is a fourth schematic block diagram of an application scenario of the tolerance testing apparatus for a semiconductor device according to the embodiment of the present application;
fig. 6 is a fifth schematic block diagram of an application scenario of the tolerance testing apparatus for a semiconductor device according to the embodiment of the present application;
fig. 7 is a sixth schematic block diagram of an application scenario of a tolerance testing apparatus for a semiconductor device according to an embodiment of the present application;
fig. 8 is a schematic flowchart of a method for testing tolerance of a semiconductor device according to an embodiment of the present application.
Icon: 10-a tolerance test device for a semiconductor device;
110-a current surge unit; 112-peak current control circuit; 114-di/dt control circuitry; 116-trigger current control circuit; 1162-trigger current control subcircuit; 1164-trigger period control subcircuit;
120-a test unit; 121-test pulse counting circuit; 122-a surge current test circuit; 123-device state test circuit; 124-peak current test circuit; 125-trigger current test circuit;
130-a master control unit; 140-a communication unit; 150-a display unit;
20-a semiconductor device under test; 30-a computer device.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
Referring to fig. 1, an embodiment of the present application provides a tolerance test apparatus 10 for a semiconductor device, where the tolerance test apparatus 10 for a semiconductor device is communicably connected to a computer device 30. The computer device 30 may be any electronic device with data calculation processing capability, and is not limited in particular.
As shown in fig. 1, the tolerance testing apparatus 10 for a semiconductor device may include a current surge unit 110, a testing unit 120, a main control unit 130 and a communication unit 140, wherein the main control unit 130 is electrically connected to the current surge unit 110 and the testing unit 120, respectively, and is communicatively connected to the computer device 30 through the communication unit 140.
In order to solve the technical problem in the foregoing background art, the current rush unit 110 may input a current rush signal to the semiconductor device under test 20 according to the set peak current value, the set current rise rate, and the set pulse period, so that the current rise rate tolerance of the semiconductor power device under test may be continuously tested.
The set peak current value may be an equivalent surge current value corresponding to the input of the highest surge voltage, the set current increase rate di/dt may be a current value that increases per unit time, and the set pulse period may be an interval period each time a current surge signal is input to the semiconductor device 20 to be tested.
The main control unit 130 may use an embedded system to input and control the above parameters (e.g., the set peak current value, the set current rise rate, and the set pulse period), for example, by interacting with the computer device 30, after the set peak current value, the set current rise rate, and the set pulse period are configured by the computer device 30, the main control unit 130 configures the set peak current value, the set current rise rate, and the set pulse period sent by the computer device 30 to the current impact unit 110.
In the above process, the test unit 120 may simultaneously test the current rush signal on the semiconductor device 20 to be tested, the number of test pulses of the current rush signal, and the device state of the semiconductor device 20 to be tested. At this time, the main control unit 130 may generate a current rise rate tolerance value of the semiconductor device 20 to be tested according to the current surge signal on the semiconductor device 20 to be tested, the number of test pulses of the current surge signal, and the device state of the semiconductor device 20 to be tested, and transmit the current rise rate tolerance value to the computer device 30 through the communication unit 140.
The device states may include, among other things, an active state and a failed state. For example, when the semiconductor device 20 under test is in an active state, it indicates that the semiconductor device 20 under test can currently tolerate the set current rise rate, and when the semiconductor device 20 under test is in a failed state, it indicates that the semiconductor device 20 under test cannot currently tolerate the set current rise rate.
Based on the above description, the various parameters described in the present embodiment are exemplified below with reference to fig. 2. As shown in fig. 2, Im (-Im) may represent a set peak current value of the current rush signal, di/dt may represent a set current rise rate, and T may represent a set pulse period, wherein, when the semiconductor device under test 30 is a triac, a bidirectional test pulse signal may be provided within one set pulse period. For example, a positive test pulse signal and a negative test pulse signal. When the semiconductor device 30 to be tested is a triac, there is only a negative test pulse signal in one set pulse period. There is a current surge signal in each pulse cycle shown in fig. 2 when the semiconductor device 20 under test is in the active state and no current surge signal in each pulse cycle shown in fig. 2 when the semiconductor device 20 under test is in the inactive state.
Based on the above design, the tolerance test apparatus 10 for a semiconductor device according to the present embodiment inputs a current surge signal to the semiconductor device 20 to be tested through the current surge unit 110 according to the set peak current value, the set current rise rate and the set pulse period, and after the test unit 120 tests the current surge signal on the semiconductor device 20 to be tested, the test pulse number of the current surge signal and the device state of the semiconductor device 20 to be tested, the main control unit 130 generates the current rise rate tolerance value of the semiconductor device 20 to be tested according to the current surge signal on the semiconductor device 20 to be tested, the test pulse number of the current surge signal and the device state of the semiconductor device 20 to be tested. Therefore, the current rise rate tolerance of the semiconductor device can be effectively quantized, so that the current rise rate tolerance of the semiconductor device can be conveniently and accurately evaluated subsequently, and the failure proportion of the semiconductor device is reduced by adopting necessary means.
It is worth noting that, in one possible embodiment, the set peak current value may be determined according to a rated current value of the semiconductor device 20 to be tested. For example, the set peak current value is usually much larger than the rated current value of the semiconductor device 20 to be tested, so that the limit endurance of the semiconductor device 20 to be tested is possible to be tested. The set current rise rate and the set pulse period may be determined according to a device usage scenario of the semiconductor device 20 under test. For example, the semiconductor device 20 to be tested is used in different device usage scenarios, and the specific usage intensity and the usage duration thereof are different, and the set current rise rate and the set pulse period can be correspondingly and flexibly set, so as to meet the specific requirements of different device usage scenarios.
In one possible embodiment, the specific structure of the current surge unit 110 will be described below with reference to fig. 3. As shown in fig. 3, the current rush unit 110 may include a peak current control circuit 112, a di/dt control circuit 114 electrically connected to the peak current control circuit 112, and a trigger current control circuit 116. The peak current control circuit 112 may input a current rush signal with a set peak current value to the semiconductor device 20 to be tested, the di/dt control circuit 114 may control a current rise rate of the current rush signal according to the set current rise rate, and the trigger current control circuit 116 may control a pulse period of a pulse trigger signal of the current rush signal according to a set pulse period.
For example, assuming that the current rise rate is set to a, the pulse period is set to b, and the peak current value is set to c, the di/dt control circuit 114 may control the current rush signal to continuously rise according to the current rise rate of a, and the trigger current control circuit 116 may control the current rush signal to generate the pulse trigger signal every b time intervals. After the pulse trigger signal is generated, the peak current control circuit 112 may input a current surge signal with a current value of c to the semiconductor device 20 under test.
In one possible implementation manner, referring to fig. 4, an exemplary structure of the trigger current control circuit 116, the trigger current control circuit 116 may include a trigger current control sub-circuit 1162 and a trigger period control sub-circuit 1164 electrically connected to the trigger current control sub-circuit 1162, and the trigger period control sub-circuit 1164 may be configured to control a pulse period of a pulse trigger signal of a current surge signal of the trigger current control sub-circuit 1162 according to a set pulse period.
For example, the trigger period control sub-circuit 1164 may employ a timing circuit and determine whether each pulse period is currently reached or whether each pulse period is ended by means of real-time timing, so as to control the pulse period of the pulse trigger signal of the current surge signal triggering the current control sub-circuit 1162 according to the arrival signal and the end signal of each pulse period.
In one possible implementation, as shown in fig. 5, the test unit 120 may include a test pulse counting circuit 121, a rush current test circuit 122, and a device state test circuit 123. The test pulse counting circuit 121 may be configured to test the number of test pulses of the current surge signal, the surge current testing circuit 122 may be configured to test the current surge signal on the semiconductor device 20 to be tested, and the device state testing circuit 123 may be configured to test the device state of the semiconductor device 20 to be tested.
For example, the test pulse counting circuit 121 may adopt a counting circuit, and the test pulse counting circuit 121 performs counting every time the semiconductor device 20 to be tested is impacted by a current impact signal, so as to continuously count the number of times the semiconductor device 20 to be tested accumulates the current impact signal. The inrush current test circuit 122 may employ a hall sensor to sense a current inrush signal on the semiconductor device 20 under test.
In addition, in a possible implementation manner, referring to fig. 6, the test unit 120 may further include a peak current test circuit 124 and a trigger current test circuit 125, the peak current test circuit 124 may be used for testing a peak current of the current surge signal, and the trigger current test circuit 125 may be used for testing a pulse trigger signal of the current surge signal on the semiconductor device 20 to be tested.
On this basis, in order to monitor the abnormal state of the entire surge process, the main control unit 130 may further determine whether there is an abnormality in the current surge unit 110 according to the peak current of the current surge signal and the pulse trigger signal of the current surge signal on the semiconductor device 20 to be tested, and output an abnormal result when it is determined that there is an abnormality in the current surge unit 110.
For example, after the pulse trigger signal is generated, if the peak current of the current rush signal is lower than the set current value range, it may be determined that there is an abnormality in the current rush unit 110 and an abnormal result may be output.
In one possible embodiment, an exemplary embodiment is provided below to further illustrate the calculation of the current rise rate endurance value of the semiconductor device 20 under test.
For example, the main control unit 130 may specifically determine whether the device state corresponding to the current impact signal tested by the test unit 120 each time is the failure state, and when the device state corresponding to the current impact signal tested at any time is the failure state, obtain the number of test pulses corresponding to the current impact signal tested this time, and determine the number of test pulses as the current rise rate tolerance value of the semiconductor device 20 to be tested.
For another example, when the device state corresponding to the current impact signal is in the valid state when the current impact signal is tested, it is continuously determined whether the device state corresponding to the next test of the current impact signal is in the invalid state, until the device state corresponding to the current impact signal is in the invalid state when the current impact signal is tested, the number of test pulses corresponding to the current impact signal before the current impact signal is tested is obtained, and the number of test pulses is determined as the current rise rate tolerance value of the semiconductor device 20 to be tested.
For example, when the number of test pulses reaches 11 thThen, the judgment test unit 120 tests the current impact signal I at the 11 th time11Whether the corresponding device state is a failed state. When the current surge signal I11When the corresponding device state is a failure state, the current impact signal I is tested at the time11The number of test pulses is 10 before, and the current rise rate tolerance value of the semiconductor device 20 to be tested can be determined to be 10.
For example, when the current surge signal I11When the corresponding device state is the effective state, continuously judging that the current impact signal I is tested at the 12 th time12Whether the corresponding device state is a failure state or not. If the 16 th test has the current impact signal I16When the corresponding device state is a failure state, the current impact signal I is tested at the time16If the number of test pulses is 15, the current rise rate tolerance value of the semiconductor device 20 to be tested can be determined to be 15.
On the basis of the above description, the present embodiment can also appropriately set the relevant test passing conditions to further evaluate the current rise rate endurance value of the semiconductor device 20 under test. For example, in one possible embodiment, referring to fig. 7, the tolerance test apparatus 10 for a semiconductor device may further include a display unit 150 electrically connected to the main control unit 130.
Therefore, the main control unit 130 may control the display unit 150 to display that the semiconductor device 20 to be tested passes the test when the number of test pulses reaches the set number and the device status of the semiconductor device 20 to be tested is in the valid state. Also, when the device state of the semiconductor device 20 to be tested is in the failure state before the number of test pulses does not reach the set number, the display unit 150 may be controlled to display that the semiconductor device 20 to be tested does not pass the test and to display the number of test pulses before the device state of the semiconductor device 20 to be tested is in the failure state.
For example, assuming that the set number of times is 10, when the test pulse number reaches 10 times and the device state of the semiconductor device 20 under test is the valid state, the control display unit 150 displays that the semiconductor device 20 under test passes the test. For another example, when the number of test pulses reaches 8 times, the device state of the semiconductor device 20 under test is determined to be a failure state, and at this time, the display unit 150 is controlled to display that the semiconductor device 20 under test fails to pass the test, and to display that the number of test pulses of the device state of the semiconductor device 20 under test before the device state is determined to be the failure state is 8 times.
It is understood that, in the actual testing process, in order to avoid unnecessary testing work, when the device status of the semiconductor device 20 under test is in the failure state, the main control unit 130 may control the current impact unit 110 to stop impacting the semiconductor device 20 under test.
In one possible embodiment, it is considered that in the actual testing process, the current rise rate tolerance value of the semiconductor device 20 to be tested may be tested in different groups for a plurality of times by using different set peak current values, set current rise rates and current rise rate tolerance values under set pulse periods, so that a plurality of groups of data may be obtained. In order to further accurately evaluate the current rise rate tolerance value of the semiconductor device 20 to be tested, the main control unit 130 may be further configured to generate a weighted value of the current rise rate tolerance value of the semiconductor device 20 to be tested according to the current rise rate tolerance values of the semiconductor device 20 to be tested under different set peak current values, set current rise rates, and set pulse periods, respectively.
For example, as one possible example, each different set of the set peak current value, the set current rise rate, and the current rise rate tolerance value at the set pulse period may construct a corresponding trade-off matrix, and the trade-off matrix may correspond to a device usage scenario corresponding to each set of the current rise rate tolerance values. Therefore, the current rise rate tolerance adjustment parameters of a plurality of device use scenes can be output according to the weighing matrix, the distribution weight of each current rise rate tolerance adjustment parameter in the plurality of current rise rate tolerance adjustment parameters in the weighing matrix is obtained, and the distribution weight sequence of each current rise rate tolerance adjustment parameter is obtained from the preset distribution weight information table according to the distribution weight of each current rise rate tolerance adjustment parameter. On this basis, according to the adjustment parameter range interval of the current rise rate tolerance adjustment parameter associated with each current rise rate tolerance adjustment parameter, the distribution weight information of the current rise rate tolerance adjustment parameter may be selected from the distribution weight sequence corresponding to the current rise rate tolerance adjustment parameter.
Next, a distribution weight lower limit value of each current rise rate tolerance adjustment parameter may be calculated according to an adjustment parameter range interval of each current rise rate tolerance adjustment parameter, and then a pre-configured query database may be queried according to the distribution weight lower limit value of each current rise rate tolerance adjustment parameter to obtain a plurality of parameter components of the current rise rate tolerance adjustment parameter.
Thus, the multiplication operation may be performed on each corresponding current rise rate tolerance value according to the parameter component of each current rise rate tolerance adjustment parameter, and the weighting processing may be performed on the multiplication result, so that the trade-off value of the current rise rate tolerance value of the semiconductor device 20 to be tested may be obtained.
Based on the same inventive concept, please refer to fig. 8 in combination, the embodiment of the present application further provides a method for testing the tolerance of a semiconductor device, which may be performed by the tolerance testing apparatus 10 of the semiconductor device in the above embodiment. It should be noted that, the detailed steps of the method for testing tolerance of a semiconductor device provided in this embodiment may refer to the description of relevant parts in the above embodiments, and this embodiment will not be described in detail. The method for testing the tolerance of the semiconductor device will be briefly described below.
In step S110, a current surge signal is input to the semiconductor device 20 according to the set peak current value, the set current rise rate, and the set pulse period.
Step S120, testing the current surge signal on the semiconductor device 20 to be tested, the number of test pulses of the current surge signal, and the device state of the semiconductor device 20 to be tested.
Step S130 is to generate a current rise rate tolerance value of the semiconductor device 20 to be tested according to the current surge signal on the semiconductor device 20 to be tested, the test pulse frequency of the current surge signal, and the device state of the semiconductor device 20 to be tested, and send the current rise rate tolerance value to the computer device 30 through the communication unit 140, where the device state includes an active state and a failure state.
For details of the above steps, reference may be made to the above description of the tolerance test apparatus 10 for a semiconductor device, and details thereof are not repeated here.
Based on the above steps, the tolerance test method for the semiconductor device provided in this embodiment can effectively quantify the current rise rate tolerance capability of the semiconductor device, so as to subsequently and accurately evaluate the current rise rate tolerance capability of the semiconductor device, and further reduce the failure proportion of the semiconductor device by adopting necessary measures.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (10)
1. A tolerance test device for a semiconductor device, which is connected to a computer device in communication, comprising:
the current impact unit is used for inputting a current impact signal to the semiconductor device to be tested according to a set peak current value, a set current rise rate and a set pulse period;
the test unit is used for testing a current surge signal on the semiconductor device to be tested, the test pulse frequency of the current surge signal and the device state of the semiconductor device to be tested;
and the main control unit is respectively electrically connected with the current impact unit and the test unit, is in communication connection with the computer equipment through the communication unit, is used for configuring a set peak current value, a set current rise rate and a set pulse period which are sent by the computer equipment to the current impact unit, generating a current rise rate tolerance value of the semiconductor device to be tested according to a current impact signal on the semiconductor device to be tested, the test pulse frequency of the current impact signal and the device state of the semiconductor device to be tested, and sending the current rise rate tolerance value to the computer equipment through the communication unit, wherein the device state comprises an effective state and a failure state.
2. The tolerance test device for a semiconductor device according to claim 1, wherein the current rush unit comprises:
the peak current control circuit is used for inputting the current impact signal of the set peak current value to the semiconductor device to be tested;
the di/dt control circuit is electrically connected with the peak current control circuit and is used for controlling the current rise rate of the current impact signal according to the set current rise rate;
and the trigger current control circuit is used for controlling the pulse period of the pulse trigger signal of the current impact signal according to the set pulse period.
3. The tolerance test device for a semiconductor device according to claim 2, wherein the trigger current control circuit comprises:
the trigger current control sub-circuit is used for controlling the pulse period of a pulse trigger signal of a current impact signal of the trigger current control sub-circuit according to the set pulse period.
4. The tolerance test apparatus for a semiconductor device according to claim 1, wherein the test unit includes:
the test pulse counting circuit is used for testing the test pulse times of the current impact signal;
the impact current test circuit is used for testing a current impact signal on the semiconductor device to be tested;
and the device state testing circuit is used for testing the device state of the semiconductor device to be tested.
5. The tolerance test device for a semiconductor device according to claim 4, wherein the test unit further comprises:
the peak current test circuit is used for testing the peak current of the current impact signal;
the trigger current test circuit is used for testing a pulse trigger signal of a current impact signal on the semiconductor device to be tested;
the main control unit is further used for determining whether the current surge unit is abnormal or not according to the peak current of the current surge signal and a pulse trigger signal of the current surge signal on the semiconductor device to be tested, and outputting an abnormal result when the current surge unit is determined to be abnormal.
6. The device for testing tolerance of a semiconductor device according to any one of claims 1 to 5, wherein the main control unit is specifically configured to:
judging whether the device state corresponding to the current impact signal tested by the test unit is a failure state or not;
when the device state corresponding to the current impact signal is in a failure state when the current impact signal is tested at any time, acquiring the corresponding test pulse frequency before the current impact signal is tested at the time, and determining the test pulse frequency as the current rise rate tolerance value of the semiconductor device to be tested;
when the device state corresponding to the current impact signal is tested to be an effective state, whether the device state corresponding to the next time when the current impact signal is tested to be a failure state or not is continuously judged, until the device state corresponding to the current impact signal is tested to be the failure state, the corresponding test pulse frequency before the current impact signal is tested to be obtained, and the test pulse frequency is determined to be the current rise rate tolerance value of the semiconductor device to be tested.
7. The device for testing tolerance of a semiconductor device according to claim 6, further comprising a display unit electrically connected to the main control unit;
when the test pulse frequency reaches a set frequency and the device state of the semiconductor device to be tested is an effective state, the main control unit controls the display unit to display that the semiconductor device to be tested passes the test; and
and when the device state of the semiconductor device to be tested is in a failure state before the test pulse frequency does not reach the set frequency, controlling the display unit to display that the semiconductor device to be tested does not pass the test and displaying the test pulse frequency of the device state of the semiconductor device to be tested before the device state is in the failure state.
8. The device according to any one of claims 1 to 5, wherein the main control unit is further configured to generate a trade-off value of the current rise rate tolerance value of the semiconductor device to be tested according to the current rise rate tolerance values of the semiconductor device to be tested at different set peak current values, set current rise rates, and set pulse periods, respectively.
9. The device for testing tolerance of a semiconductor device according to claim 1, wherein the set peak current value is determined in accordance with a rated current value of the semiconductor device under test, and the set current rise rate and the set pulse period are determined in accordance with a device usage scenario of the semiconductor device under test.
10. A method for testing the tolerance of a semiconductor device, which is applied to the semiconductor device tolerance testing apparatus according to any one of claims 1 to 9, the method comprising:
inputting a current impact signal to the semiconductor device to be tested according to a set peak current value, a set current rise rate and a set pulse period;
testing a current impact signal on the semiconductor device to be tested, the test pulse frequency of the current impact signal and the device state of the semiconductor device to be tested;
generating a current rise rate tolerance value of the semiconductor device to be tested according to the current impact signal on the semiconductor device to be tested, the test pulse frequency of the current impact signal and the device state of the semiconductor device to be tested, and sending the current rise rate tolerance value to the computer equipment through the communication unit, wherein the device state comprises an effective state and a failure state.
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