CN111337153A

CN111337153A - Temperature sensor and temperature analog signal digitization method

Info

Publication number: CN111337153A
Application number: CN202010163468.8A
Authority: CN
Inventors: 蒋磊; 孙铭阳
Original assignee: Beijing Zhongke Yinxin Technology Co ltd
Current assignee: Jiangsu Yinhe Microelectronics Co.,Ltd.
Priority date: 2020-03-10
Filing date: 2020-03-10
Publication date: 2020-06-26
Anticipated expiration: 2040-03-10
Also published as: CN111337153B

Abstract

The invention discloses a temperature sensor and a method, wherein the temperature sensor comprises a controllable sampling circuit, an integrating circuit and a digital output circuit; the controllable sampling circuit is electrically connected with the input end of the integrating circuit, the controllable sampling circuit is also electrically connected with the output end of the integrating circuit, and the output end of the integrating circuit is electrically connected with the digital output circuit; the temperature sensor has a sigma delta ADC mode for generating an Mth bit temperature data to an Nth bit temperature data, and a SARADC mode for generating an N-1 th bit temperature data to a 1 st bit temperature data; the duty cycle T ═ kT of the temperature sensor in the SARADC mode₀K is an integer greater than 0 and less than a predetermined value, T₀N-1 is more than or equal to 0 and less than M is the clock period of the integrating circuit, and M is the resolution of the temperature sensor; the invention can greatly improve and reduce the conversion rate under the premise of unchanged temperature conversion precision and circuit quiescent currentThe average power consumption of the circuit is reduced.

Description

Temperature sensor and temperature analog signal digitization method

Technical Field

The invention belongs to the technical field of integrated circuit design, and particularly relates to a temperature sensor and a temperature analog signal digitization method.

Background

With the continuous expansion of application scenarios, the demand for high-resolution and low-power consumption temperature sensors is greatly increased, and in the mainstream high-resolution temperature sensor structure, a Σ Δ ADC is generally adopted to convert an analog quantity with temperature information into a digital output, and such an ADC can achieve an ultra-high resolution greater than 20 bits to provide a temperature conversion accuracy less than 0.01 ℃, but such a sensor usually comes at the cost of an excessively low conversion rate, and at the same time, a relatively high average power consumption is accompanied.

A conventional BJT-based temperature sensor circuit configuration is shown in fig. 1. In the figure V_BE、ΔV_BEGenerated by BJTs biased at appropriate currents; c_S、αC_STo respectively correspond to V_BE、ΔV_BESampling capacitor of C_IIs an integrating capacitance, [ phi ]₁、Φ₂Respectively corresponding to the sampling and integration periods of the Integrator; when the Comparator result is 1, the integrator integrates-V_BEOtherwise, the integral α Δ V is integrated_BE(ii) a The N-bit Counter here acts as a down-sampling filter (N is the resolution of the Σ Δ ADC), whose digital output quantity D is_OUTRepresenting the density of 1 in the input code stream bs, the duty ratio of the output code stream of the comparator obtained by charge conservation is:

wherein, V_BE+αΔV_BEIs a reference voltage V_refThus μ is a PTAT amount that can be used to characterize temperature.

The single temperature transition time of the temperature sensor shown in FIG. 1 is T_conv.＝T₀*2^NWherein T is₀Is the clock period of the circuit; when the value of N is large, too long a single temperature transition time is generated.

Disclosure of Invention

In view of the above, the present invention is directed to a temperature sensor and a method for digitizing a temperature analog signal, so as to shorten a time for converting the temperature analog signal while ensuring a relatively high resolution of the temperature sensor.

In order to achieve the above object, a temperature sensor according to an aspect of the present invention includes: the circuit comprises a controllable sampling circuit, an integrating circuit and a digital output circuit; the controllable sampling circuit is electrically connected with the input end of the integrating circuit, the controllable sampling circuit is also electrically connected with the output end of the integrating circuit, and the integrating circuitThe output end of the branch circuit is electrically connected with the digital output circuit; the temperature sensor has a sigma delta ADC mode for generating an Mth bit temperature data to an Nth bit temperature data, and a SARADC mode for generating an N-1 th bit temperature data to a 1 st bit temperature data; the duty cycle T ═ kT of the temperature sensor in the SARADC mode₀K is an integer greater than 0 and less than a predetermined value, T₀N-1 is more than or equal to 0 and less than M is the clock period of the integrating circuit, and M is the resolution of the temperature sensor;

when the temperature sensor is in the SARADC mode, the controllable sampling circuit is used for providing sampling signals to the integrating circuit in each working period, and adjusting the size and the feedback mode of an integrating capacitor of the integrating circuit, and the integrating circuit is used for generating a differential target voltage value delta V according to the sampling signals in each working period; and the digital output circuit is used for generating temperature data D forming binary digital temperature according to the differential target voltage value in each working period.

In the above scheme, the integration circuit generates the differential target voltage value Δ V in the 1 st duty cycle of the sar adc mode₁＝2ΔV_ΣΔADC±V_ref，ΔV_ΣΔADCFor a differential target voltage value, V, generated by the integrating circuit at the end of the last duty cycle of the sigma delta ADC mode_refIs a reference voltage; the digital output circuit is used for outputting N-1 bit temperature data according to the differential target voltage value of the 1 st working period of the SARADC mode in the 1 st working period of the SARADC mode; and/or the presence of a gas in the gas,

a differential target voltage value Δ V generated by the integration circuit at the end of the ith duty cycle of the SARADC mode_i＝2ΔV_i-1±V_ref，ΔV_i-1The digital output circuit is used for generating a differential target voltage value at the end of the i-1 working period of the SARADC mode according to the differential target voltage value delta V generated by the integrating circuit at the end of the i-1 working period of the SARADC mode in the i-th working period of the SARADC mode_iGenerating N-i bit temperature data; i is more than or equal to 2 and less than or equal to N-1.

In the above solution, each duty cycle of the temperature sensor in the sar adc mode includes a first period, a second period, a third period and a fourth period;

when Δ V_t>When the voltage value of the temperature sensor is 0, in the t +1 working period of the SARADC mode, the differential voltage value output by the integrating circuit in the first period is delta V_t-V_BE(ii) a The differential voltage value output by the integration circuit in the second period is 2(Δ V)_t-V_BE) (ii) a The differential voltage value output by the integration circuit in the third period is 2(Δ V)_t-V_BE)-αΔV_BEThe differential voltage value output by the integrating circuit in the fourth period is 2 delta V_t-V_ref；

When Δ V_tWhen the voltage is less than 0, the differential voltage value output by the integrating circuit in the first period is delta V_t+V_BE(ii) a The differential voltage value output by the integration circuit in the second period is 2(Δ V)_t+V_BE) (ii) a The differential voltage value output by the integration circuit in the third period is 2(Δ V)_t-V_BE)+αΔV_BEThe differential voltage value output by the integrating circuit in the fourth period is 2 delta V_t+V_ref。

In the above scheme, the controllable sampling circuit includes a first sampling sub-circuit, a second sampling sub-circuit, a first switching sub-circuit and a second switching sub-circuit, and the digital output circuit includes a comparator and a counter; the first switch sub-circuit and the second switch sub-circuit are used for controlling the integrating circuit to be in a first feedback mode and a second feedback mode; the analog signal generating circuit is used for generating two analog temperature signals V_BEAnd Δ V_BEAnd respectively output to the first sampling sub-circuit and the second sampling sub-circuit;

the first sampling sub-circuit is electrically connected with a first input end of the integrating circuit, the second sampling sub-circuit is electrically connected with a second input end of the integrating circuit, a first output end of the integrating circuit is electrically connected with a second output end of the comparator, a second output end of the integrating circuit is electrically connected with a first output end of the comparator, and an output end of the comparator is electrically connected with the counter; the first sampling sub-circuit is also electrically connected with the second output end of the integrating circuit through the first switching sub-circuit, and the second sampling sub-circuit is also electrically connected with the second output end of the integrating circuit through the second switching sub-circuit;

the first and second switch sub-circuits are configured to be in an off state during the first, third and fourth periods and to be in an on state during the second period; the first sampling sub-circuit is used for sampling the temperature analog signal at each time interval to obtain a first voltage V_BEThe second sampling sub-circuit is used for sampling the temperature analog signal at each time interval to obtain a second voltage delta V_BE(ii) a The total sampling capacitance of the first sampling sub-circuit in the second period is smaller than the reference sampling capacitance of the first sampling sub-circuit, and the total sampling capacitance of the second sampling sub-circuit in the second period is smaller than the reference sampling capacitance of the second sampling sub-circuit;

the comparator is used for determining temperature data D according to the differential target voltage value delta V in the fourth period; the counter is used for generating temperature data forming binary digital temperature according to the temperature data in the fourth time period.

In the above scheme, the reference sampling capacitance of the first sampling sub-circuit and the reference sampling capacitance of the second sampling sub-circuit are α C_S；

The total capacitance of the first sampling sub-circuit in the second period and the total capacitance of the second sampling sub-circuit in the second period are α C_S-0.5C_I；

The integration capacitance of the integration circuit in the second period is 1.5C_IThe reference integral capacitance of the integral circuit is C_I。

The embodiment of the invention also provides a temperature analog signal digitization method which is applied to the temperature sensor in any one of the schemes; the temperature sensor has a first circuit for generating a first voltageA sigma delta ADC mode from M-bit temperature data to N-th bit temperature data, wherein the temperature sensor has a duty cycle T ═ kT in the SARADC mode₀K is an integer greater than 0 and less than a predetermined value, T₀N-1 is more than or equal to 0 and less than M is the clock period of the integrating circuit, and M is the resolution of the temperature sensor;

the temperature analog signal digitization method comprises the following steps:

in the sigma delta ADC mode, the temperature sensor generates Mth-bit temperature data to Nth-bit temperature data according to the temperature analog signal; in the SARADC mode, the temperature sensor generates the temperature data from the (N-1) th bit to the (1) th bit according to the generated temperature data; wherein the content of the first and second substances,

when the temperature sensor is in a SARADC mode, the controllable sampling circuit provides sampling signals to the integrating circuit in each working period, and the size and the feedback mode of a sampling capacitor of the integrating circuit are adjusted; the integrating circuit forms a differential target voltage value delta V according to the sampling signal in each working period; and the digital output circuit generates temperature data D forming binary digital temperature according to the differential target voltage value in each working period.

In the above scheme, the integration circuit generates the differential target voltage value Δ V in the 1 st duty cycle of the sar adc mode₁＝2ΔV_ΣΔADC±V_ref，ΔV_ΣΔADCFor a differential target voltage value, V, generated by the integrating circuit at the end of the last duty cycle of the Σ Δ ADC mode_refIs a reference voltage; the digital output circuit is used for outputting N-1 bit temperature data according to the differential target voltage value of the 1 st working period of the SARADC mode in the 1 st working period of the SARADC mode; and/or the presence of a gas in the gas,

a differential target voltage value Δ V generated by the integration circuit at the end of the ith duty cycle of the SARADC mode_i＝2ΔV_i-1±V_ref，ΔV_i-1The digital output circuit is used for generating a differential target voltage value at the end of the i-1 working period of the SARADC mode according to the integrating circuit in the i working period of the SARADC modeDifferential target voltage value delta V of ith working cycle of SARADC mode_iGenerating N-i bit temperature data; i is more than or equal to 2 and less than or equal to N-1.

In the above scheme, the step of providing the sampling signal to the integrating circuit by the B controllable sampling circuit in each working period, and adjusting the size of the integrating capacitor of the integrating circuit and the feedback mode includes:

the first switch sub-circuit and the second switch sub-circuit are used for being in an off state in a first period, a third period and a fourth period, so that the integrating circuit is in a first feedback mode; in a second period, the integration circuit is in a second feedback mode; the first sampling sub-circuit samples the temperature analog signal at each time interval to obtain a first voltage V_BEThe second sampling sub-circuit samples the temperature analog signal at each time interval to obtain a second voltage delta V_BE(ii) a The total sampling capacitance of the first sampling sub-circuit in the second period is smaller than the reference sampling capacitance of the first sampling sub-circuit, and the total sampling capacitance of the second sampling sub-circuit in the second period is smaller than the reference sampling capacitance of the second sampling sub-circuit;

the digital output circuit generates temperature data D forming binary digital temperature according to the differential target voltage value delta V in each working period, and the method comprises the following steps:

the comparator determines temperature data D according to the differential target voltage value delta V in the fourth period;

the counter generates temperature data constituting binary digital temperatures from the temperature data in the fourth period.

Compared with the prior art, the temperature sensor provided by the invention has a sigma delta ADC mode for generating the temperature data from the Mth bit to the Nth bit and a SARADC mode for generating the temperature data from the N-1 st bit to the 1 st bit, so that the conversion rate can be greatly increased and the average power consumption of the circuit can be reduced on the premise of unchanged temperature conversion precision and static current of the circuit.

Drawings

FIG. 1 is a circuit configuration diagram of a prior art temperature sensor;

FIG. 2 is a schematic block diagram of a temperature sensor according to an embodiment of the present invention;

FIG. 3 is a diagram of an embodiment of a temperature sensor outputting D in a SARADC mode₁～D₀A schematic of the bit temperature data;

FIG. 4 is a schematic block diagram of a controllable sampling circuit in a temperature sensor according to an embodiment of the present invention;

FIG. 5 is a circuit diagram of a temperature sensor according to an embodiment of the present invention;

FIG. 6 is a diagram of a temperature sensor at Φ according to an embodiment of the present invention₁A circuit structure diagram of phase time;

FIG. 7 shows a temperature sensor at Φ₂Circuit structure diagram of phase time.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

An embodiment of the present invention provides a temperature sensor, as shown in fig. 2, including: a controllable sampling circuit 100, an integrating circuit 200 and a digital output circuit 300; the controllable sampling circuit 100 is electrically connected with the input end of the integrating circuit 200, the controllable sampling circuit 100 is also electrically connected with the output end of the integrating circuit 200, and the output end of the integrating circuit 200 is electrically connected with the digital output circuit 300; the temperature sensor is provided with a sigma delta ADC mode for generating Mth-Nth bit temperature data and a SARADC mode for generating Nth-1 st bit temperature data; work period T ═ kT of temperature sensor in SARADC mode₀K is an integer greater than 0 and less than a predetermined value, T₀N-1 is more than or equal to 0 and less than M is the clock period of the integrating circuit 200, and M is the resolution of the temperature sensor;

as shown in fig. 2, when the temperature sensor is in the sar adc mode, the controllable sampling circuit 100 is configured to provide a sampling signal to the integrating circuit 200 in each working period, and adjust the sampling capacitance of the integrating circuit 200 and the feedback mode, and the integrating circuit 200 is configured to form a differential target voltage value Δ V according to the sampling signal in each working period; the digital output circuit 300 is used to generate temperature data D constituting binary digital temperatures from the differential target voltage values at every duty cycle.

As shown in fig. 2, assuming that the resolution M of the temperature sensor is 12, k is 4, and N is 2, the present invention divides the conversion process into two steps: first, in the Σ Δ ADC mode, the output of the digital output circuit 300 is increased by 10-bit temperature data D in the normal mode₁₁～D₂This step requires T₀*2¹⁰s; then, the temperature sensor enters a SARADC mode through an enabling signal, only 4 clock cycles are needed for generating one digital output bit at the time, and temperature data D are generated₁～D₀Total 8T₀s。

For a temperature sensor with M-bit resolution, if a conventional Σ Δ ADC circuit structure is adopted, the single temperature conversion time is T_conv.＝T₀*2^M(ii) a If the invention is adopted, the single temperature conversion time is shortened to T_prop.＝T₀*2^M-N+8T₀. When the value of N is larger, the embodiment of the invention can improve the single conversion time by nearly 2^NAnd the average power consumption of the circuit is greatly reduced.

As shown in fig. 2, the differential target voltage value Δ V of the integration circuit 200 in the 1 st duty cycle of the sar adc mode₁＝2ΔV_ΣΔADC±V_ref，ΔV_ΣΔADCIs the differential target voltage value, V, generated by the integrating circuit 200 at the end of the last duty cycle of the Σ Δ ADC mode_refIs a reference voltage; the digital output circuit 300 is configured to output N-1 bit temperature data according to the differential target voltage value of the 1 st duty cycle of the sar adc mode in the 1 st duty cycle of the sar adc mode; and/or the presence of a gas in the gas,

the differential target voltage value Δ V generated by the integration circuit 200 at the end of the ith duty cycle of the SARADC mode_i＝2ΔV_i-1±V_ref，ΔV_i-1The digital output circuit 300 is used for generating the differential target voltage value at the end of the i-1 th working period of the sar adc mode according to the differential target voltage value Δ V generated by the integrating circuit 200 at the end of the i-1 th working period of the sar adc mode in the i-th working period of the sar adc mode_iGenerating N-i bit temperature data; i is more than or equal to 2 and less than or equal to N-1.

In particular, the amount of the solvent to be used,as shown in fig. 2 and 3, the integration circuit 200 outputs D in the sar adc mode assuming that the temperature sensor has a resolution M of 12, k of 4, and N of 2₁～D₀Bit temperature data, in the sigma-delta ADC mode, to cause the digital output circuit 300 to output 10 higher bit temperature data D in the normal mode₁₁～D₂，D₂Temperature data output for the last bit of the upper 10-bit temperature data.

In the SARADC mode, D₁For temperature data corresponding to the 1 st duty cycle, Δ V₁₀For the differential target voltage value, | Δ V, generated at the end of the 10 th duty cycle of the Σ Δ ADC mode₁₀|＜V_ref. When the integrating circuit 200 determines Δ V₁₀>When 0, it is subjected to Δ V₁＝2ΔV₁₀-V_refOperation if Δ V₁₁＝2ΔV₁₀-V_ref>0 determines D₁Is 1, and 1 is added to the circuit integration value of the temperature data output for the last bit of the upper 10-bit temperature data if Δ V₁₂＝2ΔV₁₀-V_ref< 0 determination of D₁Is 0, and 1 is added to the circuit integration value of the temperature data output for the last bit of the upper 10-bit temperature data. When the integrating circuit 200 determines Δ V₁₀If < 0, it is subjected to Δ V₁＝2ΔV₁₀+V_refOperation if Δ V₁₃＝2ΔV₁₀+V_ref>0 determines D₁Is 1, and the circuit integration value of the temperature data output for the last bit of the upper 10-bit temperature data is kept constant if Δ V₁₄＝2ΔV₁₀+V_ref< 0 determination of D₁Is 0, and the circuit integration value of the temperature data output for the last bit of the upper 10-bit temperature data remains unchanged.

Similarly, as shown in FIG. 2, in the SARADC mode, D₀When the integrator circuit 200 determines Δ V for the temperature data corresponding to the 2 nd duty cycle₁>At time 0, according to the differential target voltage value Δ V generated by the integration circuit 200 at the end of the 1 st duty cycle of the SARADC mode₁The differential target voltage value Δ V generated by the integration circuit 200 at the end of the 2 nd duty cycle of the SARADC mode can be determined₂＝2ΔV₁±V_refAnd (6) operation.

As shown in FIG. 2, when the integrating circuit 200 determines Δ V₁₁＝2ΔV₁₀-V_ref> 0, at this time Δ V₂₁＝2ΔV₁₁-V_refIf Δ V₂₁＝2ΔV₁₁-V_ref>0, then D₀If Δ V is 1₂₂＝2ΔV₁₁-V_ref< 0 determination of D₁The value of (d) is 0.

When Δ V₁₂＝2ΔV₁₀-V_refAt < 0, at this time,. DELTA.V₂₃＝2ΔV₁₂+V_ref. If Δ V₂₃＝2ΔV₁₂+V_ref>0, then D₀Has a value of 1; if Δ V₂₄＝2ΔV₁₂+V_refIf < 0, then D₀The value of (d) is 0.

When Δ V₁₃＝2ΔV₁₀+V_ref>At 0, at this time,. DELTA.V₂₅＝2ΔV₁₃-V_ref. If Δ V₂₅＝2ΔV₁₃-V_ref>0, then D₀Has a value of 1; if Δ V₂₆＝2ΔV₁₃-V_refIf < 0, then D₀The value of (d) is 0.

When Δ V₁₄＝2ΔV₁₀+V_refAt < 0, at this time,. DELTA.V₂₇＝2ΔV₁₄+V_ref. If Δ V₂₇＝2ΔV₁₄+V_ref>0, then D₀Has a value of 1; if Δ V₂₈＝2ΔV₁₄+V_refIf < 0, then D₀The value of (d) is 0.

Each duty cycle of the temperature sensor in the sar adc mode includes a first period, a second period, a third period, and a fourth period.

When Δ V is shown in FIG. 2_t>At time 0, in the t +1 th working cycle of the sar adc mode, the differential voltage value output by the integrating circuit 200 in the first period is Δ V_t-V_BE(ii) a The differential voltage value output by the integration circuit 200 in the second period is 2(Δ V)_t-V_BE) (ii) a The difference output by the integrating circuit 200 in the third periodThe divided voltage value is 2 (delta V)_t-V_BE)-αΔV_BEThe differential voltage value output by the integrating circuit 200 in the fourth period is 2 Δ V_t-V_ref；

When Δ V_t< 0, as shown in fig. 2, the differential voltage value outputted by the integrating circuit 200 in the first period is Δ V_t+V_BE(ii) a The differential voltage value output by the integration circuit 200 in the second period is 2(Δ V)_t+V_BE) (ii) a The differential voltage value output by the integration circuit 200 in the third period is 2(Δ V)_t-V_BE)+αΔV_BEThe differential voltage value output by the integrating circuit 200 in the fourth period is 2 Δ V_t+V_ref。

Specifically, as shown in fig. 2, the temperature data D output at the last bit of the upper 10-bit temperature data_NIs a differential target voltage value DeltaV₀>At 0, the integration process of the integration circuit 200 at different periods of each duty cycle is as follows:

a first period: due to DeltaV₀>0, digital output bit D at the clock edge starting at the first period_NPlus 1, the circuit integral value of the integrating circuit 200 is-V_BEThe differential voltage of the integrating circuit 200 is V_O1＝V_OP-V_ON＝ΔV₀-V_BE。

A second period of time T₂The circuit realizes × 2 function and outputs voltage V_O2＝2V_O1＝2(ΔV₀-V_BE)。

A third period of time T₃And a fourth period T₄: if the second period of time T₂Differential voltage V of_O2<0, then at T₃、T₄Inner separate integral + V_BE、-αΔV_BE(ii) a If V_O2>0, then integrate respectively- α Δ V_BE、+V_BE(ii) a Therefore, the third period T₃Differential voltage V of_O3＝2(ΔV₀-V_BE)+V_BEOr V_O3＝2(ΔV₀-V_BE)-αΔV_BEIrrespective of the third period T₃In which case the fourth period T₄Difference of (2)The sub-target voltage value is always V_O4＝2(ΔV₀-V_BE)+V_BE-αΔV_BEI.e. 2 Δ V₀-V_BE-αΔV_BEDue to V_ref＝V_BE+αΔV_BESo that the differential target voltage value is 2 Δ V₀-V_ref(ii) a It should be appreciated that the fourth time period T is now₄Output voltage V of_O4Namely, the differential target voltage value, and the corresponding temperature data can be determined according to the positive and negative of the differential target voltage value.

As shown in fig. 4, the controllable sampling circuit 100 comprises a first sampling sub-circuit 101, a second sampling sub-circuit 102, a first switching circuit 103 and a second switching sub-circuit 104. The digital output circuit 300 comprises a comparator 310 and a counter 320, and the first switch circuit 103 and the second switch sub-circuit 104 are used for controlling the integrating circuit 200 to be in a first feedback mode and a second feedback mode. The analog signal generating circuit is used for generating two analog temperature signals V_BEAnd Δ V_BEAnd output to the first sampling sub-circuit 101 and the second sampling sub-circuit 102, respectively.

For example, the following steps are carried out: the analog signal generating circuit can adopt a temperature analog signal generating circuit based on a double BJT, and comprises two bipolar transistors and two bias currents I_bias1And I_bias ₂Respectively flows to Q1 of the bipolar tube and Q2 of the bipolar tube to generate two analog temperature signals V_BEAnd Δ V_BE，V_BETwo V for the voltage magnitude between emitter and base of bipolar tube_BEThe difference producing a further temperature signal Δ V_BE。

As shown in fig. 4, the first sampling sub-circuit 101 is electrically connected to a first input terminal of the integrating circuit 200, the second sampling sub-circuit 102 is electrically connected to a second input terminal of the integrating circuit 200, a first output terminal of the integrating circuit 200 is electrically connected to a second output terminal of the comparator 310, a second output terminal of the integrating circuit 200 is electrically connected to a first output terminal of the comparator 310, and an output terminal of the comparator 310 is electrically connected to the counter 320; the first sampling sub-circuit 101 is further electrically connected to a second output terminal of the integrating circuit 200 through a first switch circuit 103, and the second sampling sub-circuit 102 is further electrically connected to a second output terminal of the integrating circuit 200 through a second switch sub-circuit 104;

as shown in fig. 4, the second switch sub-circuit 103 is for the second switch sub-circuit to be in an off state at the first period, the third period and the fourth period, and to be in an on state at the second period; the first sampling sub-circuit 101 is used for sampling the temperature analog signal in each period to obtain a first voltage V_BEThe second sampling sub-circuit 102 is configured to sample the temperature analog signal at each time interval to obtain a second voltage Δ V_BE(ii) a The total sampling capacitance of the first sampling sub-circuit 101 in the second period is smaller than the reference sampling capacitance of the first sampling sub-circuit 101, and the total sampling capacitance of the second sampling sub-circuit 102 in the second period is smaller than the reference sampling capacitance of the second sampling sub-circuit 102;

as shown in fig. 4, the reference sampling capacitance of the first sampling sub-circuit 101 and the reference sampling capacitance of the second sampling sub-circuit 102 are α C_SThe total sampling capacitance of the first sampling sub-circuit 101 in the second period and the total sampling capacitance of the second sampling sub-circuit 102 in the second period are α C_S-0.5C_I(ii) a The integration capacitance of the integration circuit 200 in the second period is 1.5C_IThe reference integration capacitance of the integration circuit 200 is C_I。

As shown in fig. 5, the first sampling sub-circuit 101 and the second sampling sub-circuit 102 each include a sampling capacitor α C formed by a plurality of serially connected switches and capacitors connected in parallel_S. The first switch sub-circuit 103 and the second switch sub-circuit 104 each comprise a first control switch S1 and a second control switch S2.

When the temperature sensor is in the Σ Δ ADC mode, the first control switch S1 remains open, and the second control switch S2 remains closed. The temperature sensor is in a Σ Δ ADC mode for generating mth-bit temperature data to nth-bit temperature data.

When the temperature sensor is in the sar adc mode, the first control switch S1 is closed, and the second control switch S2 is open, the temperature sensor is in the sar adc mode for generating the N-1 st bit temperature data to the 1 st bit temperature data.

As shown in fig. 5, for the integration circuit 200, the integration circuit 200 contains two integration capacitors C_IAnd in parallel with a first switch Φ for acquiring the sampling period and the integration period, respectively₁And a second switch phi₂。

Assuming that the resolution M of the temperature sensor is 12, the first control switch S is guaranteed in the Σ Δ ADC mode₁Second control switch S₂When closed, the digital output circuit 300 outputs 10-bit high-temperature data D according to the normal mode₁₁～D₂Generating temperature data D in the SARADC mode₁～D₀。

As shown in FIGS. 5-7, when the temperature sensor enters the SARADC mode, the circuit continues to operate and generates temperature data D with 4 time periods per duty cycle₁～D₀. In the following,. DELTA.V₀>In case of 0, D is generated₁The process of (2) describes the operation of the integrating circuit 200 for 4 periods:

1) a first period of time T₁: first control switch S₁Second control switch S₂And (5) closing. Due to DeltaV₀>0 at T₁Digital output bit D at the beginning clock edge₂Adds 1 to the circuit integration value of (2), the circuit integration value output by the integration circuit 200 is-V_BEThe differential voltage at the output of the integrating circuit 200 becomes V_O1＝V_OP-V_ON＝ΔV₀-V_BE。

2) A second period of time T₂: first control switch S₁Closed, second control switch S₂Off, at this point, the original sampling capacitor α C_SIs split into (α C)_S-0.5C_I) And 0.5C_ITwo parts, i.e. total sampling capacitance α C_S-0.5C_IIntegral capacitance of 1.5C_I(ii) a At phi₁、Φ₂Phase, the input voltage of the integrator circuit 200 remains unchanged, at which time the circuit performs × 2, which converts T to₁Periodic differential voltage V_O1Becomes V_O2＝2V_O1＝2(ΔV₀-V_BE)。

The specific circuit is shown in FIGS. 6 and 7, and is shown in phi₁Phase time, V_O1To integrating capacitor C_ICharging, in the circuitTotal charge quantity Q₁＝V_O1C_I(ii) a At phi₂In phase, assume that the amplifier input voltage is V_INObtaining the total charge Q in the circuit₂＝[C_I(V_OP-V_IN)+0.5C_I(V_ON-V_IN)]-[0.5C_I

(V_OP-V_IN)+C_I×(V_ON-V_IN)]＝0.5C_I(VOP-VON)＝0.5V_O2C_I。

According to conservation of charge, this time has V_O2＝2V_O1。

3) A third period of time T₃A fourth time period T₄: first control switch S₁Second control switch S₂And (5) closing. The circuit switches to the sigma delta ADC mode if T₂Periodic output V_O2<0, then at T₃、T₄Inner separate integral + V_BE、-αΔV_BE(ii) a If V_O2>0, then integrate respectively- α Δ V_BE、+V_BE(ii) a Δ V is always obtained at the output of the integrating circuit 200₁＝V_O4＝2(ΔV₀-V_BE)+V_BE-αΔV_BE＝2ΔV₀-V_ref(ii) a Determining Δ V by comparator 310₁Positive or negative of (2), then D can be determined₁。

Similarly, the Δ V is judged and processed in the same manner for 4 periods₁Can determine D₀。

The embodiment of the invention also provides a temperature analog signal digitization method which is applied to the temperature sensor of the embodiment; the temperature sensor has a sigma delta ADC mode for generating an Mth bit temperature data to an Nth bit temperature data, and the duty cycle T ═ kT of the temperature sensor in the SARADC mode₀K is an integer greater than 0 and less than a predetermined value, T₀N-1 is more than or equal to 0 and less than M is the clock period of the integrating circuit 200, and M is the resolution of the temperature sensor;

in the sigma delta ADC mode, the temperature sensor generates Mth-bit temperature data to Nth-bit temperature data according to the temperature analog signal; in the SARADC mode, the temperature sensor generates the temperature data of the (N-1) th bit to the temperature data of the 1 st bit according to the generated temperature data;

when the temperature sensor is in the sar adc mode, the controllable sampling circuit 100 provides a sampling signal to the integrating circuit 200 in each duty cycle, and adjusts the sampling capacitance of the integrating circuit 200 and the feedback mode; the integrating circuit 200 forms a differential target voltage value Δ V according to the sampling signal in each working period; the digital output circuit 300 generates temperature data D constituting binary digital temperatures from the differential target voltage values at every duty cycle.

The integration circuit 200 generates a differential target voltage value Δ V during the 1 st duty cycle of the SARADC mode_ΣΔADC±V_ref，ΔV_ΣΔADCIs the differential target voltage value, V, generated by the integrating circuit 200 at the end of the last duty cycle of the Σ Δ ADC mode_refIs a reference voltage; the digital output circuit 300 is configured to output N-1 bit temperature data according to a differential target voltage value generated at the end of the 1 st duty cycle of the sar adc mode in the 1 st duty cycle of the sar adc mode; and/or the presence of a gas in the gas,

the differential target voltage value Δ V generated by the integration circuit 200 at the end of the ith duty cycle of the SARADC mode_i＝2ΔV_i-1±V_ref，ΔV_i-1The digital output circuit 300 is used for generating the differential target voltage value at the end of the i-1 th working period of the sar adc mode by the integrating circuit 200, according to the differential target voltage value Δ V of the integrating circuit 200 in the i-th working period of the sar adc mode_iGenerating N-i bit temperature data; i is more than or equal to 2 and less than or equal to N-1.

Each work cycle of the temperature sensor in the SARADC mode comprises a first time period, a second time period, a third time period and a fourth time period;

when Δ V_t>At time 0, in the t +1 th working cycle of the sar adc mode, the differential voltage value output by the integrating circuit 200 in the first period is Δ V_t-V_BE(ii) a The differential voltage value output by the integration circuit 200 in the second period is 2(Δ V)_t-V_BE) (ii) a The integrated powerThe differential voltage value output by the circuit 200 in the third period is 2(Δ V)_t-V_BE)-αΔV_BEThe differential voltage value output by the integrating circuit 200 in the fourth period is 2 Δ V_t-V_ref；

When Δ V_tWhen the voltage is less than 0, the differential voltage value output by the integrating circuit 200 in the first period is Δ V_t+V_BE(ii) a The differential voltage value output by the integration circuit 200 in the second period is 2(Δ V)_t+V_BE) (ii) a The differential voltage value output by the integration circuit 200 in the third period is 2(Δ V)_t-V_BE)+αΔV_BEThe differential voltage value output by the integrating circuit 200 in the fourth period is 2 Δ V_t+V_ref。

The controllable sampling circuit 100 provides a sampling signal to the integrating circuit 200 in each working period, and adjusts the size and feedback mode of the integrating capacitor of the integrating circuit 200, including:

second switch sub-circuit 103 the second switch sub-circuit is for being in an off state during the first, third and fourth periods, such that the integrating circuit 200 is in a first feedback mode; in a second period, in a conducting state, so that the integrating circuit 200 is in a second feedback mode; the first sampling sub-circuit 101 samples the temperature analog signal at each period to obtain a first voltage V_BEThe second sampling sub-circuit 102 samples the temperature analog signal at each period to obtain a second voltage Δ V_BE(ii) a The total sampling capacitance of the first sampling sub-circuit 101 in the second period is smaller than the reference sampling capacitance of the first sampling sub-circuit 101, and the total sampling capacitance of the second sampling sub-circuit 102 in the second period is smaller than the reference sampling capacitance of the second sampling sub-circuit 102;

the integration circuit 200 forming the differential target voltage value Δ V from the sampling signal at each duty cycle includes:

the integration circuit 200 couples the first voltage V to each period_BEAnd a second voltage Δ V_BEPerforming integration; the sampling capacitance of the integrating circuit 200 in the second period is smaller than the reference sampling capacitance of the integrating circuit 200;

integration junction of integration circuit 200 during second periodIf the fruit is greater than 0, V is paired in the third period_BEIntegrate and take- α Δ V in the fourth period_BEWhen the integration result of the two periods is less than 0, the integration result is equal to- α Δ V in the third period_BEIntegrating, and comparing V in the fourth period_BEIntegrating to obtain a differential target voltage value delta V;

the digital output circuit 300 generates the temperature data D constituting the binary digital temperature from the differential target voltage value at each duty cycle includes:

the comparator 310 determines the temperature data D according to the differential target voltage value Δ V at the fourth period;

the counter 320 generates temperature data constituting binary digital temperatures from the temperature data in the fourth period.

The reference sampling capacitance of the first sampling sub-circuit 101 and the reference sampling capacitance of the second sampling sub-circuit 102 are α C_S；

The total capacitance of the first sampling sub-circuit 101 during the second period and the total capacitance of the second sampling sub-circuit 102 during the second period are α C_S-0.5C_I；

The integration capacitance of the integration circuit 200 in the second period is 1.5C_IThe reference integration capacitance of the integration circuit 200 is C_I。

The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims

1. A temperature sensor, comprising: the circuit comprises a controllable sampling circuit, an integrating circuit and a digital output circuit; the controllable sampling circuit is electrically connected with the input end of the integrating circuit, the controllable sampling circuit is also electrically connected with the output end of the integrating circuit, and the output end of the integrating circuit is electrically connected with the digital output circuit; the temperature sensor has a sigma delta ADC mode for generating an Mth bit temperature data to an Nth bit temperature data, and a SARADC mode for generating an N-1 th bit temperature data to a 1 st bit temperature data; the duty cycle T ═ kT of the temperature sensor in the SARADC mode₀K is an integer greater than 0 and less than a predetermined value, T₀Is an integrating circuitN-1 is more than or equal to 0 and less than M, and M is the resolution of the temperature sensor;

2. The temperature sensor of claim 1, wherein the integration circuit generates a differential target voltage value Δ V during the 1 st duty cycle of the SARADC mode₁＝2ΔV_ΣΔADC±V_ref，ΔV_ΣΔADCFor a differential target voltage value, V, generated by the integrating circuit at the end of the last duty cycle of the sigma delta ADC mode_refIs a reference voltage; the digital output circuit is used for outputting N-1 bit temperature data according to the differential target voltage value of the 1 st working period of the SARADC mode in the 1 st working period of the SARADC mode; and/or the presence of a gas in the gas,

3. The temperature sensor of claim 1, wherein each duty cycle of the temperature sensor in the sar adc mode comprises a first period, a second period, a third period, and a fourth period;

4. The temperature sensor of claim 1, wherein the controllable sampling circuit comprises a first sampling sub-circuit, a second sampling sub-circuit, a first switching sub-circuit, and a second switching sub-circuit, and the digital output circuit comprises a comparator and a counter; the first switch sub-circuit and the second switch sub-circuit are used for controlling the integrating circuit to be in a first feedback mode and a second feedback mode; the analog signal generating circuit is used for generating two analog temperature signals V_BEAnd Δ V_BEAnd output to the first sampling sub-circuit and the second sampling sub-circuit, respectively;

the first sampling sub-circuit is electrically connected with a first input end of the integrating circuit, the second sampling sub-circuit is electrically connected with a second input end of the integrating circuit, a first output end of the integrating circuit is electrically connected with a second output end of the comparator, a second output end of the integrating circuit is electrically connected with a first output end of the comparator, and an output end of the comparator is electrically connected with the counter; the first sampling sub-circuit is further electrically connected to the second output terminal of the integrating circuit through the first switching sub-circuit, and the second sampling sub-circuit is further electrically connected to the second output terminal of the integrating circuit through the second switching sub-circuit 104;

5. The temperature sensor of claim 3, wherein the reference sampling capacitance of the first sampling sub-circuit and the reference sampling capacitance of the second sampling sub-circuit are α C_S；

6. A temperature analog signal digitization method, which is applied to the temperature sensor of any one of claims 1 to 5; what is needed isThe temperature sensor has a sigma delta ADC mode for generating an Mth bit temperature data to an Nth bit temperature data, the temperature sensor having a duty cycle T ═ kT in the SARADC mode₀K is an integer greater than 0 and less than a predetermined value, T₀N-1 is more than or equal to 0 and less than M is the clock period of the integrating circuit, and M is the resolution of the temperature sensor;

7. The method of claim 6, wherein the integration circuit generates the differential target voltage Δ V during the 1 st duty cycle of the SARADC mode₁＝2ΔV_ΣΔADC±V_ref，ΔV_ΣΔADCFor a differential target voltage value, V, generated by the integrating circuit at the end of the last duty cycle of the Σ Δ ADC mode_refIs a reference voltage; the digital output circuit is used for outputting N-1 bit temperature data according to the differential target voltage value of the 1 st working period of the SARADC mode in the 1 st working period of the SARADC mode; and/or the presence of a gas in the gas,

a differential target voltage value Δ V generated by the integration circuit at the end of the ith duty cycle of the SARADC mode_i＝2ΔV_i-1±V_ref，ΔV_i-1For the i-1 th duty cycle node of the integrating circuit in the SARADC modeA differential target voltage value generated during beam forming, the digital output circuit being used for generating a differential target voltage value Δ V according to the i-th working period of the integrating circuit in the SARADC mode during the i-th working period of the SARADC mode_iGenerating N-i bit temperature data; i is more than or equal to 2 and less than or equal to N-1.

8. The method of claim 6, wherein each duty cycle of the temperature sensor in the SARADC mode comprises a first period, a second period, a third period, and a fourth period;

9. The method of claim 6, wherein the B controllable sampling circuit provides a sampling signal to the integrating circuit in each working period, and the adjusting of the size and feedback mode of the integrating capacitor of the integrating circuit comprises:

the first and second switch sub-circuits are used for switching off in the first, third and fourth periodsA state such that the integrating circuit is in a first feedback mode; in a second period, the integration circuit is in a second feedback mode; the first sampling sub-circuit samples the temperature analog signal at each time interval to obtain a first voltage V_BEThe second sampling sub-circuit samples the temperature analog signal at each time interval to obtain a second voltage delta V_BE(ii) a The total sampling capacitance of the first sampling sub-circuit in the second period is smaller than the reference sampling capacitance of the first sampling sub-circuit, and the total sampling capacitance of the second sampling sub-circuit in the second period is smaller than the reference sampling capacitance of the second sampling sub-circuit;

10. The method of claim 6, wherein the reference sampling capacitance of the first sampling sub-circuit and the reference sampling capacitance of the second sampling sub-circuit are α C_S；