CN1113364C - 动态随机存取存储器 - Google Patents
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- CN1113364C CN1113364C CN96120524A CN96120524A CN1113364C CN 1113364 C CN1113364 C CN 1113364C CN 96120524 A CN96120524 A CN 96120524A CN 96120524 A CN96120524 A CN 96120524A CN 1113364 C CN1113364 C CN 1113364C
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
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Abstract
一种动态随机存取存储器包括:存贮数据于其中的单元阵列;列地址选通脉冲禁止缓冲器,它响应一个外部列地址选通脉冲禁止信号,至少产生一个内部列地址选通脉冲信号,以选择来自单元阵列的数据;及内部列地址选通启动信号产生电路,它至少产生一个内部列地址选通脉冲启动信号,以控制来自列地址选通脉冲禁止缓冲器的内部列地址选通脉冲信号数。根据本发明,可用一个外部列地址选通脉冲禁止管脚产生多个内部列地址选通脉冲信号以减小封装尺寸。
Description
本发明一般涉及半导体存储器,特别涉及动态随机存取存储器(此后称之为DRAM),其中用一个外部列地址选通脉冲禁止管脚(external column addressstrobe bar pin)产生多个内部列地址选通脉冲信号,以减小封装的尺寸。
参见图1,其中按块示出了常规DRAM的结构。如该图所示,DRAM包括响应多个外部列地址选通脉冲禁止信号/UCAS和/LCAS产生多个内部(例如两个)列地址选通脉冲信号ucas和lcas的列地址选通脉冲信号禁止缓冲器(此后称之为/CAS缓冲器)。来自/CAS缓冲器13的内部列地址选通脉冲信号lcas和ucas与来自单元阵列块11和12的数据结合,以分别选择L-数据和U-数据。
在上述常规DRAM中,外部列地址选通脉冲禁止管脚的数量与内部列地址选通脉冲信号的数量一样多,下面将参照图2A和图2B对此作详细说明。
图2A和图2B是图1中/CAS缓冲器13的逻辑电路图。如该图所示,用来接收多个外部列地址选通脉冲禁止信号的外部列地址选通脉冲禁止管脚的数量与内部列地址选通脉冲信号的数量一样多。
随着内部列地址选通脉冲信号数的增加,外部列地址选通脉冲禁止管脚数也增加,结果增加了封装的尺寸。所以/CAS缓冲器输入端管脚数的这种增加对***制造者所期望的小型化产生了不利影响。另外,当同时启动多个外部列地址选通脉冲禁止信号时,会在它们之间产生时间扭斜。这种时间扭斜会导致DRAM的误操作。
因此,为了解决上述问题作了本发明,本发明的目的是提供一种DRAM,其中用一个外部列地址选通脉冲禁止管脚产生多个内部列地址选通脉冲信号,以便能减小封装尺寸,避免时间扭斜,并可以选择地启动多个内部列地址选通脉冲信号。
根据本发明,提供一种动态随机存取存储器可实现上述和其它目的,所说动态随机存取存储器包括:存贮数据于其中的单元阵列;列地址选通脉冲禁止缓冲器,它响应一个外部列地址选通脉冲禁止信号,至少产生一个内部列地址选通脉冲信号,以选择来自单元阵列的数据;及控制装置,它至少产生一个内部列地址选通脉冲启动信号,以控制来自列地址选通脉冲禁止缓冲器的内部列地址选通脉冲信号数。
参照附图所作的以下详细说明会使本发明的上述和其它目的、特征和优点更加明显。
图1是表示常规DRAM结构的方块图;
图2A和2B是图1中/CAS缓冲器的逻辑电路图;
图3是表示根据本发明的一个实施例的DRAM结构的方块图;
图4A和4B是图3中/CAS缓冲器的逻辑电路图;
图5是图3中内部列地址选通脉冲启动信号产生电路的电路图;及
图6是表示图5中内部列地址选通脉冲启动信号产生电路的工作的时序图。
参见图3,其中按块示出了根据本发明的一个实施例的DRAM的结构。如该图所示,DRAM包括:存贮数据于其中的单元阵列块31和32;/CAS缓冲器33,它响应一个外部列地址选通脉冲禁止信号/CAS,至少产生一个内部列地址选通脉冲信号,以选择来自单元阵列31和32的数据;及内部列地址选通脉冲启动信号(此后称之为内部CAS启动信号)产生电路36,它至少产生一个内部CAS启动信号ENi,以控制来自/CAS缓冲器33的内部列地址选通脉冲信号数。如图3所示,/CAS缓冲器33适于通过一个输入管脚接收外部列地址选通脉冲禁止信号/CAS。/CAS缓冲器33响应一个外部列地址选通脉冲禁止信号/CAS,产生多个内部列地址选通脉冲信号,这正如以下参照图4A和4B的更详细地说明的一样。
图4A和4B是图3中/CAS缓冲器33的逻辑电路图。在图4A中,构成/CAS缓冲器33,使之响应外部列地址选通脉冲禁止信号/CAS和来自内部CAS启动信号产生电路36的内部CAS启动信号EN1和EN2,产生多个内部列地址选通脉冲信号ucas和lcas。图4B中,构成/CAS缓冲器33,使之响应外部列地址选通脉冲禁止信号/CAS和来自内部CAS启动信号产生电路36的内部CAS启动信号EN1-EN4,产生多个内部列地址选通脉冲信号cas1-cas4。换句话说,尽管常规/CAS缓冲器通过多个输入管脚接收多个外部列地址选通脉冲禁止信号,但本发明的/CAS缓冲器只通过一个输入管脚接收一个外部列地址选通脉冲禁止信号。
下面将参照图4A和4B详细说明根据本发明的优选实施例的有上述结构的/CAS缓冲器33的工作。
在由图4A的结构将要产生两个内部列地址选通脉冲信号ucas和lcas时,逻辑低的外部列地址选通脉冲禁止信号/CAS和逻辑低的/CAS缓冲器启动信号enb加到NOR门41,来自内部CAS启动信号产生电路36的逻辑高的内部CAS启动信号EN1和EN2分别加到第一和第二NAND门42和43。
结果,NOR门41的输出变为逻辑高,第一NAND门42的输出变为逻辑低,内部列地址选通脉冲信号ucas或第一反相器44的输出变为逻辑高。
另外,第二NAND门43的输出变为逻辑低,内部列地址选通脉冲信号lcas或第二反相器45的输出变为逻辑高。
换句话说,/CAS缓冲器33响应/CAS缓冲器启动信号enb,接收外部列地址选通脉冲禁止信号/CAS,它被激活,并且被激活的/CAS缓冲器33响应内部CAS启动信号EN1和EN2,产生内部列地址选通脉冲信号ucas和lcas。
来自/CAS缓冲器33的内部列地址选通脉冲信号ucas和lcas与来自单元阵列块31和32的数据结合,以分别选择L-数据和U-数据。所选的L-数据和U-数据分别通过第一和第二输入/输出(此后称之为I/O)缓冲器341和342输入/输出。
在响应外部列地址选通脉冲禁止信号/CAS和来自如图4所示的内部CAS启动信号产生电路36的内部CAS启动信号EN1-EN4产生多个内部列地址选通脉冲信号cas1-cas4时,所产生的这些信号与来自单元阵列块的数据结合,以分别选择U1-数据、U2-数据、L1-数据和L2-数据。所选的U1-数据、U2-数据、L1-数据和L2-数据分别通过第一至第四I/O缓冲器输入/输出。
如上所述,本发明的/CAS缓冲器接收一个外部列地址选通脉冲禁止信号/CAS,所接收的信号与来自内部CAS启动信号产生电路36的多个内部CAS启动信号结合,产生多个内部列地址选通脉冲信号。
图5是图3中内部CAS启动信号产生电路36的电路图。如该图所示,内部CAS启动信号产生电路36适于响应外部列地址选通脉冲禁止信号/CAS、行地址选通脉冲禁止信号/RAS、写启动信号/WE和输入/输出信号I/Oi,至少产生一个内部CAS启动信号ENi。为该目的,内部CAS启动信号产生电路36包括操作控制器52,它根据当外部列地址选通脉冲禁止信号/CAS为逻辑高且写启动信号/WE为逻辑低时行地址选通脉冲禁止信号/RAS的逻辑态控制电路的工作;及响应为逻辑高的写启动信号/WE而被驱动的逻辑门53和54。当逻辑门53和54被驱动时,它们响应输入/输出信号I/Oi至少产生一个内部CAS启动信号ENi,并根据输入/输出信号I/Oi的逻辑态控制至少一个内部CAS启动信号ENi的逻辑态。
下面将参照图5详细说明根据本发明的优选实施例的具有上述结构的内部CAS启动信号产生电路36的工作情况。
如果当外部列地址选通脉冲禁止信号/CAS为逻辑高和写启动信号/WE为逻辑低时,行地址选通脉冲禁止信号/RAS为逻辑低,则第一节点N1处或锁定输出的信号变为逻辑高。把第一节点N1处的信号加到NMOS晶体管MN1的栅极。结果,NMOS晶体管MN1导通,因此,可使整个电路准备工作。
此时,如果输入/输出信号I/Oi为逻辑高,则在第二节点N2处的信号变为逻辑低,因此,使第三节点N3处的信号由逻辑高变为逻辑低。结果,因为内部CAS启动信号ENi变为逻辑低,所以它不能启动相应的内部列地址选通脉冲信号cas。在这种情况下,对于I/O缓冲器来说对应于被禁止的内部列地址选通脉冲信号cas数据被屏蔽。
图6是表示图5中内部CAS启动信号产生电路36的工作的时序图。当在行地址选通脉冲禁止信号/RAS为逻辑低的条件下,输入/输出信号I/Oi为逻辑高时,外部列地址选通脉冲禁止信号/CAS为逻辑高,写启动信号/WE为逻辑低。没有激活内部CAS启动信号ENi,禁止相应的内部列地址选通脉冲信号cas。如果不是这种情况,则内部CAS启动信号ENi被激活,启动相应的内部列地址选通脉冲信号。
由上述说明可看出,根据本发明,可用一个外部列地址选通脉冲禁止管脚产生多个内部列地址选通脉冲信号。因此,可减小封装尺寸以满足***制造者所希望的小型化。另外,使用一个外部列地址选通脉冲禁止管脚可有效地避免多个外部列地址选通脉冲禁止信号间的时间扭斜。
尽管以上为了说明的目的公开了本发明的优选实施例,但本领域的技术人员应该明白,在不脱离所附权利要求书所公开的本发明的范围和精神实质的情况下,可以对本发明作各种改型、附加和替换。
Claims (5)
1.一种动态随机存取存储器,该动态随机存取存储器具有用于产生多个内部列地址选通禁止信号的发生器,该发生器包括:
控制装置,用于产生至少一个用于控制所述多个内部列地址选通禁止信号生成的内部列地址选通使能信号;以及
列地址选通禁止缓冲器,用于响应于所述内部列地址选通使能信号,利用一个外部列地址选通禁止信号,产生所述多个内部列地址选通信号。
2.根据权利要求1所述的动态随机存取存储器,其中,所述列地址选通禁止缓冲器适用于通过一个外部封装管脚接收所述一个外部列地址选通禁止信号。
3.根据权利要求1所述的动态随机存取存储器,其中,所述控制装置适用于响应于所述的一个外部列地址选通禁止信号、行地址选通禁止信号、写使能信号和输入/输出信号,产生所述多个内部列地址选通使能信号。
4.根据权利要求3所述的动态随机存取存储器,其中,所述控制装置适用于根据所述输入/输出信号的逻辑状态,控制所述多个内部列地址选通使能信号的逻辑状态。
5.根据权利要求1所述的动态随机存取存储器,其中,有选择地使能所述多个内部列地址选通使能信号以控制对应的数据路径。
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Application Number | Priority Date | Filing Date | Title |
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KR95-39981 | 1995-11-06 | ||
KR9539981 | 1995-11-06 | ||
KR1019950039981A KR0170905B1 (ko) | 1995-11-06 | 1995-11-06 | 디램 |
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CN1154560A CN1154560A (zh) | 1997-07-16 |
CN1113364C true CN1113364C (zh) | 2003-07-02 |
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CN96120524A Expired - Fee Related CN1113364C (zh) | 1995-11-06 | 1996-11-06 | 动态随机存取存储器 |
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Country | Link |
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US (1) | US5801998A (zh) |
JP (1) | JPH09147548A (zh) |
KR (1) | KR0170905B1 (zh) |
CN (1) | CN1113364C (zh) |
DE (1) | DE19645745B4 (zh) |
GB (1) | GB2307075B (zh) |
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1995
- 1995-11-06 KR KR1019950039981A patent/KR0170905B1/ko not_active IP Right Cessation
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1996
- 1996-11-05 US US08/740,951 patent/US5801998A/en not_active Expired - Lifetime
- 1996-11-06 CN CN96120524A patent/CN1113364C/zh not_active Expired - Fee Related
- 1996-11-06 DE DE19645745A patent/DE19645745B4/de not_active Expired - Fee Related
- 1996-11-06 JP JP8308614A patent/JPH09147548A/ja active Pending
- 1996-11-06 GB GB9623138A patent/GB2307075B/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH09147548A (ja) | 1997-06-06 |
KR0170905B1 (ko) | 1999-03-30 |
DE19645745B4 (de) | 2011-09-29 |
GB2307075A (en) | 1997-05-14 |
DE19645745A1 (de) | 1997-05-07 |
KR970029804A (ko) | 1997-06-26 |
CN1154560A (zh) | 1997-07-16 |
GB2307075B (en) | 2000-05-17 |
US5801998A (en) | 1998-09-01 |
GB9623138D0 (en) | 1997-01-08 |
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