CN111326098A - Source electrode driving control method and device and display terminal - Google Patents
Source electrode driving control method and device and display terminal Download PDFInfo
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- CN111326098A CN111326098A CN202010269447.4A CN202010269447A CN111326098A CN 111326098 A CN111326098 A CN 111326098A CN 202010269447 A CN202010269447 A CN 202010269447A CN 111326098 A CN111326098 A CN 111326098A
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The embodiment of the application provides a source electrode driving control method, a source electrode driving control device and a display terminal, wherein the source electrode driving control method comprises the following steps: after the system is powered on, the time schedule controller sends a clock data recovery training mode signal to the source driver; the source driver recovers the clock data based on the clock data recovery training mode signal, generates a lock detection signal and returns the lock detection signal to the time schedule controller; and if the lock detection signal is in an effective state and the number of the clock data recovery training mode signals received by the source driver is greater than a preset value, the source driver sets the lock detection signal to be in an ineffective state so as to reset the time schedule controller and stop sending the clock data recovery training mode signals to the source driver. According to the embodiment of the application, when the time schedule controller is halted and continuously sends the clock data recovery training mode signal to the source driver, the source driver detects and controls the time schedule controller to reset in time so as to recover to normal.
Description
Technical Field
The embodiment of the application relates to the technical field of display, in particular to a source driving control method, a source driving control device and a display terminal.
Background
At present, as the size of the display panel is getting larger and higher, the resolution is getting higher and higher, so that the Data transmitted between the Timing Controller (TCON) and the Source driver (Source driver) of the display panel is getting more and more, therefore, the V-By-one (vbo) interface is generally used for communication, the timing controller will send a Clock Data Recovery training mode signal (CDR pattern) to the Source driver, so that the Source driver performs Clock Data Recovery (CDR) and generates a lock detection signal based on the Clock Data Recovery training mode signal, if the lock detection signal is in an effective state, it indicates that the Clock Data Recovery of the Source driver is successful, a Phase Locked Loop (PLL) between the timing controller and the Source driver is Locked, and if the lock detection signal is in an invalid state, it indicates that the Clock Data Recovery of the Source driver is failed, the phase locked loop between the timing controller and the source driver is not locked. The timing controller performs subsequent steps according to whether the lock detection signal is valid.
However, there is a case where, if the timing controller has a crash problem and always sends the clock data recovery training mode signal to the source driver and the phase-locked loop between the timing controller and the source driver is locked, the source driver always performs clock data recovery and generates a lock detection signal in an active state based on the clock data recovery training mode signal, so that the timing controller always sends the clock data recovery training mode signal to the source driver, and the timing controller cannot be reset all the time and cannot perform subsequent steps.
Disclosure of Invention
In order to solve the above problem, in one aspect, embodiments of the present application provide a source driving control method applied to a display terminal including a timing controller and a source driver that communicate with each other. The source driving control method comprises the following steps:
after the system is powered on, the time schedule controller sends a clock data recovery training mode signal to the source driver.
And the source driver recovers clock data based on the clock data recovery training mode signal to generate a lock detection signal and returns the lock detection signal to the time schedule controller.
And if the lock detection signal is in an effective state and the number of the clock data recovery training mode signals received by the source driver is greater than a preset value, the source driver sets the lock detection signal to be in an ineffective state so as to reset the timing controller and stop sending the clock data recovery training mode signals to the source driver.
In some embodiments, the step of "the source driver performs clock data recovery to generate a lock detection signal based on the clock data recovery training pattern signal" includes:
and the source driver utilizes a phase-locked loop to take the clock data recovery training mode as an input signal of the phase-locked loop so as to recover clock data which accords with the clock data recovery training mode and generate the lock detection signal.
If the clock data is successfully recovered, the lock detection signal is in an effective state, and if the clock data is unsuccessfully recovered, the lock detection signal is in an ineffective state.
In some embodiments, the active state of the lock detection signal is a high signal and the inactive state of the lock detection signal is a low signal.
In some embodiments, the active state of the lock detection signal is a low signal and the inactive state of the lock detection signal is a high signal.
On the other hand, the embodiment of the present application further provides a source driving control device, where the source driving control device is applied to a display terminal, where the display terminal includes a timing controller and a source driver that are communicated with each other, and the device is configured to control the timing controller to send a clock data recovery training mode signal to the source driver after a system is powered on; and controlling the source driver to perform clock data recovery based on the clock data recovery training mode signal, and generating a lock detection signal to return to the timing controller.
And if the lock detection signal is in an effective state and the number of the clock data recovery training mode signals received by the source driver is greater than a preset value, controlling the source driver to set the lock detection signal to be in an ineffective state so as to reset the time schedule controller and stop sending the clock data recovery training mode signals to the source driver.
In some embodiments, the apparatus further comprises a phase-locked loop; the phase-locked loop is used for the source driver to take the clock data recovery training mode signal as an input signal of the phase-locked loop so as to recover clock data which accords with the clock data recovery training mode and generate the lock detection signal; if the clock data is successfully recovered, the lock detection signal is in an effective state, and if the clock data is unsuccessfully recovered, the lock detection signal is in an ineffective state.
In some embodiments, the active state of the lock detection signal is a high signal and the inactive state of the lock detection signal is a low signal.
In some embodiments, the active state of the lock detection signal is a low signal and the inactive state of the lock detection signal is a high signal.
In another aspect, an embodiment of the present application further provides a display terminal, where the display terminal includes: the display device comprises a display panel, a time schedule controller, a source driver and the source driving control device. The source driving control device is used for controlling source driving of the display panel and comprises a processor and a memory used for storing executable instructions of the processor.
The executable instructions are arranged to: after a system is powered on, the time schedule controller sends a clock data recovery training mode signal to the source electrode driver; and the source driver recovers the clock data based on the clock data recovery training mode signal, generates a lock detection signal and returns the lock detection signal to the time schedule controller.
And if the lock detection signal is in an effective state and the number of the clock data recovery training mode signals received by the source driver is greater than a preset value, the source driver sets the lock detection signal to be in an ineffective state so as to reset the timing controller and stop sending the clock data recovery training mode signals to the source driver.
In some embodiments, the timing controller and the source driver communicate with each other using an image transfer digital interface VBO or an embedded display interface EDP.
According to the source electrode driving control method, the source electrode driving control device and the display terminal, after a system is powered on, the time schedule controller sends clock data recovery training mode signals to the source electrode driver; the source driver recovers the clock data based on the clock data recovery training mode signal, generates a lock detection signal and returns the lock detection signal to the time schedule controller; and if the lock detection signal is in an effective state and the number of the clock data recovery training mode signals received by the source driver is greater than a preset value, the source driver sets the lock detection signal to be in an ineffective state so as to reset the time schedule controller and stop sending the clock data recovery training mode signals to the source driver. According to the embodiment of the application, when the time schedule controller is halted and continuously sends the clock data recovery training mode signal to the source driver, the source driver detects and controls the time schedule controller to reset in time so as to recover to normal.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a general flowchart of a source driving control method according to an embodiment of the present application;
fig. 2 is a detailed flowchart of a source driving control method according to an embodiment of the present disclosure;
fig. 3 is a control schematic diagram of a source driving control device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Fig. 1 is a general flowchart of a Source driving control method according to an embodiment of the present disclosure, and referring to fig. 1, the embodiment of the present disclosure provides a Source driving control method applied to a display terminal, where the display terminal includes a timing controller TCON and a Source driver in communication with each other, and the Source driving control method includes the following steps:
s1, after the system is powered on, the TCON sends a clock data recovery training mode signal CDRPattern to the Source Driver.
S2, the Source Driver recovers the clock data based on the CDR pattern to generate a lock detection signal Sdlock, and returns the Sdlock to the TCON.
S3, if Sdlock is in an effective state and the number of CDR patterns received by the Source Driver is greater than a preset value, the Source Driver sets the Sdlock in an ineffective state so as to reset the TCON and stop sending the CDR patterns to the Source Driver.
Specifically, since the transmission rate between the TCON and the Source Driver is generally set to a predetermined value, during the normal driving process, the length, i.e., the number, of the CDR patterns transmitted by the TCON is limited, and if the number of the CDR patterns received by the Source Driver exceeds a set value, it indicates that the TCON crashes, at this time, the Source Driver sets Sdlock to an invalid state and returns Sdlock to the TCON, so that the TCON resets and simultaneously outputs a black picture, at this time, the TCON stops crashing and exits a dead cycle of continuously transmitting the CDR patterns to the Source Driver.
It should be noted that, in addition to taking the number of the CDR pattern signals not exceeding the set value as the detection condition, the duration of receiving the CDR pattern signals may also be taken as the detection condition, that is, after the preset time, if the Sourcedriver can still receive the CDR patterns sent by the TCON, it may also indicate that the TCON has a crash fault.
The Source electrode driving control method provided by the embodiment of the application can detect and control the TCON to reset to recover to normal in time through the Source Driver when the TCON has a crash problem and continuously sends the CDR pattern to the Source Driver.
Further, the step S2, where "Source Driver performs clock data recovery based on CDR pattern to generate Sdlock", includes:
the Source Driver uses a phase-locked loop PLL to take a clock data recovery training pattern CDR pattern as an input signal of the PLL so as to recover clock data conforming to the CDR pattern and generate Sdlock.
If the clock data recovery is successful, the Sdlock is in an effective state, and if the clock data recovery is failed, the Sdlock is in an ineffective state.
Specifically, the PLL is a feedback circuit for uniformly integrating clock signals, and functions to synchronize the phase of a clock on the circuit with that of an external clock, so that different signal terminals can share the same sampling clock. In the Source drive control method, a Source driver uses a CDR pattern sent by a TCON as an input signal of a PLL, the PLL is used for recovering clock data conforming to the CDR pattern, and if the clock data is successfully recovered, an effective Sdlock is generated; and if the clock data recovery fails, generating Sdlock in an invalid state.
It is understood that if the active state of Sdlock is a high signal, the inactive state of Sdlock is a low signal. Similarly, if the active state of Sdlock is a low signal, the inactive state of Sdlock is a high signal.
Fig. 2 is a detailed flowchart of a source driving control method according to an embodiment of the present application, where in fig. 2, an active state of Sdlock is a high level signal, and an inactive state is a low level signal.
Specifically, after the system is powered on, the TCON sends the CDR pattern to the Source Driver. The Source Driver uses the PLL to take the CDR pattern as an input signal of the PLL to recover clock data conforming to the CDR pattern and generate Sdlock, and returns Sdlock to TCON. And if the Sdlock is in an effective state and the number of the CDRPatterns received by the Source Driver is greater than a preset value, the Source Driver sets the Sdlock in an ineffective state so as to reset the TCON and stop sending the CDRPatterns to the Source Driver.
Fig. 3 is a control schematic diagram of a Source driving control device according to an embodiment of the present disclosure, and referring to fig. 3, an embodiment of the present disclosure further provides a Source driving control device, which is applied to a display terminal, where the display terminal includes a TCON and a Source Driver that communicate with each other, and the Source driving control device is configured to control the TCON to send a CDR pattern to the Source Driver after a system is powered on; and controlling the Source Driver to recover clock data based on the CDR pattern, and generating Sdlock to return to the TCON.
And if the Sdlock is in an effective state and the number of the CDR patterns received by the Source Driver is greater than a preset value, controlling the Source Driver to set the Sdlock in an ineffective state so as to reset the TCON and stop sending the CDR patterns to the Source Driver.
Specifically, if the number of the CDR patterns received by the Source driver exceeds a set value, it indicates that the TCON crashes, and at this time, the Source driver sets Sdlock to an invalid state and returns the Sdlock to the TCON, so that the TCON resets and outputs a black picture at the same time, and at this time, the TCON stops crashing and exits from a dead cycle of continuously sending CDR patterns to the Source driver.
Further, the apparatus further comprises a phase locked loop, PLL; the PLL is used for Source Driver to take the CDR pattern as an input signal of the PLL so as to recover clock data conforming to the CDR pattern and generate Sdlock; if the clock data recovery is successful, the Sdlock is in an effective state, and if the clock data recovery is failed, the Sdlock is in an ineffective state.
It is understood that if the active state of Sdlock is a high signal, the inactive state of Sdlock is a low signal. Similarly, if the active state of Sdlock is a low signal, the inactive state of Sdlock is a high signal.
Based on the above embodiment, the present application further provides a display terminal, which includes: the display device comprises a display panel, a TCON, a Source Driver and the Source driving control device, wherein the Source driving control device is used for controlling the Source driving of the display panel and comprises a processor and a memory for storing executable instructions of the processor.
Wherein the executable instructions are arranged to:
after the system is powered on, the TCON sends CDR pattern to the Source Driver.
And the Source Driver recovers the clock data based on the CDR pattern, generates Sdlock and returns the Sdlock to the TCON.
And if the Sdlock is in an effective state and the number of the CDR patterns received by the Source Driver is greater than a preset value, the Source Driver sets the Sdlock in an ineffective state so as to reset the TCON and stop sending the CDCDR patterns to the Source Driver.
It should be noted that the TCON and the Source Driver communicate with each other by using an image transmission digital interface VBO or an embedded display interface EDP.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The above description of the embodiments is only for assisting understanding of the technical solutions and the core ideas thereof; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. A source driving control method applied to a display terminal including a timing controller and a source driver communicating with each other, the source driving control method comprising:
after a system is powered on, the time schedule controller sends a clock data recovery training mode signal to the source electrode driver;
the source electrode driver recovers clock data based on the clock data recovery training mode signal, generates a lock detection signal and returns the lock detection signal to the time schedule controller;
and if the lock detection signal is in an effective state and the number of the clock data recovery training mode signals received by the source driver is greater than a preset value, the source driver sets the lock detection signal to be in an ineffective state so as to reset the timing controller and stop sending the clock data recovery training mode signals to the source driver.
2. The source driving control method according to claim 1, wherein the step of the source driver performing clock data recovery based on the clock data recovery training pattern signal to generate the lock detection signal comprises:
the source driver uses a phase-locked loop to take the clock data recovery training mode signal as an input signal of the phase-locked loop so as to recover clock data which accords with the clock data recovery training mode and generate the lock detection signal;
if the clock data is successfully recovered, the lock detection signal is in an effective state, and if the clock data is unsuccessfully recovered, the lock detection signal is in an ineffective state.
3. The source driving control method of claim 1, wherein the active state of the lock detection signal is a high signal, and the inactive state of the lock detection signal is a low signal.
4. The source driving control method of claim 1, wherein the active state of the lock detection signal is a low signal, and the inactive state of the lock detection signal is a high signal.
5. A source electrode driving control device is applied to a display terminal, the display terminal comprises a time schedule controller and a source electrode driver which are communicated with each other, and the source electrode driving control device is characterized in that the source electrode driving control device is used for controlling the time schedule controller to send a clock data recovery training mode signal to the source electrode driver after a system is powered on;
controlling the source driver to recover clock data based on the clock data recovery training mode signal, generating a lock detection signal and returning the lock detection signal to the time schedule controller;
and if the lock detection signal is in an effective state and the number of the clock data recovery training mode signals received by the source driver is greater than a preset value, controlling the source driver to set the lock detection signal to be in an ineffective state so as to reset the time schedule controller and stop sending the clock data recovery training mode signals to the source driver.
6. The source drive control apparatus of claim 5, wherein the apparatus further comprises a phase locked loop; the phase-locked loop is used for the source driver to take the clock data recovery training mode signal as an input signal of the phase-locked loop so as to recover clock data which accords with the clock data recovery training mode and generate the lock detection signal; if the clock data is successfully recovered, the lock detection signal is in an effective state, and if the clock data is unsuccessfully recovered, the lock detection signal is in an ineffective state.
7. The source driving control device of claim 5, wherein the active state of the lock detection signal is a high signal and the inactive state of the lock detection signal is a low signal.
8. The source driving control device of claim 5, wherein the active state of the lock detection signal is a low signal and the inactive state of the lock detection signal is a high signal.
9. A display terminal, comprising: a display panel, a timing controller, a source driver, and the source driving control device according to any one of claims 5 to 8, the source driving control device for controlling source driving of the display panel;
the source electrode driving control device comprises a processor and a memory for storing executable instructions of the processor; the executable instructions are arranged to:
after a system is powered on, the time schedule controller sends a clock data recovery training mode signal to the source electrode driver;
the source electrode driver recovers clock data based on the clock data recovery training mode signal, generates a lock detection signal and returns the lock detection signal to the time schedule controller;
and if the lock detection signal is in an effective state and the number of the clock data recovery training mode signals received by the source driver is greater than a preset value, the source driver sets the lock detection signal to be in an ineffective state so as to reset the timing controller and stop sending the clock data recovery training mode signals to the source driver.
10. The display terminal of claim 9, wherein the timing controller and the source driver communicate with each other using an image transfer digital interface VBO or an embedded display interface EDP.
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