CN111324414B - NVM storage media emulator - Google Patents
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- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
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Abstract
The present application relates to memory technology, and relates to an NVM storage medium emulator for emulating an NVM storage medium with software. The application provides an NVM storage medium simulation method, comprising the following steps: responsive to acquiring a first command compliant with an NVM chip interface protocol; if the first command is a legal write command, acquiring a corresponding first virtual block according to a physical address accessed by the first command; acquiring a first cache unit or a first data file unit which provides a storage space for a first virtual block; and writing the data corresponding to the first command into the first cache unit or the first data file unit.
Description
Technical Field
The present application relates to memory technology, and relates to an NVM storage medium emulator for emulating an NVM storage medium with software.
Background
Fig. 1 illustrates a block diagram of a storage device. The storage device 102 is coupled to a host for providing storage capability for the host. The host and storage device 102 may be coupled by a variety of means including, but not limited to, connecting the host to the storage device 102 via, for example, SATA (Serial Advanced Technology Attachment ), SCSI (Small Computer System Interface, small computer system interface), SAS (Serial Attached SCSI ), IDE (Integrated Drive Electronics, integrated drive electronics), USB (Universal Serial Bus ), PCIE (Peripheral Component Interconnect Express, PCIE, peripheral component interconnect Express), NVMe (NVM Express), ethernet, fibre channel, wireless communication network, and the like. The host may be an information processing device capable of communicating with the storage device in the manner described above, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, or the like. The memory device 102 includes an interface 103, a control unit 104, one or more NVM chips 105, and a DRAM (Dynamic Random Access Memory ) 110.
NAND flash memory, phase change memory, feRAM (Ferroelectric RAM, ferroelectric memory), MRAM (Magnetic Random Access Memory, magnetoresistive memory), RRAM (Resistive Random Access Memory, resistive memory), XPoint memory, etc. are common NVM.
The interface 103 may be adapted to exchange data with a host by way of, for example, SATA, IDE, USB, PCIE, NVMe, SAS, ethernet, fibre channel, etc.
The control unit 104 is used to control data transfer among the interface 103, NVM chip 105, and DRAM 110, and also for memory management, host logical address to flash physical address mapping, erase balancing, bad block management, etc. The control component 104 can be implemented in a variety of ways, such as software, hardware, firmware, or a combination thereof, for example, the control component 104 can be in the form of an FPGA (Field-programmable gate array, field programmable gate array), an ASIC (Application Specific Integrated Circuit, application-specific integrated circuit), or a combination thereof. The control component 104 may also include a processor or controller in which software is executed to manipulate the hardware of the control component 104 to process IO (Input/Output) commands. Control unit 104 may also be coupled to DRAM 110 and may access data of DRAM 110. FTL tables and/or cached data of IO commands may be stored in the DRAM.
The control section 104 includes a flash interface controller (or referred to as a media interface, a media interface controller, a flash channel controller) that is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in a manner conforming to an interface protocol of the NVM chip 105 to operate the NVM chip 105 and receive command execution results output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", and the like.
The memory Target (Target) is one or more Logical Units (LUNs) of shared CE (Chip Enable) signals within the NAND flash package. One or more dies (Die) may be included within the NAND flash package. Typically, the logic unit corresponds to a single die. The logic cell may include multiple planes (planes). Multiple planes within a logic unit may be accessed in parallel, while multiple logic units within a NAND flash memory chip may execute commands and report status independently of each other.
Data is typically stored and read on a page-by-page basis on NVM storage media. While data is erased in blocks. A block (also called a physical block) contains a plurality of pages. A block contains a plurality of pages. Pages on a storage medium (referred to as physical pages) have a fixed size, e.g., 17664 bytes. The physical pages may also have other sizes.
During development, the simulator is used to simulate the functions and behavior of portions of the storage device to support the development and debugging process when the hardware device is not available. The simulator also provides state observation and modification capabilities that are difficult for hardware devices to possess, thereby facilitating problem localization and identification.
A simulator for the control unit 103 is already present. It is also desirable to have a simulator for NVM chip 105.
Disclosure of Invention
A simulator for an NVM storage medium configured of a plurality of NVM chips used in a storage device is provided. The simulator is implemented in software and interacts with the control unit. The control component that interacts with the NVM storage medium emulator may be a control component emulator or a hardware control component.
According to a first aspect of the present application, there is provided a first NVM storage medium emulation method according to the first aspect of the present application, comprising: responsive to acquiring a first command compliant with an NVM chip interface protocol; if the first command is a legal write command, acquiring a corresponding first virtual block according to a physical address accessed by the first command; acquiring a first cache unit or a first data file unit which provides a storage space for a first virtual block; and writing the data corresponding to the first command into the first cache unit or the first data file unit.
According to the first NVM storage medium emulation method of the first aspect of the present application, if the storage space corresponding to the first virtual block recorded in the entry of the virtual block table is provided by the first cache unit, the data corresponding to the first command is written into the first cache unit.
According to the first or second NVM storage medium emulation method of the first aspect of the present application, if the memory space corresponding to the first virtual block recorded in the entry of the virtual block table is provided by the first data file unit, the data of the first data file unit is loaded into the newly allocated cache unit, and the data corresponding to the first command is written into the newly allocated cache unit.
According to one of the first to third NVM storage medium emulation methods of the first aspect of the present application, if the storage space corresponding to the first virtual block recorded in the entry of the virtual block table is not provided by the cache unit or the data file unit, a new cache unit is allocated from the cache, and the data corresponding to the first command is written into the newly allocated cache unit.
The third or fourth NVM storage medium emulation method according to the first aspect of the present application, further includes updating a virtual block table corresponding to the first virtual block, where the storage space for recording the first virtual block in the entry of the virtual block table is provided by the newly allocated cache unit.
According to one of the first to fifth NVM storage medium emulation methods of the first aspect of the present application, if the first command is a legal read command, acquiring a corresponding first virtual block according to a physical address accessed by the first command; acquiring a first cache unit or a first data file unit which provides a storage space for a first virtual block; and acquiring data from the first cache unit or the first data file unit.
According to one of the first to sixth NVM storage medium emulation methods of the first aspect of the present application, if the first command is a legal erase command, acquiring a corresponding first virtual block according to a physical address accessed by the first command; and erasing the physical block indicated to be erased by the first command, and setting an erasure flag in the first virtual block.
According to one of the first to seventh NVM storage medium simulation methods of the first aspect of the present application, a physical address of the first command is obtained, a chunk to which the physical address accessed by the first command belongs is obtained according to the physical address accessed by the first command, and a corresponding first virtual chunk is obtained according to the chunk number.
According to one of the first to eighth NVM storage medium emulation methods of the first aspect of the present application, in response to obtaining a first command conforming to the NVM chip interface protocol, checking whether the format of the first command meets the requirements of the NVM chip interface protocol, and checking whether the first command meets the constraint conditions of the NVM chip, if both the first command meets the constraint conditions, the first command is a legal command, otherwise, generating a processing result of command illegality.
A ninth NVM storage medium emulation method according to the first aspect of the present application, wherein the requirements of the NVM chip interface protocol include: if the first command is a read command, the first command should include a specified length and a specified number of instruction addresses; if the first command is an erase command, the physical block number should be indicated in the first command and the physical block number should indicate an existing physical block.
The ninth or tenth NVM storage medium simulation method according to the first aspect of the present application, wherein the constraints of the NVM chip include: if the first command is a read command or an erase command, the physical page accessed by the first command should be a physical page to which data has been written; if the first command is a write command, the physical page accessed by the first command should be a physical page in an erased state.
According to one of the tenth to eleventh NVM storage medium simulation methods of the first aspect of the present application, the format of the first command satisfies the requirements of the NVM chip interface protocol and satisfies the constraint conditions of the NVM chip, and if the first command is a management command, the logic unit is set to be in a specified state according to the management command, or the accessed state information is acquired, so as to generate a management command processing result.
The twelfth NVM storage media emulation method according to the first aspect of the present application, wherein the management command comprises a set feature command, a read feature command, or a reset command.
According to one of the eleventh to thirteenth NVM storage medium emulation methods of the first aspect of the present application, wherein the format of the first command satisfies the requirements of the NVM chip interface protocol and satisfies the constraint condition of the NVM chip, and if the physical address accessed by the first command belongs to a bad block, a processing result of the processing failure is generated.
According to the fourteenth NVM storage medium simulation method of the first aspect of the present application, if the first command is a program command to access a bad block, a processing result indicating a processing failure of the program command is generated; if the first command is a read command for accessing the bad block, generating data with uncorrectable errors as a processing result of the read command; if the first command is an erase command to access the bad block, a processing result indicating that the erase command processing failed is generated.
According to one of the tenth to fifteenth NVM storage medium emulation methods of the first aspect of the present application, wherein the format of the first command satisfies the requirements of the NVM chip interface protocol and satisfies the constraints of the NVM chip, data for which there is an uncorrectable error is generated with a specified probability for the read command as a processing result of the read command.
According to one of the tenth to fifteenth NVM storage medium emulation methods of the first aspect of the present application, wherein the format of the first command satisfies the requirements of the NVM chip interface protocol and satisfies the constraints of the NVM chip, and if the address accessed by the first command does not satisfy the specified relationship with the address of one or more write commands previously accessing the same physical block, the data corresponding to the first command is changed to data having uncorrectable errors.
According to one of the tenth to fifteenth NVM storage medium emulation methods of the first aspect of the present application, wherein the format of the first command satisfies the requirements of the NVM chip interface protocol and satisfies the constraint conditions of the NVM chip, and if the number of times the physical block accessed by the first command is erased is greater than the specified number of times, the data corresponding to the first command is changed to have uncorrectable data.
According to a second aspect of the present application, there is provided a first computer device according to the second aspect of the present application, comprising a memory, a processor and a computer program stored on the memory and executable on the processor, said processor implementing one of the NVM storage medium simulation methods described above when executing said program.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following description will briefly introduce the drawings that are required to be used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings may also be obtained according to these drawings for a person having ordinary skill in the art.
FIG. 1 is a block diagram of a solid state storage device of the related art;
FIG. 2 is a schematic diagram of a simulator system according to an embodiment of the present application;
FIG. 3 illustrates a block diagram of an NVM storage media emulator according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a large block and virtual address space, and a mapping from the virtual address space to a cache unit or data file unit, according to an embodiment of the present application;
FIG. 5 illustrates a virtual block table according to an embodiment of the present application;
FIG. 6 illustrates a flow chart of a programming command processing unit according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application, taken in conjunction with the accompanying drawings, clearly and completely describes the technical solutions of the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
FIG. 2 is a schematic diagram of a simulator system according to an embodiment of the present application.
NVM storage media emulator 210 runs as a separate process or processes in a computer or server and interacts in an interprocess communication with the control component's media interface 220. The control unit's media interface 220 generates commands that conform to the NVM chip interface protocol, provides the commands to the NVM storage media emulator 210, and receives the results output by the NVM storage media emulator 210. For simulation purposes, the physical layer features of the NVM chip interface protocol are omitted, but include, for example, "commands," "addresses," "data," and/or "states" representing logical meanings. Optionally, timing information of the NVM chip interface protocol is included in the commands, and NVM storage medium emulator 210 responds to commands of the timing information that properly conform to the NVM chip interface protocol.
The "channels" of the NVM chip coupled to the control components are modeled as queues, including "command commit queue 230" and "command completion queue 240". The media interface 220 sends commands to the "command commit queue 230" of the NVM storage media emulator 210, and the NVM storage media emulator 210 indicates command processing results to the media interface 220 via the "command completion queue 240". Optionally, commands passed between the media interface 220 and the NVM storage media emulator 210 are also numbered or identified so that commands in the "command completion queue 240" are numbered to identify which of the plurality of commands is processed to completion. NVM storage media emulator 210 retrieves and processes commands from command commit queue 230 and passes the results of the command processing to media interface 220 through command completion queue 240.
Alternatively, to simulate an NVM chip with large storage capacity, an NVM storage medium simulator is run on a 64-bit computing system to access memory space much greater than 4 GB. The memory space provides a cache. The management and use of the cache will be described in detail later. The NVM storage media emulator is also suitable for use in 32-bit computing systems, where the memory space available from the 32-bit computing system is limited, thereby affecting the performance (but not the functionality) of the NVM storage media emulator.
While the NVM storage media emulator and the emulator of the media interface may run on the same or different computer/server.
FIG. 3 illustrates a block diagram of an NVM storage media emulator according to an embodiment of the present application.
The command acquired from the command commit queue 330 is processed by one or more of a command format checking unit 311, a command rule checking unit 312, a management command processing unit 313, a bad block processing unit 314, and a UECC (uncorrectable error) unit 315. When some commands are processed by the command format checking unit 311, the command rule checking unit 312, the management command processing unit 313, the bad block processing unit 314, or the UECC (uncorrectable error) unit 315, processing results for the commands are generated and added to the command completion queue 340. The command whose processing result is added to the command completion queue 340, is no longer processed by the NVM storage media emulator 310.
The command, which is not processed by any of the command format checking unit 311, the command rule checking unit 312, the management command processing unit 313, the bad block processing unit 314, and the UECC (uncorrectable error) unit 315, is a legal read command, program command, or erase command. And is processed by a program command processing unit 316, a read command processing unit 317, or an erase command processing unit (not shown).
Taking a program command as an example, the program command processing unit 316 processes the program command, writes data indicated by the program command into the buffer 318 or the data file 319, and adds the program command processing result to the command completion queue 340. For a read command, the read command processing unit 317 acquires data accessed by the read command from the cache 318 or the data file 319, and generates a read command processing result to be added to the command completion queue 340. Optionally, the read command processing result also carries data to be accessed by the read command. For an erase command, the erase command processing unit sets a flag to indicate that the physical block indicated by the erase command is erased.
Alternatively, the command format checking unit 311, the command rule checking unit 312, the management command processing unit 313, the bad block processing unit 314, the UECC (uncorrectable error) unit 315, the programming command processing unit 316, the read command processing unit 317, and the erase command processing unit are provided by a single thread, and the thread processes one command acquired from the command commit queue 330 at a time. Still alternatively, NVM storage medium emulator 310 instantiates multiple threads, each single thread providing command format checking unit 311, command rule checking unit 312, management command processing unit 313, bad block processing unit 314, UECC (uncorrectable error) unit 315, programming command processing unit 316, read command processing unit 317, and erase command processing unit.
NVM storage media emulator 310 also includes cache 318 and data file 319 to emulate the physical storage space provided by multiple NVM chips. Cache 318 is provided by the memory of the computer/server running NVM storage media emulator 310, and data file 319 is stored in a mechanical hard disk, solid state disk, or other storage device.
The cache 318 serves as a cache for data files 319. The cache 318 includes a plurality of cache molecules. The buffer unit has a size of several MB, several tens of MB, or even hundreds of MB. The cache unit is the minimum unit of allocation and replacement of the cache. The cache unit is written to the data file 319 in its entirety, read from the data file 319 in its entirety, or allocated in its entirety.
FIG. 4 is a schematic diagram of a large block and virtual address space according to an embodiment of the present application.
A chunk includes a physical block from each of a plurality of logical units (referred to as a logical unit group). Preferably, each logical unit provides a physical block for a large block. By way of example, a large block is constructed on every 16 Logical Units (LUNs). Each chunk includes 16 physical blocks, from each of 16 Logical Units (LUNs). In the example of FIG. 4, chunk 0 includes physical chunk 0 from each of the 8 Logical Units (LUNs), and chunk 1 includes physical chunk 1 from each Logical Unit (LUN). There are a variety of other ways to construct the chunk.
As an alternative, page stripes are constructed in large blocks, with physical pages of the same physical address in each Logical Unit (LUN) constituting a "page stripe". In FIG. 4, physical pages P0-0, P0-1 and … … and P0-7 form page stripe 0, where physical pages P0-0, P0-1 and … … are used to store user data and physical pages P0-7 are used to store parity data calculated from all user data within the stripe. Similarly, in FIG. 4, physical pages P2-0, P2-1 and … …, and P2-7 constitute page stripe 2. Alternatively, the physical page used to store the parity data may be located anywhere in the page stripe.
According to embodiments of the present application, the control component manages the physical memory space provided by the plurality of NVM chips in large blocks. When writing data to a large block, data is written sequentially to each page stripe of the large block. Each physical block within a large block is erased as a whole. It will be appreciated, however, that the erase commands provided by the media interface to the NVM chip or NVM storage media emulator are erase commands for individual physical blocks, with other commands possibly interposed between these erase commands.
The NVM storage medium emulator emulates a plurality of NVM chips with a virtual address space to provide the physical storage space of the control component. The virtual address space includes an address space provided by a plurality of virtual blocks. The plurality of virtual blocks constituting the virtual address space have consecutive numbers, for example, from 0 to N, N representing the largest number of virtual blocks. The virtual blocks are in one-to-one correspondence with the large blocks provided by the plurality of NVM chips emulated by the NVM storage medium emulator. Referring to fig. 4, big block 0 corresponds to virtual block 0, and big block 1 corresponds to virtual block 1. The virtual block has the same size as the large block. The memory space provided by each page stripe of a large block is mapped consecutively to the address space of the virtual block by the page stripe number. Each physical page within the page stripe is also mapped consecutively to the address space of the virtual block.
One or more physical blocks of a large block may be bad blocks. Optionally, bad blocks are also mapped to the address space of the virtual block. One or more bad blocks of its corresponding big block are also marked along with the virtual block. Optionally, the address space of the virtual block to which the bad block is mapped exhibits different characteristics when accessed than other address spaces.
Fig. 4 also illustrates the mapping from the virtual address space to a cache unit or data file unit.
NVM storage media emulators provide storage capacity for virtual address space with cache units of cache 318 (see also fig. 3) or data file units of data file 319. The cache unit has the same size as the data file unit. The virtual address space provided by the virtual block is mapped to one or more cache units or data file units. For example, the virtual address space represented by virtual block 0 in FIG. 4 is mapped to cache unit 0 and cache unit 1. The former part of the virtual address space represented by virtual block 2 is mapped to cache unit 2, while the latter part is not mapped to any cache unit or data file unit. The former part of the virtual address space represented by virtual block 4 is mapped to cache unit 10 and the latter part is mapped to data file unit 20.
For example, when data is written to the virtual address space represented by virtual block 0 (programming command is received), the cache location to which it is mapped and the offset location within the cache location are determined from the accessed virtual address space, and the data is written to the cache location to complete the simulation of the programming command. When data is read out from the virtual address space represented by virtual block 4 (a read command is received), its offset position mapped into data file unit 20 and within data file unit 20 is determined from the accessed virtual address space, and the data is retrieved from data file unit 20 as a response to the read command (as an example, the contents of data file unit 20 are not loaded into the cache).
When writing data into the virtual address space represented by the virtual block 4 (receiving a programming command), it is determined that it is mapped to the data file unit 20 according to the accessed virtual address space, an empty buffer unit is allocated, the contents of the data file unit 20 are loaded into the allocated buffer unit, and the data indicated by the programming command is written into the allocated buffer unit. When data is read out from the virtual address space represented by virtual block 0 (a read command is received), the offset position mapped to the cache unit 1 and within the cache unit 1 is determined from the accessed virtual address space, and the data is acquired from the cache unit 1 as a response to the read command.
Fig. 5 illustrates a virtual block table according to yet another embodiment of the present application.
In the embodiment of fig. 5, the virtual address space provided by the virtual block is mapped to a cache unit or a data file unit. The virtual block table records a mapping of virtual blocks to cache units or data file units that provide storage capacity for the virtual blocks. The virtual block table provides a mapping of virtual address space to a cache location or data file.
The mapping of physical addresses to virtual address space indicated by commands received from the NVM storage media emulator is resolvable. For example, according to the Logical Unit (LUN) number and the physical block number of the physical address, the corresponding large block number is obtained according to the large block construction mode, and the virtual block number is obtained. And obtaining the offset in the virtual block according to the physical block number and the physical page address of the physical address. And obtaining a cache unit or a data file unit for providing storage space for the virtual block according to the virtual block table, thereby completing conversion from the physical address of the command to the cache unit or the data file unit so as to simulate access to the physical address of the NVM chip by accessing the cache unit and/or the data file unit.
The virtual block table includes a plurality of entries, each entry indicating a mapping of one of the virtual blocks to a cache unit or a data file unit. The entry may include a virtual block number and a cache unit index or a data file index. Optionally, the sequence number or position of an entry in the virtual block table implies the virtual block number it represents. Still optionally, the entries of the virtual block table also include additional information indicating the location of each bad block of the large block to which the virtual block corresponds, and/or the status of each physical block/physical page (erased, written, number of times erased, time data was written, etc.).
Referring back to fig. 3, the command format check unit 311 processes the command acquired from the command submission queue 330. The command format checking unit 311 checks whether the format of the acquired command meets the requirements of the NVM chip interface protocol, for example, the command type (program, read, erase, set feature, etc.) indicated by the command should be known, and other parts of the command correspond to the command type. For example, if the command is a read command, the command should also include a portion of a specified length and a specified number of indicated addresses; in the case of an erase command, the physical block number should be indicated in the command and no data should be included, and the physical block number should be within a specified range to indicate an objectively existing physical block.
The command format checking unit 311 checks whether the format of the single command satisfies the requirements of the NVM chip interface protocol. For commands meeting the requirements of the NVM chip interface protocol, the command is passed to the command rule checking unit 312 for continued processing, for commands not meeting the requirements of the NVM chip interface protocol, a command processing result is generated indicating that the command format does not meet the requirements of the NVM chip interface protocol, and is added to the command completion queue 340 to complete processing of the command without being passed to the command rule checking unit 312 or other processing units.
The command rule checking unit 312 processes the commands from the command format checking unit 311 and checks whether the constraint condition of the specified NVM chip is satisfied between a single command or a plurality of commands. For example, for a read command, the physical page it accesses should be a physical page that has been written with data, if the physical page it accesses is a physical page in the erased state, then the constraints of the NVM chip are not met; for a write command, the physical page it accesses should be the physical page in the erased state, and not the physical page to which data has been written; for an erase command, the physical block it accesses should be the physical block to which data is written, and should not be the physical block in the erased state. As yet another example, the command rule checking unit checks whether a plurality of commands satisfy a specified constraint condition. For example, an erase pause command is to be applied to a physical block that is processing an erase command, and an erase resume command is to be applied to a physical block that has just received an erase pause command. For program commands that are adjacent to each other in front of the same physical block, the physical pages accessed should have a specified order, etc.
If the command rule checking unit 312 checks the current command and does not find that it does not satisfy the specified constraint, the command is passed to the management command processing unit 313 for continued processing; if it is found that the specified constraint is not satisfied, a command processing result indicating that the command rule does not satisfy the specified constraint is generated and added to the command completion queue 340 to complete processing of the command without passing to the management command processing unit 313 or other processing units.
The management command processing unit 313 processes management commands such as a Set Feature (Set Feature) command, a Read Feature (Read Feature) command, or a reset command. For the management command, the management command processing unit generates a management command processing result according to the management setting, for example, the logic unit is in a specified state, or acquires the accessed state information, and adds the management command processing result to the command completion queue 340 to complete the processing of the command without passing to the bad block processing unit 314 or other processing units. If the management command processing unit 313 receives a non-management command, the command is passed to the bad block processing unit 314 or other processing units.
Bad block processing unit 314 processes commands that access bad blocks. The bad block processing unit 314 identifies whether the physical address accessed by the program command or the read command belongs to a bad block, for example, accesses a virtual block table to acquire whether the accessed physical address belongs to a bad block. For a program command accessing a bad block, the bad block processing unit 314 generates a processing result indicating that the program command processing failed, and adds to the command completion queue 340 to complete the processing of the command without passing to the UECC unit 315 or other processing units. For a read command accessing a bad block, the bad block processing unit 314 generates data having uncorrectable errors as a result of processing of the read command and adds to the command completion queue 340 to complete processing of the command without passing to the UECC unit 315 or other processing units. Alternatively, for an erase command accessing a bad block, the bad block processing unit 314 generates a processing result indicating that the erase command processing failed, and adds to the command completion queue 340 to complete the processing of the command without passing to the UECC unit 315 or other processing units. If bad block processing unit 314 receives a command that does not access a bad block, the command is passed to UECC unit 315 or other processing units.
The UECC unit 315 generates data in which uncorrectable errors exist. For example, for a read command, the UECC unit 315 processes the read command with a specified probability, generates data having uncorrectable errors in response to the processed read command as a processing result of the read command, and adds the data to the command completion queue 340 to complete the processing of the command without passing to other processing units. With a specified probability, read commands that are not processed by the UECC unit are passed to other processing units. Still by way of example, for a programming command, the UECC unit 315 recognizes that the address accessed by the writing command does not satisfy a specified relationship (e.g., a sequential increasing relationship) with the address of one or more writing commands previously accessing the same physical block, changes the data to be written by the programming command to data in which there is an uncorrectable error, and generates a result indicating that the programming command processing is completed. Optionally, in the result indicating that the programming command processing is complete, the write data is also marked for uncorrectable errors. Still by way of example, for a program command, the UECC unit 315 also identifies the number of times the physical block accessed by the write command is erased, and if the number of times is greater than a specified value, changes the data to be written by the program command to data having uncorrectable errors, and generates a result indicating that the program command processing is complete.
According to the embodiment of fig. 3, the command that has not yet been processed after processing by the UECC unit 315 is a normal read command, program command or erase command. The normal read command, program command, or erase command is processed by the read command processing unit 316, program command processing unit 317, or erase command processing unit, respectively.
FIG. 6 illustrates a flow chart of a programming command processing unit according to an embodiment of the present application.
For a programming command, a programming command processing unit processes the programming command, obtains a physical address of the programming command (610); the physical address accessed by the programming command is used to obtain the chunk to which it belongs, and the virtual block table is accessed according to the chunk number, and a cache unit or a data file unit providing storage space for the virtual block is obtained from the virtual block table (620). If the memory space in the entry of the virtual block table in which the physical address accessed by the program command is recorded is provided by the cache unit, the data to be written by the program command is written into the cache unit (630).
Judging whether the storage space corresponding to the physical address of the programming command is provided by the data file unit, if the storage space in which the physical address accessed by the programming command is recorded in the entry of the virtual block table is provided by the data file unit (640), loading the data of the data file unit corresponding to the physical address of the programming command into a newly allocated cache unit (650), and turning to execute step 630, and writing the data to be written by the programming command into the newly allocated cache unit. And updating the virtual block table, wherein the memory space for recording the physical address accessed by the programming command in the entry of the virtual block table is provided by the newly allocated cache unit.
If the memory space in the entry of the virtual block table where the physical address accessed by the programming command is recorded is not provided by either the cache unit or the data file unit (640), meaning that no memory space has been allocated for the physical address, then the cache unit is allocated from the cache (660), and the process proceeds to step 630, where the data to be written by the programming command is written to the newly allocated cache unit. And updating the virtual block table, wherein the memory space for recording the physical address accessed by the programming command in the entry of the virtual block table is provided by the newly allocated cache unit.
And the programming command processing unit also generates a processing result of the programming command and adds the processing result to the command completion queue.
It can be appreciated that, as the command rule checking unit and the UECC unit process, the program command processed by the obtained program command processing unit will not access the physical page that has been written, and the accessed physical page also satisfies the constraint condition of the NVM chip. Similarly, a read command processed by the read command processing unit will not access a physical page in the erased state nor will it access a bad block.
For a read command, the read command processing unit processes the read command, obtains a large block to which the read command belongs according to a physical address accessed by the read command, accesses the virtual block table according to the large block number, and obtains a cache unit or a data file unit for providing a storage space for the virtual block from the virtual block table. If the storage space of the physical address accessed by the read command is recorded in the entry of the virtual block table, the buffer unit provides the storage space, and the data is acquired from the buffer unit as a processing result of the read command and is added to the command completion queue. If the memory space in the virtual block table in which the physical address accessed by the read command is recorded is provided by the data file unit, the data is acquired from the data file unit as a result of processing the read command and is added to the command completion queue.
Optionally, the read command processing unit also adds a certain number of errors, for example, flipping some bits, to simulate the characteristics of the NVM storage medium in the data acquired as a result of the read command processing.
For an erase command, the erase command processing unit sets a flag in the virtual block table to indicate that the physical block indicated by the erase command is erased.
While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application. It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.
Claims (10)
1. A method of simulating an NVM storage medium, comprising:
responding to a first command which is sent by the acquisition control component and follows an NVM chip interface protocol;
if the first command is a legal write command, acquiring a corresponding first virtual block according to a physical address accessed by the first command, wherein a virtual address space is used for simulating a physical address space provided by a plurality of NVM chips to a control component, and the virtual address space comprises the address space provided by the plurality of virtual blocks; the virtual blocks are in one-to-one correspondence with the large blocks provided by the simulated multiple NVM chips; the large block comprises physical blocks from a plurality of logic units, and the control part manages physical storage spaces provided by the plurality of NVM chips according to the large block;
acquiring a first cache unit or a first data file unit which provides a storage space for a first virtual block; writing data corresponding to the first command into a first cache unit or a first data file unit; wherein,
obtaining a big block corresponding to the physical address according to the logical unit number and the physical block number of the physical address and the construction mode of the big block, and obtaining a first virtual block corresponding to the physical address according to the corresponding relation between the big block and the virtual block;
the cache unit or the data file unit provides the capacity for the virtual address space provided by the virtual block, the mapping relation between the virtual block and the cache unit or the data file unit is managed through the virtual block table, and the first cache unit or the first data file unit providing the storage space for the first virtual block is obtained according to the mapping relation.
2. The NVM storage medium emulation method of claim 1, wherein,
if the first command is a legal read command, acquiring a corresponding first virtual block according to a physical address accessed by the first command;
acquiring a first cache unit or a first data file unit which provides a storage space for a first virtual block; and acquiring data from the first cache unit or the first data file unit.
3. The NVM storage medium emulation method of claim 1, wherein,
if the first command is a legal erasing command, acquiring a corresponding first virtual block according to a physical address accessed by the first command; and erasing the physical block indicated to be erased by the first command, and setting an erasure flag in the first virtual block.
4. The NVM storage medium emulation method of any of claims 1-3, wherein in response to obtaining a first command that complies with the NVM chip interface protocol, checking whether a format of the first command meets requirements of the NVM chip interface protocol, and checking whether the first command meets constraints of the NVM chip, if both meet, the first command is a legal command, otherwise generating a processing result that the command is illegal.
5. The NVM storage medium emulation method of claim 4, wherein the constraints of the NVM chip comprise:
if the first command is a read command or an erase command, the physical page accessed by the first command should be a physical page to which data has been written;
if the first command is a write command, the physical page accessed by the first command should be a physical page in an erased state.
6. The NVM storage medium emulation method of claim 4, wherein the format of the first command satisfies the requirements of the NVM chip interface protocol and satisfies the constraints of the NVM chip, and if the physical address accessed by the first command belongs to a bad block, generating a processing result of the processing failure.
7. The NVM storage medium emulation method of claim 6, wherein,
if the first command is a programming command for accessing the bad block, generating a processing result indicating that the programming command fails to be processed;
if the first command is a read command for accessing the bad block, generating data with uncorrectable errors as a processing result of the read command;
if the first command is an erase command to access the bad block, a processing result indicating that the erase command processing failed is generated.
8. The NVM storage medium emulation method of claim 4, wherein the format of the first command satisfies the requirements of the NVM chip interface protocol and satisfies the constraints of the NVM chip, and wherein data with uncorrectable errors are generated for the read command with a specified probability as a result of processing the read command.
9. The NVM storage medium emulation method of claim 4, wherein the format of the first command satisfies the requirements of the NVM chip interface protocol and satisfies the constraints of the NVM chip, and if the address accessed by the first command does not satisfy the specified relationship with the address of one or more write commands previously accessing the same physical block, changing the data corresponding to the first command to data having uncorrectable errors.
10. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the NVM storage medium emulation method of one of the preceding claims 1-9 when executing the program.
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| CN112559387B (en) * | 2020-12-23 | 2023-05-02 | 湖南国科微电子股份有限公司 | Read request processing method, device, equipment and medium |
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