CN111313886A

CN111313886A - SR latch circuit based on interconnection line capacitance

Info

Publication number: CN111313886A
Application number: CN201911171038.4A
Authority: CN
Inventors: 张跃军; 赵志伟; 李林
Original assignee: Ningbo University
Current assignee: Ningbo University
Priority date: 2019-11-26
Filing date: 2019-11-26
Publication date: 2020-06-19
Anticipated expiration: 2039-11-26
Also published as: CN111313886B

Abstract

The invention discloses an SR latch circuit based on interconnection line capacitance, which comprises a first NOR gate circuit and a second NOR gate circuit, wherein the first NOR gate circuit comprises a first node isolation module, a first capacitance value adjusting module and a first sampling module; the advantage is that the device has the ability of resisting line crosstalk, and can still output correct logic signals when being interfered by crosstalk noise.

Description

SR latch circuit based on interconnection line capacitance

Technical Field

The present invention relates to an SR latch circuit, and more particularly, to an SR latch circuit based on interconnection line capacitors.

Background

Sequential logic can construct a finite state machine, and the finite state machine and the combinational logic are fused to construct an integrated circuit with multiple functions. Sequential logic circuits have become the fundamental structure in the development of today's integrated circuits. The storage element is one of the most critical elements in a sequential logic circuit, and the SR latch circuit is the basis for constructing various storage elements, so that the intensive research on the SR latch circuit has a profound significance for promoting the overall development of integrated circuits.

As the spatial dimensions of metal interconnect lines in integrated circuits become smaller, problems, such as noise, result. In the industry, the trend of increasing resistance due to smaller and smaller line width of metal interconnects in integrated circuits is alleviated, so that the aspect ratio of the metal interconnects is continuously increased along with the reduction of the process size. However, increasing the vertical thickness of the metal interconnection line increases the lateral capacitance, which results in an increasing proportion of the multi-layer inter-metal lateral capacitance to the total capacitance between the lines.

The conventional SR latch circuit is generally composed of two complementary CMOS NOR gates, and the complementary CMOS NOR gate circuit is composed of two PMOS transistors and two NMOS transistors. When two complementary CMOS NOR gate circuits are connected through a physical long-distance metal interconnection line, the transverse capacitance between multiple layers of metal is increased due to the fact that the space size of the metal interconnection line is smaller and smaller, at the moment, signals of the complementary CMOS NOR gate are prone to being interfered by crosstalk noise to output wrong logic signals, the complementary CMOS NOR gate circuit is abnormal in function, the SR latch circuit is abnormal in function, and finally the integrated circuit is failed.

Disclosure of Invention

The invention aims to solve the technical problem of providing an SR latch circuit based on interconnection line capacitance, which has the wire crosstalk resistance and can still output correct logic signals when being interfered by crosstalk noise.

The technical scheme adopted by the invention for solving the technical problems is as follows: an SR latch circuit based on interconnection line capacitance comprises a first NOR gate circuit and a second NOR gate circuit, wherein the first NOR gate circuit comprises a first node isolation module, a first capacitance value adjusting module and a first sampling module, the first node isolation module comprises a first MOS tube and a second MOS tube, the first MOS tube and the second MOS tube are both N-type MOS tubes, the drain electrode of the first MOS tube is connected with a power supply, the source electrode of the first MOS tube is connected with the drain electrode of the second MOS tube, the connecting end of the first MOS tube and the drain electrode of the second MOS tube is the output end of the first node isolation module, the source electrode of the second MOS tube is grounded, the grid electrode of the first MOS tube, the substrate of the first MOS tube, the grid electrode of the second MOS tube and the substrate of the second MOS tube are grounded, the first capacitance value adjusting module comprises a third MOS tube and a fourth MOS tube, the third MOS transistor and the fourth MOS transistor are both N-type MOS transistors, the grid electrode of the third MOS transistor is connected with the grid electrode of the fourth MOS transistor, the connecting end of the third MOS transistor is the output end of the first capacitance value adjusting module, the output end of the first capacitance value adjusting module is connected with the output end of the first node isolating module, the source electrode of the third MOS transistor, the drain electrode of the third MOS transistor are connected with the substrate of the third MOS transistor, the connecting end of the third MOS transistor is the first input end of the first capacitance value adjusting module, the first input end of the first capacitance value adjusting module is the first input end of the first NOR gate circuit, the source electrode of the fourth MOS transistor, the drain electrode of the fourth MOS transistor and the substrate of the fourth MOS transistor are connected, the connecting end of the fourth MOS transistor is the second input end of the first capacitance value adjusting module, and the second input end of the first capacitance value adjusting module is the second input end of the first NOR gate circuit, the channel width adjusting range of the third MOS tube is 300-450 nm, the channel length adjusting range of the third MOS tube is 400-550 nm, the channel width adjusting range of the fourth MOS tube is 300-450 nm, and the channel length adjusting range of the fourth MOS tube is 400-550 nm; the first sampling module comprises a fifth MOS tube and a sixth MOS tube, the fifth MOS tube is a P-type MOS tube, the sixth MOS tube is an N-type MOS tube, the source electrode of the fifth MOS tube is connected with a power supply, the grid electrode of the fifth MOS tube is connected with the grid electrode of the sixth MOS tube, the connecting end of the grid electrode of the fifth MOS tube and the grid electrode of the sixth MOS tube is the input end of the first sampling module, the input end of the first sampling module is connected with the output end of the first node isolation module, the drain electrode of the fifth MOS tube is connected with the drain electrode of the sixth MOS tube, the connecting end of the drain electrode of the fifth MOS tube and the drain electrode of the sixth MOS tube is the output end of the first sampling module, the output end of the first sampling module is the output end of the first NOR gate circuit, the substrate of the fifth MOS tube is connected with the power supply, the substrate of the sixth MOS tube is grounded, the source electrode of the sixth MOS tube is grounded, the channel width adjusting range of the fifth MOS tube is 50-60 nm, the channel length adjusting range of the sixth MOS tube is 80-120 nm, the channel width adjusting range of the sixth MOS tube is 50-60 nm, and the channel length adjusting range of the sixth MOS tube is 150-200 nm; the second nor gate circuit comprises a second node isolation module, a second capacitance value adjusting module and a second sampling module, the second node isolation module comprises an eleventh MOS tube and a twelfth MOS tube, the eleventh MOS tube and the twelfth MOS tube are both N-type MOS tubes, a drain electrode of the eleventh MOS tube is connected with a power supply, a source electrode of the eleventh MOS tube is connected with a drain electrode of the twelfth MOS tube, a connecting end of the eleventh MOS tube and the drain electrode of the twelfth MOS tube is an output end of the second node isolation module, a source electrode of the twelfth MOS tube is grounded, a grid electrode of the eleventh MOS tube, a substrate of the eleventh MOS tube, a grid electrode of the twelfth MOS tube and a substrate of the twelfth MOS tube are all grounded, the second capacitance value adjusting module comprises a ninth MOS tube and a tenth MOS tube, and the ninth MOS tube and the tenth MOS tube are both N-type MOS tubes, the grid electrode of the ninth MOS tube is connected with the grid electrode of the tenth MOS tube, the connecting end of the ninth MOS tube is the output end of the second capacitance value adjusting module, the output end of the second capacitance value adjusting module is connected with the output end of the second node isolating module, the source electrode of the ninth MOS tube, the drain electrode of the ninth MOS tube and the substrate of the ninth MOS tube are connected, and the connecting end of the ninth MOS tube is the first input end of the second capacitance value adjusting module; the first input end of the second capacitance value adjusting module is the first input end of the second nor circuit, the source electrode of the tenth MOS transistor, the drain electrode of the tenth MOS transistor and the substrate of the tenth MOS transistor are connected, and the connection end of the tenth MOS transistor is the second input end of the second capacitance value adjusting module, the second input end of the second capacitance value adjusting module is the second input end of the second nor circuit, the channel width adjusting range of the ninth MOS transistor is 300-450 nm, the channel length adjusting range of the ninth MOS transistor is 400-550 nm, the channel width adjusting range of the tenth MOS transistor is 300-450 nm, and the channel length adjusting range of the tenth MOS transistor is 400-550 nm; the second sampling module comprises a seventh MOS tube and an eighth MOS tube, the seventh MOS tube is a P-type MOS tube, the eighth MOS tube is an N-type MOS tube, the source electrode of the seventh MOS tube is connected with a power supply, the substrate of the seventh MOS tube is connected with a power supply, the grid electrode of the seventh MOS tube is connected with the grid electrode of the eighth MOS tube, the connecting end of the seventh MOS tube is the input end of the second sampling module, the input end of the second sampling module is connected with the output end of the second node isolation module, the drain electrode of the seventh MOS tube is connected with the drain electrode of the eighth MOS tube, the connecting end of the seventh MOS tube is the output end of the second sampling module, the output end of the second sampling module is the output end of the second NOR gate circuit, the substrate of the eighth MOS tube is grounded, the source electrode of the eighth MOS tube is grounded, the channel width adjusting range of the seventh MOS tube is 50-60 nm, the channel length adjusting range of the seventh MOS tube is 80-120 nm, the channel width adjusting range of the eighth MOS tube is 50-60 nm, and the channel length adjusting range of the eighth MOS tube is 150-200 nm. The second input end of the first NOR gate circuit is the first input end of the SR latch circuit, the first input end of the second NOR gate circuit is the second input end of the SR latch circuit, the second input end of the second NOR gate circuit is connected with the output end of the first NOR gate circuit, the connecting end of the second NOR gate circuit is the first output end of the SR latch circuit, the output end of the second NOR gate circuit is connected with the first input end of the first NOR gate circuit, and the connecting end of the second NOR gate circuit is the second output end of the SR latch circuit.

Compared with the prior art, the invention has the advantages that the first NOR gate circuit is formed by the first node isolation module, the first capacitance value adjusting module and the first sampling module, the first node isolation module comprises a first MOS (metal oxide semiconductor) transistor and a second MOS transistor, the first capacitance value adjusting module comprises a third MOS transistor and a fourth MOS transistor, the first sampling module comprises a fifth MOS transistor and a sixth MOS transistor, the second NOR gate circuit is formed by the second node isolation module, the second capacitance value adjusting module and the second sampling module, the second node isolation module comprises an eleventh MOS transistor and a twelfth MOS transistor, the second capacitance value adjusting module comprises a ninth MOS transistor and a tenth MOS transistor, and the second sampling module comprises a seventh MOS transistor and an eighth MOS transistor. When the distance between the two metal wires is small or the longitudinal relative area of the metal layers of the interconnection wire is changed, the action degree of the disturbed wire is changed, the coupling capacitance between the disturbed wire and the disturbed wire is changed, the values of the channel width W and the channel length L of a third MOS tube M3, a fourth MOS tube M4, a ninth MOS tube M9 and a tenth MOS tube M10 in the first capacitance value adjusting module and the second capacitance value adjusting module are simultaneously adjusted properly, the channel width adjusting range of the third MOS tube is 300-450 nm, the channel length adjusting range of the third MOS tube is 400-550 nm, the channel width adjusting range of the fourth MOS tube is 300-450 nm, the channel length adjusting range of the fourth MOS tube is 400-550 nm, the channel width adjusting range of the ninth MOS tube is 300-450 nm, the channel length adjusting range of the ninth MOS tube is 400-550 nm, and the channel width adjusting range of the tenth MOS tube is 300-450 nm, the channel length adjusting range of the tenth MOS tube is 400-550 nm, meanwhile, in order to avoid the problem of overlarge voltage value generated at the output end of the first node isolation module and the output end of the second node isolation module, the channel width W and the channel length L of an inverter formed by a fifth MOS tube M5, a sixth MOS tube M6, a seventh MOS tube M7 and an eighth MOS tube M8 are properly adjusted, so that the output end Q and the inverted output end Q' of the latch output correct logic signals, the channel width adjusting range of the fifth MOS tube is 50-60 nm, the channel length adjusting range of the fifth MOS tube is 80-120 nm, the channel width adjusting range of the sixth MOS tube is 50-60 nm, the channel length adjusting range of the sixth MOS tube is 150-200 nm, the channel width adjusting range of the seventh MOS tube is 50-60 nm, and the channel length adjusting range of the seventh MOS tube is 80-120 nm, the channel width adjusting range of the eighth MOS tube is 50-60 nm, the channel length adjusting range of the eighth MOS tube is 150-200 nm, the silicon substrate and the grid electrode of the first MOS tube, the second MOS tube, the eleventh MOS tube and the twelfth MOS tube are grounded, and then are respectively connected in series with a power supply VDD and a ground VSS after forming a large resistor so as to simulate that VDD in an actual device reaches a disturbed metal wire through a SiO2 insulating medium layer, in the working process of the SR latch circuit, the first MOS tube, the second MOS tube, the eleventh MOS tube and the twelfth MOS tube are always in a closed state and only used as large resistors to provide stable isolation conditions for signal input connected into a first NOR gate circuit and a second NOR gate circuit, and the third MOS tube, the fourth MOS tube, the ninth MOS tube and the tenth MOS tube in the first capacitance value adjusting module and the second capacitance value adjusting module adopt specific sizes to balance the influence of peripheral interference wires on the disturbed wire, the SR latch circuit has the advantages that the coupling capacitance value is kept relatively stable, the first NOR gate circuit and the second NOR gate circuit are kept to work normally, the fifth MOS transistor and the sixth MOS transistor as well as the seventh MOS transistor and the eighth MOS transistor form two inverters, low level signals at the output end of the first node isolation module and the output end of the second node isolation module can be correctly identified, and correct NAND logic signals are output.

Drawings

FIG. 1 is a circuit diagram of an interconnect line capacitance based SR latch circuit of the present invention;

FIG. 2 is a simulation plot of a first NOR gate circuit of the interconnect line capacitance based SR latch circuit of the present invention;

FIG. 3 is a graph of a simulation of the delay of the falling edge output by the first NOR gate of the interconnection line capacitance based SR latch circuit of the present invention;

FIG. 4 is a graph of a simulation of the delay in the rising edge output of the first NOR gate of the interconnection line capacitance based SR latch circuit of the present invention;

FIG. 5 is a simulation graph of the interconnect line capacitance based SR latch circuit of the present invention;

FIG. 6 is a graph of a simulation of the delay when the first output terminal of the interconnection line capacitance based SR latch circuit of the present invention outputs a falling edge;

FIG. 7 is a simulation graph of the delay of the first output terminal of the SR latch circuit based on the interconnection line capacitance of the present invention when outputting a rising edge.

Detailed Description

The invention is described in further detail below with reference to the accompanying examples.

Example (b): as shown in fig. 1, an SR latch circuit based on interconnection line capacitance includes a first nor gate and a second nor gate, the first nor gate includes a first node isolation module, a first capacitance value adjustment module and a first sampling module, the first node isolation module includes a first MOS tube M1 and a second MOS tube M2, the first MOS tube M1 and the second MOS tube M2 are both N-type MOS tubes, a drain of the first MOS tube M1 is connected to a power supply, a source of the first MOS tube M1 and a drain of the second MOS tube M2 are connected and a connection end thereof is an output end V1 of the first node isolation module, a source of the second MOS tube M2 is grounded, a gate of the first MOS tube M1, a substrate of the first MOS tube M1, a gate of the second MOS tube M2 and a substrate of the second MOS tube M2 are both grounded, the first capacitance value adjustment module includes a third MOS tube M3 and a fourth MOS tube M4, a gate of the third MOS tube M638 and a gate of the fourth MOS tube M3 are both connected and a gate of the fourth MOS tube M638 and a gate of the fourth MOS tube M4 are both connected and a gate of the first MOS tube M638 and a gate of the fourth MOS tube M638 is connected and a third MOS tube M638 is The output end of the first capacitance value adjusting module is connected with the output end of the first node isolating module, the source electrode of the third MOS transistor M3, the drain electrode of the third MOS transistor M3 and the substrate of the third MOS transistor M3 are connected, and the connection end thereof is the first input end of the first capacitance value adjusting module, the first input end of the first capacitance value adjusting module is the first input end of the first nor gate circuit, the source electrode of the fourth MOS transistor M4, the drain electrode of the fourth MOS transistor M4 is connected with the substrate of the fourth MOS transistor M4, the connection end of the fourth MOS transistor M4 is the second input end of the first capacitance value adjusting module, the second input end of the first capacitance value adjusting module is the second input end of the first NOR gate circuit, the channel width adjusting range of the third MOS transistor M3 is 450-550 nm, the channel length adjusting range of the third MOS transistor M3 is 400-550 nm, the channel width adjusting range of the fourth MOS transistor M4 is 300-450 nm, and the channel length adjusting range of the fourth MOS transistor M4 is 400-550 nm; the first sampling module comprises a fifth MOS tube M5 and a sixth MOS tube M6, the fifth MOS tube M5 is a P-type MOS tube, the sixth MOS tube M6 is an N-type MOS tube, and the source of the fifth MOS tube M5The grid of the fifth MOS tube M5 is connected with the grid of the sixth MOS tube M6, the connection end of the fifth MOS tube M5 is the input end of the first sampling module, the input end of the first sampling module is connected with the output end of the first node isolation module, the drain of the fifth MOS tube M5 is connected with the drain of the sixth MOS tube M6, the connection end of the fifth MOS tube M6 is the output end of the first sampling module, the output end of the first sampling module is the output end of the first NOR gate circuit, the substrate of the fifth MOS tube M5 is connected with the power supply, the substrate of the sixth MOS tube M6 is grounded, the source of the sixth MOS tube M6 is grounded, the channel width adjustment range of the fifth MOS tube M5 is 50-60 nm, the channel length adjustment range of the sixth MOS tube M6 is 150-120 nm, the channel width adjustment range of the sixth MOS tube M6 is 50-60 nm, and the channel length adjustment range of the sixth MOS tube M6 is 150-200 nm; the second nor gate circuit comprises a second node isolation module, a second capacitance value adjustment module and a second sampling module, the second node isolation module comprises an eleventh MOS transistor M11 and a twelfth MOS transistor M12, the eleventh MOS transistor M11 and the twelfth MOS transistor M12 are both N-type MOS transistors, the drain of the eleventh MOS transistor M11 is connected to a power supply, the source of the eleventh MOS transistor M11 and the drain of the twelfth MOS transistor M12 are connected, and the connection end of the eleventh MOS transistor M11 and the connection end of the twelfth MOS transistor M12 is the output end V2 of the second node isolation module, the source of the twelfth MOS transistor M12 is grounded, the gate of the eleventh MOS transistor M11, the substrate of the eleventh MOS transistor M11, the gate of the twelfth MOS transistor M12 and the substrate of the twelfth MOS transistor M12 are all grounded, the second capacitance value adjustment module comprises a ninth MOS transistor M9 and a tenth MOS transistor M10, the ninth MOS transistor M9 and the tenth MOS transistor M10 are both N-type MOS transistors, the ninth MOS transistor M9 and the connection end of the ninth MOS transistor M10 are connected, and the connection end of the second capacitance value adjustment module, the output end of the second capacitance value adjusting module is connected with the output end of the second node isolating module, the source electrode of the ninth MOS tube M9, the drain electrode of the ninth MOS tube M9 and the substrate of the ninth MOS tube M9 are connected, and the connecting end of the ninth MOS tube M9 is the first input end of the second capacitance value adjusting module; the first input end of the second capacitance value adjusting module is the first input end of the second nor gate circuit, the source electrode of the tenth MOS transistor M10, the drain electrode of the tenth MOS transistor M10 and the substrate of the tenth MOS transistor M10 are connected, the connection end of the connection end is the second input end of the second capacitance value adjusting module, the second input end of the second capacitance value adjusting module is the second input end of the second nor gate circuit, and the ninth input end of the ninth capacitance value adjusting module is the first input end of the second nor gate circuitThe channel width adjusting range of the MOS transistor M9 is 300-450 nm, the channel length adjusting range of the ninth MOS transistor M9 is 400-550 nm, the channel width adjusting range of the tenth MOS transistor M10 is 300-450 nm, and the channel length adjusting range of the tenth MOS transistor M10 is 400-550 nm; the second sampling module comprises a seventh MOS tube M7 and an eighth MOS tube M8, the seventh MOS tube M7 is a P-type MOS tube, the eighth MOS tube M8 is an N-type MOS tube, the source of the seventh MOS tube M7 is connected with a power supply, the substrate of the seventh MOS tube M7 is connected with the power supply, the grid of the seventh MOS tube M7 is connected with the grid of the eighth MOS tube M8, the connecting end of the seventh MOS tube M3583 is the input end of the second sampling module, the input end of the second sampling module is connected with the output end of the second node isolation module, the drain of the seventh MOS tube M7 is connected with the drain of the eighth MOS tube M8, the connecting end of the seventh MOS tube M7 is the output end of the second sampling module, the output end of the second or not gate circuit, the substrate of the eighth MOS tube M8 is grounded, the source of the eighth MOS tube M8 is grounded, the channel width of the seventh MOS tube M7 is adjusted within a range of 50-60 nm, the channel length of the seventh MOS tube M7 is adjusted within a range of 120-60 nm, and the channel width of the eighth MOS tube M8 is adjusted, the channel length adjustment range of the eighth MOS transistor M8 is 150-200 nm. The second input end of the first NOR gate circuit is the first input end of the SR latch circuit and is connected with a first input signal S, the first input end of the second NOR gate circuit is the second input end of the SR latch circuit and is connected with a second input signal R signal, the second input end of the second NOR gate circuit is connected with the output end of the first NOR gate circuit, the connecting end of the second NOR gate circuit is the first output end of the SR latch circuit, a first output signal Q is output, the output end of the second NOR gate circuit is connected with the first input end of the first NOR gate circuit, the connecting end of the second NOR gate circuit is the second output end of the SR latch circuit, and a second output signal Q is output^’。

The simulation curve of the first nor gate circuit of the SR latch circuit based on the interconnection line capacitance of the present invention is shown in fig. 2, and it can be known from the analysis of fig. 2 that: when the voltage signal is induced at the node V, the low-threshold inverter samples the voltage signal to obtain that Q is 1; when the voltage is 3.5ns, S is 1, Q' is 1, a 710mV induced voltage between high and low level signals is generated at a node V, and a low threshold inverter is used for sampling to obtain Q is 0; at 4.5ns, S is 0 and Q' is 1, and a 490mV induced voltage generated at the node V1 is sampled by a low-threshold inverter to obtain Q is 0; at 5.5ns, S is 1 and Q' is 0, a 490mV induced voltage between the high and low level signals is generated at node V, sampled by a low threshold inverter, and shaped to obtain Q0.

The time delay of the first NOR gate circuit of the SR latch circuit based on the interconnection line capacitance is simulated when the first NOR gate circuit outputs the falling edge, the time delay simulation curve is shown in FIG. 3, and the analysis of FIG. 3 shows that: the fall delay time was 8.9 ps.

The time delay of the first NOR gate circuit of the SR latch circuit based on the interconnection line capacitance is simulated when the first NOR gate circuit outputs the rising edge, the time delay simulation curve is shown in FIG. 4, and the analysis of FIG. 4 shows that: the rise delay time of the output is 10.8 ps.

The SR latch circuit based on the interconnection line capacitance of the present invention is simulated, and the simulation curve is shown in fig. 5, and it can be known from analyzing fig. 5 that: when the signal is 3ns, R is 0 and S is 0, an induced voltage signal is generated at a node V1, and Q is 0 after sampling by a low-threshold inverter; at 4.5ns, R is 1 and S is 1, and after the induced voltage generated at the node V1 is sampled by the low-threshold inverter, the Q signal is output in an unstable state; at 7.5ns, R is 0 and S is 1, an induced voltage is generated at a node V1, and Q is 0 after sampling by a low-threshold inverter; at 9ns, R is 1 and S is 0, and the induced voltage generated at node V1 is sampled by a low-threshold inverter to obtain Q is 0.

The time delay of the first output end of the SR latch circuit based on the interconnection line capacitor of the present invention when outputting the falling edge is simulated, the time delay simulation curve is shown in fig. 6, and it can be known from analyzing fig. 6 that: the falling delay time of the output end signal Q is 117.2 ps; the output Q' fall delay time is 117.2 ps.

The time delay of the first output end of the SR latch circuit based on the interconnection line capacitor is simulated, the time delay simulation curve is shown in FIG. 7, and the analysis of FIG. 7 shows that: the rising delay time of the output end signal Q is 55.9 ps; the output Q' rise delay time is 59.4 ps.

Claims

1. An SR latch circuit based on interconnection line capacitance comprises a first NOR gate circuit and a second NOR gate circuit, and is characterized in that the first NOR gate circuit comprises a first node isolation module, a first capacitance value adjusting module and a first sampling module, the first node isolation module comprises a first MOS tube and a second MOS tube, the first MOS tube and the second MOS tube are both N-type MOS tubes, the drain electrode of the first MOS tube is connected with a power supply, the source electrode of the first MOS tube is connected with the drain electrode of the second MOS tube, the connecting end of the source electrode of the first MOS tube and the drain electrode of the second MOS tube is the output end of the first node isolation module, the source electrode of the second MOS tube is grounded, the grid electrode of the first MOS tube, the substrate of the first MOS tube, the grid electrode of the second MOS tube and the substrate of the second MOS tube are grounded, the first capacitance value adjusting module comprises a third MOS tube and a fourth MOS tube, the third MOS transistor and the fourth MOS transistor are both N-type MOS transistors, the grid electrode of the third MOS transistor is connected with the grid electrode of the fourth MOS transistor, the connecting end of the third MOS transistor is the output end of the first capacitance value adjusting module, the output end of the first capacitance value adjusting module is connected with the output end of the first node isolating module, the source electrode of the third MOS transistor, the drain electrode of the third MOS transistor are connected with the substrate of the third MOS transistor, the connecting end of the third MOS transistor is the first input end of the first capacitance value adjusting module, the first input end of the first capacitance value adjusting module is the first input end of the first NOR gate circuit, the source electrode of the fourth MOS transistor, the drain electrode of the fourth MOS transistor and the substrate of the fourth MOS transistor are connected, the connecting end of the fourth MOS transistor is the second input end of the first capacitance value adjusting module, and the second input end of the first capacitance value adjusting module is the second input end of the first NOR gate circuit, the channel width adjusting range of the third MOS tube is 300-450 nm, the channel length adjusting range of the third MOS tube is 400-550 nm, the channel width adjusting range of the fourth MOS tube is 300-450 nm, and the channel length adjusting range of the fourth MOS tube is 450-550 nm; the first sampling module comprises a fifth MOS tube and a sixth MOS tube, the fifth MOS tube is a P-type MOS tube, the sixth MOS tube is an N-type MOS tube, the source electrode of the fifth MOS tube is connected with a power supply, the grid electrode of the fifth MOS tube is connected with the grid electrode of the sixth MOS tube, the connecting end of the grid electrode of the fifth MOS tube and the grid electrode of the sixth MOS tube is the input end of the first sampling module, the input end of the first sampling module is connected with the output end of the first node isolation module, the drain electrode of the fifth MOS tube is connected with the drain electrode of the sixth MOS tube, the connecting end of the drain electrode of the fifth MOS tube and the drain electrode of the sixth MOS tube is the output end of the first sampling module, the output end of the first sampling module is the output end of the first NOR gate circuit, the substrate of the fifth MOS tube is connected with the power supply, the substrate of the sixth MOS tube is grounded, the source electrode of the sixth MOS tube is grounded, the channel width regulating range of the fifth MOS tube is 60nm, the channel length adjusting range of the sixth MOS tube is 80-120 nm, the channel width adjusting range of the sixth MOS tube is 50-60 nm, and the channel length adjusting range of the sixth MOS tube is 150-200 nm; the second nor gate circuit comprises a second node isolation module, a second capacitance value adjusting module and a second sampling module, the second node isolation module comprises an eleventh MOS tube and a twelfth MOS tube, the eleventh MOS tube and the twelfth MOS tube are both N-type MOS tubes, a drain electrode of the eleventh MOS tube is connected with a power supply, a source electrode of the eleventh MOS tube is connected with a drain electrode of the twelfth MOS tube, a connecting end of the eleventh MOS tube and the drain electrode of the twelfth MOS tube is an output end of the second node isolation module, a source electrode of the twelfth MOS tube is grounded, a grid electrode of the eleventh MOS tube, a substrate of the eleventh MOS tube, a grid electrode of the twelfth MOS tube and a substrate of the twelfth MOS tube are all grounded, the second capacitance value adjusting module comprises a ninth MOS tube and a tenth MOS tube, and the ninth MOS tube and the tenth MOS tube are both N-type MOS tubes, the grid electrode of the ninth MOS tube is connected with the grid electrode of the tenth MOS tube, the connecting end of the ninth MOS tube is the output end of the second capacitance value adjusting module, the output end of the second capacitance value adjusting module is connected with the output end of the second node isolating module, the source electrode of the ninth MOS tube, the drain electrode of the ninth MOS tube and the substrate of the ninth MOS tube are connected, and the connecting end of the ninth MOS tube is the first input end of the second capacitance value adjusting module; the first input end of the second capacitance value adjusting module is the first input end of the second nor circuit, the source electrode of the tenth MOS transistor, the drain electrode of the tenth MOS transistor and the substrate of the tenth MOS transistor are connected, and the connection end of the tenth MOS transistor is the second input end of the second capacitance value adjusting module, the second input end of the second capacitance value adjusting module is the second input end of the second nor circuit, the channel width adjusting range of the ninth MOS transistor is 300-450 nm, the channel length adjusting range of the ninth MOS transistor is 400-550 nm, the channel width adjusting range of the tenth MOS transistor is 300-450 nm, and the channel length adjusting range of the tenth MOS transistor is 400-550 nm; the second sampling module comprises a seventh MOS tube and an eighth MOS tube, the seventh MOS tube is a P-type MOS tube, the eighth MOS tube is an N-type MOS tube, the source electrode of the seventh MOS tube is connected with a power supply, the substrate of the seventh MOS tube is connected with a power supply, the grid electrode of the seventh MOS tube is connected with the grid electrode of the eighth MOS tube, the connecting end of the seventh MOS tube is the input end of the second sampling module, the input end of the second sampling module is connected with the output end of the second node isolation module, the drain electrode of the seventh MOS tube is connected with the drain electrode of the eighth MOS tube, the connecting end of the seventh MOS tube is the output end of the second sampling module, the output end of the second sampling module is the output end of the second NOR gate circuit, the substrate of the eighth MOS tube is grounded, the source electrode of the eighth MOS tube is grounded, the channel width adjusting range of the seventh MOS tube is 50-60 nm, the channel length adjusting range of the seventh MOS tube is 80-120 nm, the channel width adjusting range of the eighth MOS tube is 50-60 nm, and the channel length adjusting range of the eighth MOS tube is 150-200 nm. The second input end of the first NOR gate circuit is the first input end of the SR latch circuit, the first input end of the second NOR gate circuit is the second input end of the SR latch circuit, the second input end of the second NOR gate circuit is connected with the output end of the first NOR gate circuit, the connecting end of the second NOR gate circuit is the first output end of the SR latch circuit, the output end of the second NOR gate circuit is connected with the first input end of the first NOR gate circuit, and the connecting end of the second NOR gate circuit is the second output end of the SR latch circuit.