CN111313872B - High-resolution low-power-consumption dynamic latching comparator - Google Patents
High-resolution low-power-consumption dynamic latching comparator Download PDFInfo
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Abstract
The invention discloses a high-resolution low-power-consumption dynamic latching comparator, and belongs to the technical field of successive approximation type analog-to-digital converters. The invention utilizes the MOSFET subthreshold characteristic, increases the resolution of the comparator, improves the precision of the comparator, adopts low power supply voltage to supply power, and reduces the overall power consumption of the comparator; compared with the dynamic latch comparator proposed by the patent 201910338368, the dynamic latch comparator proposed by the invention has higher resolution and lower power consumption, and the dynamic latch comparator is used for a successive approximation type analog-to-digital converter with low power supply voltage, while the patent 201910338368 can only work under the standard power supply voltage condition.
Description
Technical Field
The technical field of direct application of "dynamic latch comparators" (pre-latch comparators) is successive approximation type analog-to-digital converters (Successive Approximation Register Analog-to-Digital Converter, abbreviated SAR ADCs).
Background
The functions of the system chip are more and more complex, the integration level is continuously improved, the circuit scale is continuously expanded, and the relationship between the power consumption and the precision of the chip is more and more concerned. In recent years, with the reduction of the size of devices, the feature size of integrated circuits has reached the ultra-deep submicron stage, and meanwhile, the power supply voltage is continuously reduced, so that the problem of power consumption is highlighted along with the effects of noise, short channels and the like. The ever shrinking chip area results in increased power density, which directly results in higher and higher difficulty in chip heat dissipation design and packaging costs. The effects of deep sub-micron short channel and noise temperature increase the difficulty of mixed signal circuit design such as high linearity, high speed, low power consumption. Analog-to-digital converters (ADCs), which are important modules of analog front-ends, require low power consumption to meet the low power consumption requirements of embedded portable systems. In order to meet the demands of no use, the ADC has various circuit structures, focuses on the improvement of different performances, is favorable for improving the speed of the ADC, is favorable for researching the low-power-consumption ADC, is favorable for high-precision ADC, and is favorable for selecting different types of ADC according to the demands by a user.
With the development of digital processing circuits, the advantages of the digital circuits in terms of power consumption and interference resistance are more and more obvious. The internet of things, artificial intelligence and current 5G technology all frequently use digital processing circuit technology, and the requirements for data processing are increasing, which promotes people to have higher requirements for 'bridges' between simulation and numbers. These technologies require ADCs to have not only one advantage, but also a number of high performance features to meet the information age development. Among the constituent modules of the ADC of different types, the comparator is the most important module, and its performance index directly affects the overall performance of the ADC. In general, performance indexes of the comparator mainly include speed, precision, power consumption, offset voltage, working voltage and the like. Different types of ADCs have different comparator requirements. For example, the Successive Approximation (SAR) ADC is mainly characterized by low speed and high accuracy, and the requirements of the comparator are mainly high accuracy and low power consumption; flash (Flash) ADCs are characterized by high speed and high power consumption, and their internal comparators need to meet high speed, low power consumption. In recent years, SAR ADC gets rid of the low-speed characteristic, can meet the application requirements of high speed, middle and high precision, keeps the inherent traditional advantages of low power consumption, area saving, easy integration, simple structure and the like, has obvious advantages compared with the architecture of Flash and other analog-digital converters, becomes a main research hotspot in the field of high-precision and low-power consumption ADC, and simultaneously promotes the research on the structure of a comparator in SAR ADC. Document [ J.R.Rusli, R.M.Sidek, H.A.Majid, W.Z.W.Hassand, M.A.Mustafa and S.Shafie, "Design and Verification of Low Voltage Low Power Dynamic Comparator over PVT Variation,"2018IEEE 5th International Conference on Smart Instrumentation,Measurement and Application (ICSIMA), songakla, thailand,2018, pp.1-5.Doi:10.1109/ICSIMA.2018.8688785] proposes a low power consumption dynamic latching comparator whose main structure is divided into two parts: the first-stage prevention large structure and the second-stage latch structure effectively reduce the energy consumption in the working process by using low power supply voltage, but the comparator has the defects that: the use of a low supply voltage results in a comparator with lower resolution and speed, a minimum input voltage difference of 0.8mV that can be resolved, a clock frequency that can operate normally is lower, typically 2MHz, and the resolution of the whole comparator is not improved by adding a compensation circuit. In terms of High precision comparison, document [ Y.Wang, M.Yao, B.Guo, Z.Wu, W.Fan and J.J.Liou, "A Low-Power High-Speed Dynamic Comparator With a Transconductance-Enhanced Latching Stage," in IEEE Access, vol.7, pp.93396-93403,2019.doi:10.1109/ACCESS.2019.2927514] uses a combination of two-stage amplifying circuit and three-stage latching structure to achieve High precision, but its supply voltage is kept at a higher level, the increase of circuit devices and higher supply voltage make the Power consumption of the whole comparator higher, and now most of the requirements on the Power consumption of the comparator circuit are higher, and the chip supply voltage is required to be lower. Therefore, there is a need to design a dynamic latching comparator for application to high precision low power SAR ADCs.
The technical solution of patent 201910338368 also has the problem of insufficient resolution and insufficient power consumption.
Disclosure of Invention
The invention provides a high-precision low-power consumption dynamic latching comparator based on the improvement of patent 201910338368, which further improves the resolution and reduces the power consumption on the basis of patent 201910338368.
The invention is characterized in that the resolution of the comparator is increased by utilizing the sub-threshold characteristic of the MOSFET, the precision of the comparator is improved, the low power supply voltage is adopted for supplying power, and the overall power consumption of the comparator is reduced;
the technical scheme of the invention is a dynamic latch comparator with high resolution and low power consumption, which comprises: a pre-amplification structure and a latch output structure;
the pre-amplification structure comprises: a differential input structure and an inverter structure, wherein:
a differential input structure comprising: six NMOS tubes: the first NMOS tube (M1 a), the second NMOS tube (M1 b), the third NMOS tube (M1 c), the fourth NMOS tube (M1 d), the fifth NMOS tube (M1 e) and the sixth NMOS tube (M1 f); two PMOS tubes: the first PMOS tube (M2 a), the second PMOS tube (M2 b), the capacitor Cc, the first parasitic capacitor and the second parasitic capacitor; wherein:
the source electrode of the first NMOS tube (M1 a) is grounded, the drain electrode of the first NMOS tube (M1 a) is connected with the source electrode of the second NMOS tube (M1 b), and the source electrode of the first NMOS tube (M1 a) and the second NMOS tube (M1 b) are connected with a capacitor C in a common joint way C One end is connected with a capacitor C C The other end of the first electrode is grounded; the grid electrode of the third NMOS tube (M1 c) is used as an input end to be connected with a first full differential input signal (VINP), the source electrode of the third NMOS tube (M1 c) is connected with the drain electrode of the second NMOS tube (M1 b), the grid electrode and the drain electrode of the fifth NMOS tube (M1 e) are both input with VDD signals, the grid electrode of the first PMOS tube (M2 a) is connected with a clock signal (CLKP), the source electrode of the first PMOS tube (M2 a) is input with VDD signals, the drain electrode of the third NMOS tube (M1 c), the source electrode of the fifth NMOS tube (M1 e) and the drain electrode of the first PMOS tube (M2 a) are connected with one end of a first parasitic capacitor and are used as a first output end P of a differential input structure P The other end of the first parasitic capacitor is grounded; the grid electrode of the first NMOS tube (M1 a) is connected with a clock signal (CLKN), and the grid electrode of the second NMOS tube (M1 b) is connected with the clock signal (CLKP);
the source of the fourth NMOS tube (M1 d) is connected with the drain of the second NMOS tube (M1 b), the grid input of the fourth NMOS tube (M1 d) is connected with the second fully differential input signal (VINN), the grid and drain of the sixth NMOS tube (M1 f) are both input with VDD signals, the grid of the second PMOS tube (M2 b) is connected with the clock signal (CLKP), the source of the second PMOS tube (M2 b) is input with VDD signals, the drain of the fourth NMOS tube (M1 d), the source of the sixth NMOS tube (M1 f) and the drain of the second PMOS tube (M2 b) are both connected with the first end of the second parasitic capacitor and are used as the second output end P of the differential input structure N The other end of the second parasitic capacitor is grounded;
the inverter structure includes: two PMOS tubes: a third PMOS tube (M3 a) and a fourth PMOS tube (M3 b), two NMOS tubes: a seventh NMOS tube (M4 a) and an eighth NMOS tube (M4 b); wherein:
the grid electrode of the seventh NMOS tube (M4 a) is connected with the grid electrode of the third PMOS tube (M3 a) and is connected with the first output end P of the differential input structure P The source stage of the third PMOS tube (M3 a) inputs a VDD signal, the drain stage of the seventh NMOS tube (M4 a) is connected with the drain stage of the third PMOS tube (M3 a) and is used as a first output end LN of the inverter structure, and the source stage of the seventh NMOS tube (M4 a) is grounded;
the grid electrode of the eighth NMOS tube (M4 b) is connected with the grid electrode of the fourth PMOS tube (M3 b) and is connected with the second output end P of the differential input structure N The source stage of the fourth PMOS tube (M3 b) inputs a VDD signal, the drain stage of the eighth NMOS tube (M4 b) is connected with the drain stage of the fourth PMOS tube (M3 b) and is used as a second output end LP of the inverter structure, and the source stage of the eighth NMOS tube (M4 b) is grounded;
the first output end LN of the inverter is the first output end LN of the pre-amplifying structure, and the second output end LP of the inverter is the second output end LP of the pre-amplifying structure;
the latch output structure includes: four PMOS tubes: a fifth PMOS tube (M6 a), a sixth PMOS tube (M6 b), a seventh PMOS tube (M6 c) and an eighth PMOS tube (M6 d); three NMOS tubes: ninth NMOS pipe (M5 a), tenth NMOS pipe (M5 b), eleventh NMOS pipe (M5 c), third parasitic capacitance, fourth parasitic capacitance, wherein:
the grid electrode of the fifth PMOS tube (M6 a) is connected with a first output end LN of the pre-amplifying structure, the source electrode of the fifth PMOS tube (M6 a) and the source electrode of the sixth PMOS tube (M6 b) are connected with an input VDD signal, the grid electrode of the sixth PMOS tube (M6 b) is connected with the grid electrode of the tenth NMOS tube (M5 b), the grid electrode of the ninth NMOS tube (M5 a) is connected with a clock signal (CLKP), and the drain electrode of the ninth NMOS tube (M5 a) is connected with the source electrode of the tenth NMOS tube (M5 b); the drain of the fifth PMOS tube (M6 a), the drain of the sixth PMOS tube (M6 b), the drain of the tenth NMOS tube (M5 b), the grid of the seventh PMOS tube (M6 c) and the grid of the eleventh NMOS tube (M5 c) are commonly connected with one end of the third parasitic capacitor and serve as the output end OUTP of the comparator, and the source of the ninth NMOS tube (M5 a) and the other end of the third parasitic capacitor are grounded;
the grid electrode of the eighth PMOS tube (M6 d) is connected with the second output end LP of the pre-amplifying structure, the source electrode of the eighth PMOS tube (M6 d) and the source electrode of the seventh PMOS tube (M6 c) are connected with an input VDD signal, the drain electrode of the eighth PMOS tube (M6 d), the drain electrode of the seventh PMOS tube (M6 c), the drain electrode of the eleventh NMOS tube (M5 c), the grid electrode of the sixth PMOS tube (M6 b) and the grid electrode of the tenth NMOS tube (M5 b) are commonly connected with one end of a fourth parasitic capacitor and serve as an output end OUTN of the comparator, and the other end of the fourth parasitic capacitor is grounded; the source electrode of the eleventh NMOS tube (M5 c) is connected with the drain electrode of the ninth NMOS tube (M5 a).
Compared with the dynamic latch comparator proposed by the patent 201910338368, the dynamic latch comparator has the advantages that the resolution is higher, the power consumption is lower, the dynamic latch comparator is used for a successive approximation type analog-to-digital converter with low power supply voltage, and the patent 201910338368 can only work under the standard power supply voltage condition.
Drawings
Fig. 1 is a basic structure of a successive approximation analog-to-digital converter.
Fig. 2 is a dynamic latching comparator proposed by patent 201910338368.
FIG. 3 is a high precision low power consumption dynamic latching comparator according to the present invention.
Fig. 4 is a graph showing the relationship between power consumption and input voltage difference proposed by patent 201910338368.
FIG. 5 is a graph of power consumption versus input voltage difference for a high precision low power dynamic latching comparator according to the present invention.
Detailed Description
The following describes the invention in detail with reference to the drawings:
fig. 2 is a fast response dynamic latching comparator as proposed in patent 201910338368. The dynamic latch comparator amplifies the input signal through a pre-amplifying structure and outputs signals XP and XN. The two input ends of the latch structure are connected with the signal XP and the signal XN, and the judgment result is output according to the voltage difference of the two signals. The voltage of output signals XP and XN of the pre-amplifying structure during reset is reduced, the response time of the whole comparator is reduced, and the power consumption of the pre-amplifying structure is reduced by adding a capacitor at the tail current of the pre-amplifying structure.
Fig. 3 is a high-precision low-power-consumption dynamic latching comparator, which is suitable for a fully-differential successive approximation analog-to-digital converter requiring high-precision low supply voltage. The dynamic latching comparator is composed of a pre-amplifying structure and a latching structure, wherein the pre-amplifying structure is divided into two parts: a differential input structure and an inverter structure. In the reset phase, the clock signal CLKP is low, CLKN is high, and the output terminal P of the differential input structure P And P N Setting high level, after the high level passes through the inverter structure, the output end L of the inverter N And L P Outputs low level, and the latch structure is connected with the output end L of the phase inverter N And L P Low level control, the latch structure outputs (comparator outputs) OUTP and OUTN are high level. In the comparison phase, the clock signal CLKP is high and CLKN is low. The differential input structure is based on a common source amplifying circuit, NMOS tubes at two ends of differential input have gate-source voltage controlled by input signals VINP and VINN and capacitance C at tail current C Is controlled by the control system. Ensuring that the leakage current of the output ends of two NMOS transistors and the gate source voltage thereof are in an exponential relationship in the comparison stage, even if the tiny gate source voltage changes, the leakage current can also cause larger change, and the change of the leakage current causes the output end P of the differential input structure P And P N The voltage of (a) decreases at different magnitudes, i.e. increases the voltage difference between the two. P (P) P And P N After the voltage of the (2) is input into the inverter, the output terminal voltage L of the inverter N And L P Gradually changes from low level to high level, and the voltage difference between the two levels is continuously increased. The pre-amplification structure of the design improves the overall accuracy of the comparator according to the characteristics of the MOSFET in the subthreshold region. The latch structure is based on the input terminal L N And L P And outputting the decision result. Assuming VINP is greater than VINN, the comparator output OUTP is low and OUTN is high. Conversely, if VINP is less than VINN, the comparator output OUTP is high and OUTN is low.
Fig. 4 is a simulation result of power consumption of the dynamic latch comparator proposed in patent 201910338368 in a certain voltage difference range of the test input signal by adopting a TSMC 180nm process. FIG. 5 is a simulation result of the high-precision low-power-consumption comparator of the design, which adopts a TSMC 65nm process, wherein the simulation process angle is TT, the simulation temperature is 27 degrees, the power supply voltage is 0.65V, the common mode voltage of the input signals VINP and VINN is 0.445V, the frequencies of the clock signals CLKP and CLKN are 200MHz, and the voltage difference range of the input signals is 7.5 mV-50 mV.
The comparator performance is compared as shown in table 1 below.
TABLE 1 comparator performance comparison
| Patent 201910338368 | The invention is that | |
| Art (nm) | 180 | 65 |
| Single end/differential | Differential motion | Differential motion |
| Response time (ns) | 0.293 | 1.304 |
| Highest operating speed (MHz) | 300 | 200 |
| Power supply voltage of power supply(V) | 1.8 | 0.65 |
| Resolution (V) | 900 | 4 |
Claims (1)
1. A high resolution low power dynamic latching comparator, the dynamic latching comparator comprising: a pre-amplification structure and a latch output structure;
the pre-amplification structure comprises: a differential input structure and an inverter structure, wherein:
a differential input structure comprising: six NMOS tubes: the first NMOS tube (M1 a), the second NMOS tube (M1 b), the third NMOS tube (M1 c), the fourth NMOS tube (M1 d), the fifth NMOS tube (M1 e) and the sixth NMOS tube (M1 f); two PMOS tubes: the first PMOS tube (M2 a), the second PMOS tube (M2 b), the capacitor Cc, the first parasitic capacitor and the second parasitic capacitor; wherein:
the source electrode of the first NMOS tube (M1 a) is grounded, the drain electrode of the first NMOS tube (M1 a) is connected with the source electrode of the second NMOS tube (M1 b), and the source electrode of the first NMOS tube (M1 a) and the second NMOS tube (M1 b) are connected with a capacitor C in a common joint way C One end is connected with a capacitor C C The other end of the first electrode is grounded; the grid electrode of the third NMOS tube (M1 c) is used as an input end to be connected with a first full differential input signal (VINP), the source electrode of the third NMOS tube (M1 c) is connected with the drain electrode of the second NMOS tube (M1 b), the grid electrode and the drain electrode of the fifth NMOS tube (M1 e) are both input with VDD signals, the grid electrode of the first PMOS tube (M2 a) is connected with a clock signal (CLKP), the source electrode of the first PMOS tube (M2 a) is input with VDD signals, the drain electrode of the third NMOS tube (M1 c), the source electrode of the fifth NMOS tube (M1 e) and the drain electrode of the first PMOS tube (M2 a) are connected with one end of a first parasitic capacitor and are used as a first output end P of a differential input structure P The other end of the first parasitic capacitor is grounded; the grid electrode of the first NMOS tube (M1 a) is connected with a clock signal (CLKN), and the grid electrode of the second NMOS tube (M1 b) is connected with the clock signal (CLKP);
the source of the fourth NMOS tube (M1 d) is connected with the second NMOS tube(M1 b) drain, gate input of the fourth NMOS tube (M1 d) connected with the second fully differential input signal (VINN), gate and drain of the sixth NMOS tube (M1 f) both input VDD signal, gate of the second PMOS tube (M2 b) connected with clock signal (CLKP), source of the second PMOS tube (M2 b) inputting VDD signal, drain of the fourth NMOS tube (M1 d), source of the sixth NMOS tube (M1 f) and drain of the second PMOS tube (M2 b) all connected with the first end of the second parasitic capacitor and serving as the second output end P of the differential input structure N The other end of the second parasitic capacitor is grounded;
the inverter structure includes: two PMOS tubes: a third PMOS tube (M3 a) and a fourth PMOS tube (M3 b), two NMOS tubes: a seventh NMOS tube (M4 a) and an eighth NMOS tube (M4 b); wherein:
the grid electrode of the seventh NMOS tube (M4 a) is connected with the grid electrode of the third PMOS tube (M3 a) and is connected with the first output end P of the differential input structure P The source stage of the third PMOS tube (M3 a) inputs a VDD signal, the drain stage of the seventh NMOS tube (M4 a) is connected with the drain stage of the third PMOS tube (M3 a) and is used as a first output end LN of the inverter structure, and the source stage of the seventh NMOS tube (M4 a) is grounded;
the grid electrode of the eighth NMOS tube (M4 b) is connected with the grid electrode of the fourth PMOS tube (M3 b) and is connected with the second output end P of the differential input structure N The source stage of the fourth PMOS tube (M3 b) inputs a VDD signal, the drain stage of the eighth NMOS tube (M4 b) is connected with the drain stage of the fourth PMOS tube (M3 b) and is used as a second output end LP of the inverter structure, and the source stage of the eighth NMOS tube (M4 b) is grounded;
the first output end LN of the inverter is the first output end LN of the pre-amplifying structure, and the second output end LP of the inverter is the second output end LP of the pre-amplifying structure;
the latch output structure includes: four PMOS tubes: a fifth PMOS tube (M6 a), a sixth PMOS tube (M6 b), a seventh PMOS tube (M6 c) and an eighth PMOS tube (M6 d); three NMOS tubes: ninth NMOS pipe (M5 a), tenth NMOS pipe (M5 b), eleventh NMOS pipe (M5 c), third parasitic capacitance, fourth parasitic capacitance, wherein:
the grid electrode of the fifth PMOS tube (M6 a) is connected with a first output end LN of the pre-amplifying structure, the source electrode of the fifth PMOS tube (M6 a) and the source electrode of the sixth PMOS tube (M6 b) are connected with an input VDD signal, the grid electrode of the sixth PMOS tube (M6 b) is connected with the grid electrode of the tenth NMOS tube (M5 b), the grid electrode of the ninth NMOS tube (M5 a) is connected with a clock signal (CLKP), and the drain electrode of the ninth NMOS tube (M5 a) is connected with the source electrode of the tenth NMOS tube (M5 b); the drain of the fifth PMOS tube (M6 a), the drain of the sixth PMOS tube (M6 b), the drain of the tenth NMOS tube (M5 b), the grid of the seventh PMOS tube (M6 c) and the grid of the eleventh NMOS tube (M5 c) are commonly connected with one end of the third parasitic capacitor and serve as the output end OUTP of the comparator, and the source of the ninth NMOS tube (M5 a) and the other end of the third parasitic capacitor are grounded;
the grid electrode of the eighth PMOS tube (M6 d) is connected with the second output end LP of the pre-amplifying structure, the source electrode of the eighth PMOS tube (M6 d) and the source electrode of the seventh PMOS tube (M6 c) are connected with an input VDD signal, the drain electrode of the eighth PMOS tube (M6 d), the drain electrode of the seventh PMOS tube (M6 c), the drain electrode of the eleventh NMOS tube (M5 c), the grid electrode of the sixth PMOS tube (M6 b) and the grid electrode of the tenth NMOS tube (M5 b) are commonly connected with one end of a fourth parasitic capacitor and serve as an output end OUTN of the comparator, and the other end of the fourth parasitic capacitor is grounded; the source electrode of the eleventh NMOS tube (M5 c) is connected with the drain electrode of the ninth NMOS tube (M5 a).
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| CN114124047A (en) * | 2022-01-26 | 2022-03-01 | 江苏思远集成电路与智能技术研究院有限公司 | Dynamic comparator |
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| EP3331162A1 (en) * | 2016-12-01 | 2018-06-06 | IMEC vzw | Input circuit for a dynamic comparator |
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