CN111312590B - Method for improving high uniformity of fin field effect transistor gate - Google Patents
Method for improving high uniformity of fin field effect transistor gate Download PDFInfo
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- CN111312590B CN111312590B CN202010105925.8A CN202010105925A CN111312590B CN 111312590 B CN111312590 B CN 111312590B CN 202010105925 A CN202010105925 A CN 202010105925A CN 111312590 B CN111312590 B CN 111312590B
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- 238000000034 method Methods 0.000 title claims abstract description 51
- 230000005669 field effect Effects 0.000 title claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 58
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 56
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 56
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 48
- 229920005591 polysilicon Polymers 0.000 claims abstract description 47
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 22
- 238000000151 deposition Methods 0.000 claims abstract description 11
- 238000005498 polishing Methods 0.000 claims description 43
- 239000000126 substance Substances 0.000 claims description 32
- 238000001312 dry etching Methods 0.000 claims description 16
- 238000001039 wet etching Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 6
- 238000000231 atomic layer deposition Methods 0.000 claims description 4
- 230000000694 effects Effects 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 76
- 238000010586 diagram Methods 0.000 description 15
- 230000008021 deposition Effects 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000003667 anti-reflective effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- General Physics & Mathematics (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a method for improving the high uniformity of a fin field effect transistor gate, which fills a dielectric layer covering a silicon nitride etching stop layer and a polysilicon virtual inter-gate groove; removing the dielectric layer and the silicon nitride etching stop layer by a non-selective etching method; removing the dielectric layer in the grooves between the polysilicon virtual gates by high-selectivity etching; depositing a chemical vapor deposition oxide; grinding to expose the hard mask silicon nitride layer; removing part of the chemical vapor deposition oxide in the groove by high-selectivity etching; filling the high-density plasma oxide and grinding until the polysilicon dummy gate is exposed. The method for improving the gate uniformity of the fin field effect transistor greatly improves the local planarization effect, so that the height difference of the polysilicon virtual gates at different line widths is smaller, and the gate height difference is smaller. Meanwhile, the thickness proportion difference between the high-density plasma oxide and the chemical vapor deposition oxide is reduced, so that the contact hole etching process window is increased.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a method for improving high uniformity of a fin field effect transistor gate.
Background
With the continued shrinking of large scale integrated circuit geometries, particularly after entering the FINFET process, localized non-uniformity in chemical mechanical polishing has become an increasingly serious and yet urgent problem to be solved.
In a typical process flow of FINFET RMG (replaced metal gate), the formation of the gate structure mainly includes thin film deposition of a 0 th layer dielectric layer (Inter layer dielectric-level 0, ILD0 for short), 2-3 times dielectric chemical mechanical planarization (to leak out the polysilicon dummy gate), polysilicon dummy gate etching, work function material deposition, metal (tungsten) deposition, and metal chemical mechanical planarization. As part of the FINFET RMG process flow, planarization effect is critical to the formation of high-K metal gates.
A Hard Mask Oxide (HM OX) acts as a barrier to amorphous polysilicon etching, and is etched in different amounts at different line widths, so that the thickness of the Hard Mask Oxide reaching ILD0 is different. In the first chemical mechanical polishing (CMP 1), since the polishing rate of the flowable chemical vapor deposited oxide (FCVD OX) is much higher than that of the contact hole etch stop layer silicon nitride (contact etch stop layer SiN, CESL SiN for short), the height of the surface at each position after polishing is strongly related to the thickness of the HM OX. After the non-selective dry etching (FCVD OX is close to the etch rate of silicon oxide) process, the height of the surface at each location is continued from the previous step.
After the second cmp, the polysilicon dummy gate height is significantly different at different locations (line widths) and the ratio of the filled high density plasma oxide (HDP OX) to FCVD OX is significantly different. The former can cause obvious difference in performance of devices at different positions, is difficult to control and is difficult to realize mass production. The latter may cause instability of the contact hole etching process (CESL SiN acts as an etch stop for this process).
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method for improving the gate uniformity of a fin field effect transistor, which is used for solving the problems of the prior art that after the second chemical mechanical polishing process of the fin field effect transistor gate, the difference of the polysilicon dummy gate heights is large at different line widths, the performance of devices at different positions is obviously different, the device is difficult to control, the large-scale mass production is difficult, and the ratio difference of the high-density plasma oxide and the chemical vapor deposition oxide filled in the process is obvious, so that the instability of the contact hole etching process is caused.
To achieve the above and other related objects, the present invention provides a method for improving gate uniformity of a finfet, comprising at least the following steps:
providing a substrate, wherein a plurality of polysilicon virtual gates with different line widths are arranged on the substrate at intervals, and a hard mask silicon nitride layer, a hard mask oxide layer and a silicon nitride etching stop layer are sequentially arranged on the upper surface of the polysilicon virtual gate from bottom to top;
filling a dielectric layer covering the top of the silicon nitride etching stop layer and the grooves between the polysilicon virtual gates;
step three, etching and removing the dielectric layer above the silicon nitride etching stop layer and the silicon nitride etching stop layer by adopting a non-selective etching method;
removing the dielectric layer in the grooves between the polysilicon virtual gates by adopting high-selectivity dry etching;
depositing chemical vapor deposition oxide covering the grooves between the top of the hard mask oxide layer and the polysilicon virtual gate;
step six, performing first chemical mechanical polishing to expose the hard mask silicon nitride layer;
step seven, removing a part of the chemical vapor deposition oxide in the grooves between the polysilicon virtual gates by adopting high-selectivity wet etching;
step eight, filling high-density plasma oxide covering the grooves between the top of the hard mask silicon nitride layer and the polysilicon virtual gate;
and step nine, performing second chemical mechanical polishing until the top of the polysilicon virtual gate is exposed.
Preferably, the silicon nitride etching stop layer in the first step is formed by adopting an atomic layer deposition mode.
Preferably, the thickness of the silicon nitride etching stop layer in the first step is 40-100 angstroms.
Preferably, the dielectric layer in the second step is one of an organic dielectric layer or a bottom anti-reflection layer.
Preferably, the non-selective etching in the third step is non-selective dry etching.
Preferably, the non-selective dry etching adopted in the third step is such that the etching rate ratio of the silicon nitride etching stop layer to the dielectric layer is 1:1.
Preferably, in the fourth step, the high-selectivity dry etching is adopted, so that the etching rate ratio of the dielectric layer to the hard mask oxide layer is not less than 10:1.
Preferably, the thickness of the chemical vapor deposition oxide deposited in the fifth step is 3000-6000 angstroms.
Preferably, the polishing rate ratio of the chemical vapor deposition oxide, the hard mask oxide layer and the hard mask silicon nitride layer is greater than 8:1.
Preferably, in the seventh step, the high-selectivity wet etching is adopted, so that the etching rate ratio of the chemical vapor deposition oxide to the hard mask silicon nitride layer is greater than 5:1.
Preferably, the thickness of the chemical vapor deposited oxide in the grooves between the polysilicon dummy gates is removed in the seventh step is greater than 500 angstroms.
Preferably, the thickness of the high-density plasma oxide filled in the step eight is 1500-4000 angstroms.
Preferably, the second chemical mechanical polishing of step nine includes two steps: the first step adopts high-selectivity chemical mechanical polishing to enable the polishing rate ratio of the high-density plasma oxide to the hard mask silicon nitride layer to be larger than 8:1, wherein the hard mask silicon nitride layer is a polishing stop layer; and in the second step, non-selective chemical mechanical polishing is adopted, so that the polishing rate ratio of the high-density plasma oxide, the hard mask silicon nitride layer and the polysilicon virtual gate is 1:1:1.
As described above, the method for improving the high uniformity of the fin field effect transistor gate of the present invention has the following advantages: the method for improving the gate uniformity of the fin field effect transistor greatly improves the local planarization effect, so that the difference of the heights of the polysilicon virtual gates at different positions (line widths) is smaller, and the final gate height difference is smaller. In addition, the thickness ratio difference of the filled high-density plasma oxide and the chemical vapor deposition oxide is made smaller, so that the contact hole etching process window is increased.
Drawings
FIG. 1 is a schematic diagram of a method for forming a silicon nitride etch stop layer on a hard mask oxide layer in accordance with the present invention;
FIG. 2 is a schematic diagram of a structure of the present invention after filling a dielectric layer covering the top of the silicon nitride etch stop layer and the recess between the polysilicon dummy gates;
FIG. 3 is a schematic diagram showing the structure of the present invention after non-selective etching and high-selective etching;
FIG. 4 is a schematic diagram of a structure of the present invention after depositing a chemical vapor deposited oxide covering the recess between the top of the hard mask oxide layer and the dummy gate of polysilicon;
FIG. 5 is a schematic view showing a structure formed by the first chemical mechanical polishing according to the present invention;
FIG. 6 is a schematic diagram showing a structure formed after the high-selectivity wet etching in the present invention;
FIG. 7 is a schematic diagram of a structure of the present invention after filling a high density plasma oxide covering the recess between the top of the hard mask silicon nitride layer and the dummy gate of polysilicon;
FIG. 8 is a schematic diagram showing a structure formed by the second chemical mechanical polishing according to the present invention;
fig. 9 is a flow chart of a method for improving gate uniformity of a finfet in accordance with the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1 to 9. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
The invention provides a method for improving the gate uniformity of a fin field effect transistor, as shown in fig. 9, fig. 9 is a flow chart of the method for improving the gate uniformity of the fin field effect transistor. The method at least comprises the following steps:
providing a substrate, wherein a plurality of polysilicon virtual gates 01 with different line widths are arranged on the substrate at intervals, and a hard mask silicon nitride layer (HMSiN) 02, a hard mask oxide layer (HMOX) 03 and a silicon nitride etching stop layer (CESL SiN) 04 are sequentially arranged on the upper surface of the polysilicon virtual gate 01 from bottom to top; FIG. 1 is a schematic diagram of a method for forming a silicon nitride etch stop layer on a hard mask oxide layer according to the present invention; this step is followed by a CESL SiN deposition followed by filling with a certain amount of an organic dielectric layer (organic dielectric layer, ODL for short) or bottom anti-reflective coating (BARC for short) reflection coating. In a further aspect of the present invention, the silicon nitride etch stop layer (CESL SiN) 04 in the first step is formed by atomic layer deposition. Still further, the thickness of the silicon nitride etch stop layer (CESL SiN) 04 in the first step is 40 to 100 angstroms. In this step in this example 40-100 angstrom of CESL SiN is grown by atomic layer deposition.
Filling a dielectric layer 05 covering the top of the silicon nitride etching stop layer (CESL SiN) 04 and the grooves between the polysilicon virtual gates 01; as shown in fig. 2, fig. 2 is a schematic diagram of a structure of the present invention after filling a dielectric layer 05 covering the top of a silicon nitride etch stop layer (CESL SiN) 04 and the grooves between polysilicon dummy gates 01; in the present invention, the dielectric layer 05 in the second step is one of an Organic Dielectric Layer (ODL) or a bottom anti-reflective layer (BARC). An appropriate amount of Organic Dielectric Layer (ODL) or bottom anti-reflective layer (BARC) is filled to nearly fill the entire recess.
Step three, etching and removing the dielectric layer 05 above the silicon nitride etching stop layer (CESL SiN) 04 and the silicon nitride etching stop layer (CESL SiN) 04 by adopting a non-selective etching method; as shown in fig. 3, fig. 3 is a schematic diagram of a structure formed by non-selective etching and high-selective etching in the present invention; the invention further provides that the non-selective etching in the third step is non-selective dry etching. Still further, the non-selective dry etching adopted in the third step makes the etching rate ratio of the silicon nitride etching stop layer (CESL SiN) 04 and the dielectric layer 05 be 1:1. This step performs a non-selective etch to bring the etch rates of ODL and CESL SiN to approximately 1:1, eating the ODL and CESL SiN over HM OX.
Removing the dielectric layer 05 in the grooves between the polysilicon virtual gates 01 by adopting high-selectivity dry etching; as shown in fig. 3, fig. 3 is a schematic diagram of a structure formed by non-selective etching and high-selective etching in the present invention; in the fourth step, the high-selectivity dry etching is adopted, so that the etching rate ratio of the dielectric layer 05 to the hard mask oxide layer (HMOX) 03 is not less than 10:1. And step three and step four are respectively carried out in advance without a selective dry etching process, so that the etching rates of the ODL (or BARC) and the CESL SiN are close to 1:1, and the ODL (or BARC) and the CESL SiN above the HMOX are removed. And then performing a high-selectivity dry etching process to ensure that the etching rates of the ODL (or the BARC) and the HMOX are more than or equal to 10:1, and completely removing the ODL (or the BARC) in the grooves (between the virtual gates). The step is to perform a high-selectivity dry etching process to ensure that the etching rate of the ODL and the HMOX is more than or equal to 10:1, and the ODL in the grooves (between the virtual gates) is completely removed.
Depositing a chemical vapor deposition oxide (FCVD OX) 06 covering a groove between the top of the hard mask oxide layer (HMOX) 03 and the polysilicon virtual gate 01; as shown in fig. 4, fig. 4 is a schematic diagram of the structure of the present invention after depositing a chemical vapor deposited oxide (FCVD OX) 06 covering the trench between the top of the hard mask oxide (HM OX) 03 and the polysilicon dummy gate 01; the invention further provides that the thickness of the chemical vapor deposition oxide (FCVD OX) 06 deposited in the step five is 3000-6000 angstroms.
Step six, performing first chemical mechanical polishing to expose the hard mask silicon nitride layer (HMSiN) 02; FIG. 5 is a schematic view of a structure of the first chemical mechanical polishing method according to the present invention; in a further aspect of the present invention, the polishing rate ratio of the chemical vapor deposition oxide (FCVD OX) 06, the hard mask oxide layer (HM OX) 03, and the hard mask silicon nitride layer (HM SiN) 02 is greater than 8:1. After FCVD OX deposition, the first cmp planarization process is performed, with a Hard mask silicon nitride layer (Hard mask SiN, abbreviated as HM SiN) as the polishing endpoint. Since the polishing rate of HM OX is very fast and the polishing rate of HM SiN is very low, even though the thickness of HM OX varies widely at different locations (line widths), the difference in surface height after polishing is small.
Step seven, removing a part of the chemical vapor deposition oxide (FCVD OX) 06 in the grooves between the polysilicon virtual gates 01 by adopting high-selectivity wet etching; as shown in fig. 6, fig. 6 is a schematic structural diagram of the present invention after high-selectivity wet etching; the present invention further provides that in step seven, the high-selectivity wet etching is adopted, so that the etching rate ratio of the chemical vapor deposition oxide (FCVD OX) 06 to the hard mask silicon nitride layer (HM SiN) 02 is greater than 5:1. Still further, in step seven, the thickness of the chemical vapor deposited oxide (FCVD OX) 06 in the recesses between the polysilicon dummy gates 01 is removed to be greater than 500 angstroms. High selectivity wet etch and HDP OX deposition, the thickness ratio of the filled high density plasma oxide (HDP OX) to FCVD OX varies less due to the better planarization effect of the previous step.
Step eight, filling a high density plasma oxide (HDP) 07 covering a groove between the top of the hard mask silicon nitride layer (HMSiN) 02 and the polysilicon dummy gate 01; as shown in fig. 7, fig. 7 is a schematic diagram showing a structure formed by filling a high density plasma oxide (HDP) 07 covering a recess between the top of a hard mask silicon nitride layer (HM SiN) 02 and a polysilicon dummy gate 01 according to the present invention; the invention further provides that the thickness of the high density plasma oxide (HDP) 07 filled in the step eight is 1500-4000 angstroms.
And step nine, performing second chemical mechanical polishing until the top of the polysilicon dummy gate 01 is exposed. FIG. 8 is a schematic diagram of a structure of the second chemical mechanical polishing method according to the present invention; in a further aspect of the present invention, the second chemical mechanical polishing in step nine includes two steps: the first step adopts high-selectivity chemical mechanical polishing to ensure that the polishing rate ratio of the high-density plasma oxide (HDP) 07 to the hard mask silicon nitride layer (HMSiN) 02 is more than 8:1, wherein the hard mask silicon nitride layer (HMSiN) 02 is a polishing stop layer; in the second step, non-selective chemical mechanical polishing is adopted, so that the polishing rate ratio of the high density plasma oxide (HDP) 07, the hard mask silicon nitride layer (HMSiN) 02 and the polysilicon dummy gate 01 is 1:1:1. The polishing end point of the first chemical mechanical polishing disc is on HMSiN, and the second chemical mechanical polishing disc is selectively polished to enable the polycrystalline silicon virtual grid to leak out.
In summary, the method for improving the gate uniformity of the fin field effect transistor greatly improves the local planarization effect, so that the difference of the polysilicon virtual gate heights at different positions (line widths) is smaller, and the final gate height difference is smaller. In addition, the thickness ratio difference of the filled high-density plasma oxide and the chemical vapor deposition oxide is made smaller, so that the contact hole etching process window is increased. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (13)
1. A method for improving gate uniformity of a fin field effect transistor, the method comprising at least the steps of:
providing a substrate, wherein a plurality of polysilicon virtual gates with different line widths are arranged on the substrate at intervals, and a hard mask silicon nitride layer, a hard mask oxide layer and a silicon nitride etching stop layer are sequentially arranged on the upper surface of the polysilicon virtual gate from bottom to top;
filling a dielectric layer covering the top of the silicon nitride etching stop layer and the grooves between the polysilicon virtual gates;
step three, etching and removing the dielectric layer above the silicon nitride etching stop layer and the silicon nitride etching stop layer by adopting a non-selective etching method;
removing the dielectric layer in the grooves between the polysilicon virtual gates by adopting high-selectivity dry etching;
depositing chemical vapor deposition oxide covering the grooves between the top of the hard mask oxide layer and the polysilicon virtual gate;
step six, performing first chemical mechanical polishing to expose the hard mask silicon nitride layer;
step seven, removing a part of the chemical vapor deposition oxide in the grooves between the polysilicon virtual gates by adopting high-selectivity wet etching;
step eight, filling high-density plasma oxide covering the grooves between the top of the hard mask silicon nitride layer and the polysilicon virtual gate;
and step nine, performing second chemical mechanical polishing until the top of the polysilicon virtual gate is exposed.
2. The method of improving gate uniformity of a fin field effect transistor according to claim 1, wherein: and in the first step, the silicon nitride etching stop layer is formed by adopting an atomic layer deposition mode.
3. The method of improving gate uniformity of a fin field effect transistor according to claim 2, wherein: and in the first step, the thickness of the silicon nitride etching stop layer is 40-100 angstroms.
4. The method of improving gate uniformity of a fin field effect transistor according to claim 1, wherein: and in the second step, the dielectric layer is one of an organic dielectric layer and a bottom anti-reflection layer.
5. The method of improving gate uniformity of a fin field effect transistor according to claim 1, wherein: and step three, the non-selective etching is non-selective dry etching.
6. The method of improving gate uniformity of a finfet in claim 5, wherein: and step three, the non-selective dry etching is adopted, so that the etching rate ratio of the silicon nitride etching stop layer to the dielectric layer is 1:1.
7. The method of improving gate uniformity of a fin field effect transistor according to claim 1, wherein: and step four, adopting the high-selectivity dry etching to enable the etching rate ratio of the dielectric layer to the hard mask oxide layer to be not less than 10:1.
8. The method of improving gate uniformity of a fin field effect transistor according to claim 1, wherein: and step five, the thickness of the chemical vapor deposition oxide deposited in the step 3000-6000 angstroms.
9. The method of improving gate uniformity of a fin field effect transistor according to claim 1, wherein: and step six, performing the first chemical mechanical polishing, wherein the polishing rate ratio of the chemical vapor deposition oxide, the hard mask oxide layer and the hard mask silicon nitride layer is greater than 8:1.
10. The method of improving gate uniformity of a fin field effect transistor according to claim 1, wherein: and step seven, adopting the high-selectivity wet etching to enable the etching rate ratio of the chemical vapor deposition oxide to the hard mask silicon nitride layer to be larger than 5:1.
11. The method of claim 10, wherein the step of improving gate uniformity of the finfet comprises: and step seven, removing the thickness of the chemical vapor deposition oxide in the grooves between the polysilicon virtual gates to be more than 500 angstroms.
12. The method of improving gate uniformity of a fin field effect transistor according to claim 1, wherein: the thickness of the high-density plasma oxide filled in the step eight is 1500-4000 angstroms.
13. The method of improving gate uniformity of a fin field effect transistor according to claim 1, wherein: the second chemical mechanical polishing of step nine includes two steps: the first step adopts high-selectivity chemical mechanical polishing to enable the polishing rate ratio of the high-density plasma oxide to the hard mask silicon nitride layer to be larger than 8:1, wherein the hard mask silicon nitride layer is a polishing stop layer; and in the second step, non-selective chemical mechanical polishing is adopted, so that the polishing rate ratio of the high-density plasma oxide, the hard mask silicon nitride layer and the polysilicon virtual gate is 1:1:1.
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| CN202010105925.8A CN111312590B (en) | 2020-02-20 | 2020-02-20 | Method for improving high uniformity of fin field effect transistor gate |
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| CN202010105925.8A CN111312590B (en) | 2020-02-20 | 2020-02-20 | Method for improving high uniformity of fin field effect transistor gate |
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| CN111312590A CN111312590A (en) | 2020-06-19 |
| CN111312590B true CN111312590B (en) | 2023-08-11 |
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| CN105448691A (en) * | 2014-08-22 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof, and electronic device |
| CN105575899A (en) * | 2014-10-30 | 2016-05-11 | 台湾积体电路制造股份有限公司 | Equal gate height control method for semiconductor device with different pattern densities |
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| CN105575899A (en) * | 2014-10-30 | 2016-05-11 | 台湾积体电路制造股份有限公司 | Equal gate height control method for semiconductor device with different pattern densities |
| CN109037053A (en) * | 2018-07-13 | 2018-12-18 | 上海华力集成电路制造有限公司 | The manufacturing method of grid |
| CN110391184A (en) * | 2019-07-24 | 2019-10-29 | 上海华力集成电路制造有限公司 | The manufacturing method of level 0 interlayer film |
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