CN111312135B - Source driver and operation method thereof - Google Patents
Source driver and operation method thereof Download PDFInfo
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- CN111312135B CN111312135B CN201811516972.0A CN201811516972A CN111312135B CN 111312135 B CN111312135 B CN 111312135B CN 201811516972 A CN201811516972 A CN 201811516972A CN 111312135 B CN111312135 B CN 111312135B
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- 238000000034 method Methods 0.000 title description 7
- 238000011084 recovery Methods 0.000 claims abstract description 45
- 238000001514 detection method Methods 0.000 claims abstract description 21
- 238000011017 operating method Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- 238000012549 training Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 101100028908 Lotus japonicus PCS3 gene Proteins 0.000 description 1
- 101150003196 PCS1 gene Proteins 0.000 description 1
- 101150071172 PCS2 gene Proteins 0.000 description 1
- 101100493726 Phalaenopsis sp. BIBSY212 gene Proteins 0.000 description 1
- 101100030895 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) RPT4 gene Proteins 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
A source driver and an operating method thereof. In the source driver, the clock data recovery circuit is used for receiving an original data signal from an external device and generating a clock signal and a first data signal according to the original data signal. The digital circuit receives the clock signal and the first data signal and generates a cut-off power signal according to the first data signal. The signal detection circuit is used for receiving a control signal from an external device and generating a starting power supply signal according to the control signal. The power control circuit cuts off the power supply signal to power off the clock data recovery circuit, and the power control circuit cuts off the power supply signal to power on the clock data recovery circuit.
Description
Technical Field
The present invention relates to a display apparatus, and more particularly, to a source driver and an operating method thereof.
Background
With the advancement of electronic technology, consumer electronics has become a necessary tool in people's life. To provide a good human-machine interface, it is also a trend to configure high quality display devices on consumer electronics. It would be a matter of those skilled in the art to reduce the power consumption of the display device during non-display time intervals.
Disclosure of Invention
The invention provides a source driver and an operation method thereof, which can effectively reduce the power consumption of the source driver in a non-display time interval.
The source driver of the present invention includes a frequency data recovery (clock data recovery, CDR) circuit, a digital circuit, a signal detection circuit, and a power control circuit. The clock data recovery circuit is used for receiving an original data signal from an external device and generating a clock signal and a first data signal according to the original data signal. The digital circuit is coupled to the clock data recovery circuit to receive the clock signal and the first data signal and generate a cut-off power signal according to the first data signal. The signal detection circuit is used for receiving a control signal from an external device and generating a starting power supply signal according to the control signal. The power control circuit is coupled to the digital circuit to receive the cut-off power signal and coupled to the signal detection circuit to receive the start-up power signal, wherein the power control circuit cuts off the power of the clock data recovery circuit according to the cut-off power signal, and the power control circuit re-electrifies the clock data recovery circuit according to the start-up power signal.
The operation method of the invention comprises the following steps: generating a clock signal and a data signal by a clock data recovery circuit according to the original data signal; generating a power-off signal by the digital circuit according to the first data signal; generating a starting power signal by a signal detection circuit according to the control signal; the power supply control circuit cuts off the power supply signal to power off the clock data recovery circuit; the power control circuit makes the clock data recovery circuit re-electrified according to the starting power signal.
Based on the above, the source driver according to the embodiments of the present invention may be powered off by the power control circuit according to the power-off signal to power off at least one or all of the clock data recovery circuit, the digital circuit and the driving circuit. And, the power control circuit is utilized to make at least one or all of the clock data recovery circuit, the digital circuit and the driving circuit be powered back according to the starting power signal. Therefore, the source driver of the invention can further reduce the power consumption of the whole source driver when operating in the non-display time interval.
In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a schematic circuit diagram of a source driver according to an embodiment of the invention.
FIG. 2 is a schematic diagram illustrating signal timing of the source driver shown in FIG. 1 according to an embodiment of the present invention.
Fig. 3 is a flowchart of an operation method of a source driver according to an embodiment of the present invention.
Detailed Description
The term "coupled" as used throughout this specification (including the claims) may refer to any direct or indirect connection. For example, if a first device couples (or connects) to a second device, that connection may be through a direct connection, or through an indirect connection via other devices and connections. In addition, wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts. The components/elements/steps in different embodiments using the same reference numerals or using the same terminology may be referred to with respect to each other.
Fig. 1 is a circuit block diagram of a source driver 100 according to an embodiment of the invention. The source driver 100 receives the original data signal TX and the control signal CS from the external device 160, and drives the display panel 170 to display an image according to the received original data signal TX and the control signal CS. Specifically, the external device 160 of the present embodiment may include a timing controller (Timing Controller, TCON). In this embodiment, the external device 160 may generate the original data signal TX and the control signal CS to the source driver 100, wherein the original data signal TX includes the display data required to be displayed by the display panel 170, and the control signal CS is used to indicate the valid data period and the invalid data period (e.g. training pattern) in the original data signal TX. Generally, an invalid data period is arranged after a vertical blanking period (vertical blanking) (before a transmission period of valid frame data). Therefore, the control signal CS carries phase (time point) information of "the vertical blanking period has ended".
Referring to fig. 1, the source driver 100 includes a clock data recovery circuit 110, a digital circuit 120, a signal detection circuit 130, a power control circuit 140 and a driving circuit 150. In which a power on/off reset (POFR) circuit is configured in the power control circuit 140. The clock data recovery circuit 110 can be used to analyze the clock signal CLK and the data signal DS1 mounted in the original data signal TX. The data signal DS1 may include pixel data, a vertical blanking start signal VBK, a line latch signal and other control signals, but the embodiment is not limited thereto. In general, the vertical blanking start signal VBK may indicate/define a start phase (start time point) of one vertical blanking period.
The digital circuit 120 of the present embodiment may be, for example, a controller or a data processor, but the present invention is not limited thereto. The digital circuit 120 is coupled to the clock data recovery circuit 110 to receive the clock signal CLK and the data signal DS1. The digital circuit 120 may process the data signal DS1 to generate a processed data signal DS2, e.g., pixel data. In addition, the digital circuit 120 may generate the power-off signal CPS according to the data signal DS1. For example, in the present embodiment, the digital circuit 120 can detect the vertical blanking start signal VBK in the data signal DS1, and generate the power-off signal CPS to the power control circuit 140 according to the vertical blanking start signal VBK. In other embodiments, the digital circuit 120 may detect other information in the data signal DS1 and generate the power-off signal CPS based on the other information.
The driving circuit 150 is coupled to the digital circuit 120 to receive the clock signal CLK. The driving circuit 150 is further coupled to the digital circuit 120 to receive the data signal DS2. The driving circuit 150 can generate source driving signals S1 to Sn according to the clock signal CLK and the data signal DS2, and the driving circuit 150 can drive the display panel 170 by using the source driving signals S1 to Sn. The present embodiment is not limited to the implementation of the driving circuit 150. For example, in some embodiments, the driving circuit 150 may include a Shift Register (Shift Register), a Data Register (Data Register), a Level Shifter (Level Shifter), a Digital-to-Analog Converter (DAC), and an Output Buffer (Output Buffer), which are well known to those skilled in the art, and related operations of the components are not described herein.
On the other hand, the signal detection circuit 130 is coupled to the external device 160 to receive the control signal CS. The control signal CS has phase (time point) information of "the vertical blanking period has ended", so the signal detection circuit 130 can generate the start power signal SPS according to the control signal CS. For example, in some application scenarios, the control signal CS with a first logic level (e.g., high level) may indicate during valid data in the original data signal TX, while the control signal CS with a second logic level (e.g., low level) may indicate during invalid data (e.g., training pattern) in the original data signal TX. Based on this, the signal detection circuit 130 may detect a falling edge of the control signal CS, and generate the power-on/power-off reset circuit for starting the power signal SPS to the power control circuit 140 according to the falling edge of the control signal CS. In other application scenarios, a control signal CS with a low level may indicate during valid data in the original data signal TX, while a control signal CS with a high level may indicate during invalid data (e.g., training pattern) in the original data signal TX. Based on this, the signal detection circuit 130 may detect a rising edge of the control signal CS, and generate the power-on/power-off reset circuit for starting the power signal SPS to the power control circuit 140 according to the rising edge of the control signal CS.
The power on/off reset circuit of the power control circuit 140 is coupled to the digital circuit 120 to receive the power off signal CPS. The power on/off reset circuit of the power control circuit 140 is coupled to the signal detection circuit 130 to receive the start power signal SPS. The power-on/power-off reset circuit of the power control circuit 140 may control the power supply of the clock data recovery circuit 110, the digital circuit 120, and/or the driving circuit 150. The power control circuit 140 can provide the power control signals PCS1, PCS2 and PCS3 to the clock data recovery circuit 110, the digital circuit 120 and the driving circuit 150 according to the power-off signal CPS and the power-on signal SPS, respectively, so as to control the clock data recovery circuit 110, the digital circuit 120 and the driving circuit 150 to operate in a power-off state or a power-on state. For example, the power control circuit 140 may power down the clock data recovery circuit 110 during the non-display time interval and power up the clock data recovery circuit 110 during the display time interval.
For details of the operation of the source driver 100, please refer to fig. 1 and fig. 2. Fig. 2 is a schematic diagram illustrating signal timing of the source driver 100 shown in fig. 1 according to an embodiment of the invention. The non-display time interval TND may include a vertical blanking period and/or other times, depending on design requirements. The embodiment shown in fig. 2 will take the vertical blanking period as an example of the non-display time interval TND. In detail, in the present embodiment, the digital circuit 120 may detect the vertical blanking start signal VBK of the data signal DS1 in the vertical blanking time interval TBK. The vertical blanking start signal VBK means the start of a vertical blanking period (non-display time period TND). Therefore, the digital circuit 120 can set the power-off signal CPS to be in an enabled (e.g. high voltage) state during the vertical blanking interval TBK according to the vertical blanking start signal VBK. At this time, the signal detection circuit 130 may receive the control signal CS. Because the control signal CS remains at a high level during the vertical blanking period, the signal detection circuit 130 may keep the power-on signal SPS at a disabled (e.g., low voltage level) state.
In the case where the power-off signal CPS is in an enabled state, the power-on/power-off reset circuit of the power control circuit 140 can know that a power-off reset event has occurred. Therefore, the power-on/power-off reset circuit of the power control circuit 140 can provide the power control signals PCS 1-PCS 3 with disabled (e.g. low voltage level) state to the corresponding clock data recovery circuit 110, digital circuit 120 and driving circuit 150 according to the power-off signal CPS, so that the clock data recovery circuit 110, digital circuit 120 and driving circuit 150 are powered off.
On the other hand, in the embodiment shown in fig. 2, the control signal CS having a high level may indicate a valid data period in the original data signal TX, and the control signal CS having a low level may indicate an invalid data period (e.g., training pattern) in the original data signal TX. The falling edge of the control signal CS means the end of the vertical blanking period (non-display time interval TND). Therefore, the signal detection circuit 130 can detect the falling edge of the control signal CS, and generate the power-on/power-off reset circuit with the enable (e.g. high voltage level) state of the power-on power signal SPS to the power control circuit 140 at the end time TEND of the non-display time interval TND according to the falling edge of the control signal CS.
In the event that the power-on power signal SPS is enabled, the power-on/power-off reset circuit of the power control circuit 140 may be aware that a power-on reset event has occurred. Therefore, the power-on/power-off reset circuit of the power control circuit 140 can provide the power control signals PCS 1-PCS 3 with enabled (e.g. high voltage) states to the corresponding clock data recovery circuit 110, digital circuit 120 and driving circuit 150 according to the power-on power signal SPS, so that the clock data recovery circuit 110, digital circuit 120 and driving circuit 150 are powered back.
In other words, in the present embodiment, the source driver 100 can determine the start and end of the vertical blanking period (non-display time period TND) through the digital circuit 120 and the signal detection circuit 130. When the digital circuit 120 detects the start of the vertical blanking period (non-display period TND) according to the vertical blanking period TBK, the digital circuit 120 may trigger a power-off reset event of the power-on/power-off reset circuit of the power control circuit 140 by cutting off the power signal CPS. Therefore, the power-on/power-off reset circuit of the power control circuit 140 can perform power-off operation on the clock data recovery circuit 110, the digital circuit 120 and the driving circuit 150 to reduce the power consumption of the source driver 100. When the signal detection circuit 130 detects the end of the vertical blanking period (non-display time period TND) according to the falling edge of the control signal CS, the signal detection circuit 130 may trigger a power-on reset event of the power-on/power-off reset circuit of the power control circuit 140 by activating the power signal SPS. Therefore, the power-on/power-off reset circuit of the power control circuit 140 can perform the power-on operation of the clock data recovery circuit 110, the digital circuit 120 and the driving circuit 150, so that the clock data recovery circuit 110, the digital circuit 120 and the driving circuit 150 restart the related circuits at the end time TEND.
Then, when the source driver 100 is operated in the display time interval TD, the clock data recovery circuit 110, the digital circuit 120 and the driving circuit 150 are all operated in the normal operation state according to the corresponding power control signals PCS 1-PCS 3, so that the driving circuit 150 can normally generate the source driving signals S1-Sn according to the clock signal CLK and the data signal DS2. The driving circuit 150 can drive the display panel 170 by using the source driving signals S1 to Sn so that the display panel 170 displays a picture in the display time period TD.
It should be noted that, in the present embodiment, a person skilled in the art can determine which internal components of the source driver 100 are powered off or powered back on according to the design requirements of the source driver 100. For example, when the source driver 100 operates in the non-display time interval TND (e.g. the vertical blanking interval), the power control circuit 140 of the present embodiment may power down at least one or all of the clock data recovery circuit 110, the digital circuit 120 and the driving circuit 150 according to the power-off signal CPS. In contrast, when the non-display time period TND is over, the power control circuit 140 may re-power at least one or all of the clock data recovery circuit 110, the digital circuit 120 and the driving circuit 150 according to the start power signal SPS.
As can be seen from the above description, the power control circuit 140 of the source driver 100 of the present embodiment can cut off the power of the clock data recovery circuit 110, the digital circuit 120 and the driving circuit 150 according to the power-off signal CPS in the non-display time interval TND, so as to reduce the power consumption of the source driver 100. On the other hand, when the non-display time period TND is over, the power control circuit 140 of the source driver 100 can resume the power of the clock data recovery circuit 110, the digital circuit 120 and the driving circuit 150 according to the start-up power signal SPS, so that the clock data recovery circuit 110, the digital circuit 120 and the driving circuit 150 can start the related circuit operation again after the end time period TEND of the non-display time period TND.
Fig. 3 is a flowchart of an operation method of the source driver 100 according to an embodiment of the invention. Referring to fig. 1 and 3, in step S310, the source driver 100 can generate the clock signal CLK and the data signal DS1 according to the original data signal TX through the clock data recovery circuit 110. In step S320, the source driver 100 can generate the power-off signal CPS according to the data signal DS1 by the digital circuit 120. In step S330, the source driver 100 may power off the clock data recovery circuit 110 by the power control circuit 140 according to the power-off signal CPS.
Next, in step S340, the source driver 100 may generate the start power signal SPS according to the control signal CS through the signal detection circuit 130. In step S350, the source driver 100 can power up the clock data recovery circuit 110 by the power control circuit 140 according to the start power signal SPS.
Details of the implementation of each step are described in the foregoing embodiments and implementations, and are not repeated herein.
In summary, the source driver according to the embodiments of the invention can be powered off by the power control circuit according to the power-off signal to power off at least one or all of the clock data recovery circuit, the digital circuit and the driving circuit. And, the power control circuit is utilized to make at least one or all of the clock data recovery circuit, the digital circuit and the driving circuit be powered back according to the starting power signal. Therefore, the source driver according to the embodiments of the present invention can reduce the power consumption of the source driver during the non-display time interval, thereby achieving the power saving effect.
Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather, it should be apparent to one skilled in the art that various changes and modifications can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (8)
1. A source driver, comprising:
the clock data recovery circuit is used for receiving an original data signal from an external device and generating a clock signal and a first data signal according to the original data signal;
the digital circuit is coupled to the clock data recovery circuit to receive the clock signal and the first data signal and generate a cut-off power signal according to the first data signal;
the signal detection circuit is used for receiving a control signal from the external device and generating a starting power supply signal according to the control signal; and
the power control circuit is coupled to the digital circuit to receive the cut-off power signal and coupled to the signal detection circuit to receive the start-up power signal, wherein the power control circuit cuts off the power of the clock data recovery circuit according to the cut-off power signal, and the power control circuit re-electrifies the clock data recovery circuit according to the start-up power signal.
2. The source driver of claim 1, wherein the power control circuit powers down the clock data recovery circuit during non-display time intervals.
3. The source driver of claim 2, wherein the non-display time interval comprises a vertical blanking interval.
4. The source driver of claim 1, wherein the digital circuit detects a vertical blanking start signal in the first data signal and generates the power-off signal to the power control circuit according to the vertical blanking start signal.
5. The source driver of claim 1, wherein the signal detection circuit detects a falling edge of the control signal and generates the enable power signal to the power control circuit according to the falling edge of the control signal.
6. The source driver of claim 1, wherein the power control circuit further powers down the digital circuit in response to the power-off signal, and the power control circuit further powers back up the digital circuit in response to the power-on signal.
7. The source driver of claim 1, wherein the digital circuit outputs a second data signal in accordance with the first data signal, the source driver further comprising:
a driving circuit coupled to the digital circuit to receive the clock signal and coupled to the digital circuit to receive the second data signal, wherein the driving circuit is configured to drive the display panel according to the second data signal;
the power supply control circuit also enables the driving circuit to be powered off according to the power-off signal, and the power supply control circuit also enables the driving circuit to be powered back on according to the starting power-on signal.
8. The source driver of claim 1, wherein the power control circuit comprises a power on/off reset circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811516972.0A CN111312135B (en) | 2018-12-12 | 2018-12-12 | Source driver and operation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811516972.0A CN111312135B (en) | 2018-12-12 | 2018-12-12 | Source driver and operation method thereof |
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| CN111312135A CN111312135A (en) | 2020-06-19 |
| CN111312135B true CN111312135B (en) | 2024-01-19 |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112951134B (en) * | 2021-04-20 | 2022-09-20 | 合肥京东方显示技术有限公司 | Clock recovery device, source electrode driving circuit, display panel and equipment |
| CN114220380B (en) * | 2022-02-22 | 2022-06-10 | 深圳通锐微电子技术有限公司 | Calibration digital circuit, source driver and display panel |
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| US6548991B1 (en) * | 2002-01-19 | 2003-04-15 | National Semiconductor Corporation | Adaptive voltage scaling power supply for use in a digital processing component and method of operating the same |
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